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bc4e814e | 1 | /* |
2 | * arch/arm/mach-spear3xx/spear310.c | |
3 | * | |
4 | * SPEAr310 machine source file | |
5 | * | |
c5fa4fdc | 6 | * Copyright (C) 2009-2012 ST Microelectronics |
10d8935f | 7 | * Viresh Kumar <viresh.linux@gmail.com> |
bc4e814e | 8 | * |
9 | * This file is licensed under the terms of the GNU General Public | |
10 | * License version 2. This program is licensed "as is" without any | |
11 | * warranty of any kind, whether express or implied. | |
12 | */ | |
13 | ||
5fb00f96 VK |
14 | #define pr_fmt(fmt) "SPEAr310: " fmt |
15 | ||
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16 | #include <linux/amba/pl08x.h> |
17 | #include <linux/amba/serial.h> | |
e9c51558 | 18 | #include <linux/irqchip.h> |
c5fa4fdc | 19 | #include <linux/of_platform.h> |
c5fa4fdc | 20 | #include <asm/mach/arch.h> |
bc4e814e | 21 | #include <mach/generic.h> |
5019f0b1 AB |
22 | #include <mach/spear.h> |
23 | ||
24 | #define SPEAR310_UART1_BASE UL(0xB2000000) | |
25 | #define SPEAR310_UART2_BASE UL(0xB2080000) | |
26 | #define SPEAR310_UART3_BASE UL(0xB2100000) | |
27 | #define SPEAR310_UART4_BASE UL(0xB2180000) | |
28 | #define SPEAR310_UART5_BASE UL(0xB2200000) | |
4c18e77f | 29 | |
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30 | /* DMAC platform data's slave info */ |
31 | struct pl08x_channel_data spear310_dma_info[] = { | |
32 | { | |
33 | .bus_id = "uart0_rx", | |
34 | .min_signal = 2, | |
35 | .max_signal = 2, | |
36 | .muxval = 0, | |
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37 | .periph_buses = PL08X_AHB1, |
38 | }, { | |
39 | .bus_id = "uart0_tx", | |
40 | .min_signal = 3, | |
41 | .max_signal = 3, | |
42 | .muxval = 0, | |
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43 | .periph_buses = PL08X_AHB1, |
44 | }, { | |
45 | .bus_id = "ssp0_rx", | |
46 | .min_signal = 8, | |
47 | .max_signal = 8, | |
48 | .muxval = 0, | |
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49 | .periph_buses = PL08X_AHB1, |
50 | }, { | |
51 | .bus_id = "ssp0_tx", | |
52 | .min_signal = 9, | |
53 | .max_signal = 9, | |
54 | .muxval = 0, | |
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55 | .periph_buses = PL08X_AHB1, |
56 | }, { | |
57 | .bus_id = "i2c_rx", | |
58 | .min_signal = 10, | |
59 | .max_signal = 10, | |
60 | .muxval = 0, | |
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61 | .periph_buses = PL08X_AHB1, |
62 | }, { | |
63 | .bus_id = "i2c_tx", | |
64 | .min_signal = 11, | |
65 | .max_signal = 11, | |
66 | .muxval = 0, | |
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67 | .periph_buses = PL08X_AHB1, |
68 | }, { | |
69 | .bus_id = "irda", | |
70 | .min_signal = 12, | |
71 | .max_signal = 12, | |
72 | .muxval = 0, | |
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73 | .periph_buses = PL08X_AHB1, |
74 | }, { | |
75 | .bus_id = "adc", | |
76 | .min_signal = 13, | |
77 | .max_signal = 13, | |
78 | .muxval = 0, | |
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79 | .periph_buses = PL08X_AHB1, |
80 | }, { | |
81 | .bus_id = "to_jpeg", | |
82 | .min_signal = 14, | |
83 | .max_signal = 14, | |
84 | .muxval = 0, | |
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85 | .periph_buses = PL08X_AHB1, |
86 | }, { | |
87 | .bus_id = "from_jpeg", | |
88 | .min_signal = 15, | |
89 | .max_signal = 15, | |
90 | .muxval = 0, | |
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91 | .periph_buses = PL08X_AHB1, |
92 | }, { | |
93 | .bus_id = "uart1_rx", | |
94 | .min_signal = 0, | |
95 | .max_signal = 0, | |
96 | .muxval = 1, | |
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97 | .periph_buses = PL08X_AHB1, |
98 | }, { | |
99 | .bus_id = "uart1_tx", | |
100 | .min_signal = 1, | |
101 | .max_signal = 1, | |
102 | .muxval = 1, | |
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103 | .periph_buses = PL08X_AHB1, |
104 | }, { | |
105 | .bus_id = "uart2_rx", | |
106 | .min_signal = 2, | |
107 | .max_signal = 2, | |
108 | .muxval = 1, | |
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109 | .periph_buses = PL08X_AHB1, |
110 | }, { | |
111 | .bus_id = "uart2_tx", | |
112 | .min_signal = 3, | |
113 | .max_signal = 3, | |
114 | .muxval = 1, | |
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115 | .periph_buses = PL08X_AHB1, |
116 | }, { | |
117 | .bus_id = "uart3_rx", | |
118 | .min_signal = 4, | |
119 | .max_signal = 4, | |
120 | .muxval = 1, | |
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121 | .periph_buses = PL08X_AHB1, |
122 | }, { | |
123 | .bus_id = "uart3_tx", | |
124 | .min_signal = 5, | |
125 | .max_signal = 5, | |
126 | .muxval = 1, | |
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127 | .periph_buses = PL08X_AHB1, |
128 | }, { | |
129 | .bus_id = "uart4_rx", | |
130 | .min_signal = 6, | |
131 | .max_signal = 6, | |
132 | .muxval = 1, | |
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133 | .periph_buses = PL08X_AHB1, |
134 | }, { | |
135 | .bus_id = "uart4_tx", | |
136 | .min_signal = 7, | |
137 | .max_signal = 7, | |
138 | .muxval = 1, | |
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139 | .periph_buses = PL08X_AHB1, |
140 | }, { | |
141 | .bus_id = "uart5_rx", | |
142 | .min_signal = 8, | |
143 | .max_signal = 8, | |
144 | .muxval = 1, | |
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145 | .periph_buses = PL08X_AHB1, |
146 | }, { | |
147 | .bus_id = "uart5_tx", | |
148 | .min_signal = 9, | |
149 | .max_signal = 9, | |
150 | .muxval = 1, | |
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151 | .periph_buses = PL08X_AHB1, |
152 | }, { | |
153 | .bus_id = "ras5_rx", | |
154 | .min_signal = 10, | |
155 | .max_signal = 10, | |
156 | .muxval = 1, | |
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157 | .periph_buses = PL08X_AHB1, |
158 | }, { | |
159 | .bus_id = "ras5_tx", | |
160 | .min_signal = 11, | |
161 | .max_signal = 11, | |
162 | .muxval = 1, | |
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163 | .periph_buses = PL08X_AHB1, |
164 | }, { | |
165 | .bus_id = "ras6_rx", | |
166 | .min_signal = 12, | |
167 | .max_signal = 12, | |
168 | .muxval = 1, | |
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169 | .periph_buses = PL08X_AHB1, |
170 | }, { | |
171 | .bus_id = "ras6_tx", | |
172 | .min_signal = 13, | |
173 | .max_signal = 13, | |
174 | .muxval = 1, | |
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175 | .periph_buses = PL08X_AHB1, |
176 | }, { | |
177 | .bus_id = "ras7_rx", | |
178 | .min_signal = 14, | |
179 | .max_signal = 14, | |
180 | .muxval = 1, | |
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181 | .periph_buses = PL08X_AHB1, |
182 | }, { | |
183 | .bus_id = "ras7_tx", | |
184 | .min_signal = 15, | |
185 | .max_signal = 15, | |
186 | .muxval = 1, | |
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187 | .periph_buses = PL08X_AHB1, |
188 | }, | |
189 | }; | |
190 | ||
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191 | /* uart devices plat data */ |
192 | static struct amba_pl011_data spear310_uart_data[] = { | |
193 | { | |
194 | .dma_filter = pl08x_filter_id, | |
195 | .dma_tx_param = "uart1_tx", | |
196 | .dma_rx_param = "uart1_rx", | |
197 | }, { | |
198 | .dma_filter = pl08x_filter_id, | |
199 | .dma_tx_param = "uart2_tx", | |
200 | .dma_rx_param = "uart2_rx", | |
201 | }, { | |
202 | .dma_filter = pl08x_filter_id, | |
203 | .dma_tx_param = "uart3_tx", | |
204 | .dma_rx_param = "uart3_rx", | |
205 | }, { | |
206 | .dma_filter = pl08x_filter_id, | |
207 | .dma_tx_param = "uart4_tx", | |
208 | .dma_rx_param = "uart4_rx", | |
209 | }, { | |
210 | .dma_filter = pl08x_filter_id, | |
211 | .dma_tx_param = "uart5_tx", | |
212 | .dma_rx_param = "uart5_rx", | |
213 | }, | |
214 | }; | |
c2c07831 | 215 | |
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216 | /* Add SPEAr310 auxdata to pass platform data */ |
217 | static struct of_dev_auxdata spear310_auxdata_lookup[] __initdata = { | |
218 | OF_DEV_AUXDATA("arm,pl022", SPEAR3XX_ICM1_SSP_BASE, NULL, | |
219 | &pl022_plat_data), | |
d42799b7 | 220 | OF_DEV_AUXDATA("arm,pl080", SPEAR_ICM3_DMA_BASE, NULL, |
0b7ee717 | 221 | &pl080_plat_data), |
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222 | OF_DEV_AUXDATA("arm,pl011", SPEAR310_UART1_BASE, NULL, |
223 | &spear310_uart_data[0]), | |
224 | OF_DEV_AUXDATA("arm,pl011", SPEAR310_UART2_BASE, NULL, | |
225 | &spear310_uart_data[1]), | |
226 | OF_DEV_AUXDATA("arm,pl011", SPEAR310_UART3_BASE, NULL, | |
227 | &spear310_uart_data[2]), | |
228 | OF_DEV_AUXDATA("arm,pl011", SPEAR310_UART4_BASE, NULL, | |
229 | &spear310_uart_data[3]), | |
230 | OF_DEV_AUXDATA("arm,pl011", SPEAR310_UART5_BASE, NULL, | |
231 | &spear310_uart_data[4]), | |
232 | {} | |
233 | }; | |
234 | ||
235 | static void __init spear310_dt_init(void) | |
bc4e814e | 236 | { |
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237 | pl080_plat_data.slave_channels = spear310_dma_info; |
238 | pl080_plat_data.num_slave_channels = ARRAY_SIZE(spear310_dma_info); | |
239 | ||
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240 | of_platform_populate(NULL, of_default_bus_match_table, |
241 | spear310_auxdata_lookup, NULL); | |
70f4c0bf | 242 | } |
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243 | |
244 | static const char * const spear310_dt_board_compat[] = { | |
245 | "st,spear310", | |
246 | "st,spear310-evb", | |
247 | NULL, | |
248 | }; | |
249 | ||
250 | static void __init spear310_map_io(void) | |
251 | { | |
252 | spear3xx_map_io(); | |
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253 | } |
254 | ||
255 | DT_MACHINE_START(SPEAR310_DT, "ST SPEAr310 SoC with Flattened Device Tree") | |
256 | .map_io = spear310_map_io, | |
e9c51558 | 257 | .init_irq = irqchip_init, |
6bb27d73 | 258 | .init_time = spear3xx_timer_init, |
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259 | .init_machine = spear310_dt_init, |
260 | .restart = spear_restart, | |
261 | .dt_compat = spear310_dt_board_compat, | |
262 | MACHINE_END |