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bc4e814e | 1 | /* |
2 | * arch/arm/mach-spear3xx/spear3xx.c | |
3 | * | |
4 | * SPEAr3XX machines common source file | |
5 | * | |
c5fa4fdc VK |
6 | * Copyright (C) 2009-2012 ST Microelectronics |
7 | * Viresh Kumar <viresh.kumar@st.com> | |
bc4e814e | 8 | * |
9 | * This file is licensed under the terms of the GNU General Public | |
10 | * License version 2. This program is licensed "as is" without any | |
11 | * warranty of any kind, whether express or implied. | |
12 | */ | |
13 | ||
5fb00f96 VK |
14 | #define pr_fmt(fmt) "SPEAr3xx: " fmt |
15 | ||
c5fa4fdc VK |
16 | #include <linux/amba/pl022.h> |
17 | #include <linux/amba/pl08x.h> | |
18 | #include <linux/of_irq.h> | |
bc4e814e | 19 | #include <linux/io.h> |
20 | #include <asm/hardware/vic.h> | |
bc4e814e | 21 | #include <mach/generic.h> |
02aa06bc | 22 | #include <mach/hardware.h> |
bc4e814e | 23 | |
70f4c0bf | 24 | /* pad multiplexing support */ |
25 | /* devices */ | |
6618c3ad | 26 | static struct pmx_dev_mode pmx_firda_modes[] = { |
70f4c0bf | 27 | { |
28 | .ids = 0xffffffff, | |
29 | .mask = PMX_FIRDA_MASK, | |
30 | }, | |
31 | }; | |
32 | ||
6618c3ad | 33 | struct pmx_dev spear3xx_pmx_firda = { |
70f4c0bf | 34 | .name = "firda", |
35 | .modes = pmx_firda_modes, | |
36 | .mode_count = ARRAY_SIZE(pmx_firda_modes), | |
37 | .enb_on_reset = 0, | |
38 | }; | |
39 | ||
6618c3ad | 40 | static struct pmx_dev_mode pmx_i2c_modes[] = { |
70f4c0bf | 41 | { |
42 | .ids = 0xffffffff, | |
43 | .mask = PMX_I2C_MASK, | |
44 | }, | |
45 | }; | |
46 | ||
6618c3ad | 47 | struct pmx_dev spear3xx_pmx_i2c = { |
70f4c0bf | 48 | .name = "i2c", |
49 | .modes = pmx_i2c_modes, | |
50 | .mode_count = ARRAY_SIZE(pmx_i2c_modes), | |
51 | .enb_on_reset = 0, | |
52 | }; | |
53 | ||
6618c3ad | 54 | static struct pmx_dev_mode pmx_ssp_cs_modes[] = { |
70f4c0bf | 55 | { |
56 | .ids = 0xffffffff, | |
57 | .mask = PMX_SSP_CS_MASK, | |
58 | }, | |
59 | }; | |
60 | ||
6618c3ad | 61 | struct pmx_dev spear3xx_pmx_ssp_cs = { |
70f4c0bf | 62 | .name = "ssp_chip_selects", |
63 | .modes = pmx_ssp_cs_modes, | |
64 | .mode_count = ARRAY_SIZE(pmx_ssp_cs_modes), | |
65 | .enb_on_reset = 0, | |
66 | }; | |
67 | ||
6618c3ad | 68 | static struct pmx_dev_mode pmx_ssp_modes[] = { |
70f4c0bf | 69 | { |
70 | .ids = 0xffffffff, | |
71 | .mask = PMX_SSP_MASK, | |
72 | }, | |
73 | }; | |
74 | ||
6618c3ad | 75 | struct pmx_dev spear3xx_pmx_ssp = { |
70f4c0bf | 76 | .name = "ssp", |
77 | .modes = pmx_ssp_modes, | |
78 | .mode_count = ARRAY_SIZE(pmx_ssp_modes), | |
79 | .enb_on_reset = 0, | |
80 | }; | |
81 | ||
6618c3ad | 82 | static struct pmx_dev_mode pmx_mii_modes[] = { |
70f4c0bf | 83 | { |
84 | .ids = 0xffffffff, | |
85 | .mask = PMX_MII_MASK, | |
86 | }, | |
87 | }; | |
88 | ||
6618c3ad | 89 | struct pmx_dev spear3xx_pmx_mii = { |
70f4c0bf | 90 | .name = "mii", |
91 | .modes = pmx_mii_modes, | |
92 | .mode_count = ARRAY_SIZE(pmx_mii_modes), | |
93 | .enb_on_reset = 0, | |
94 | }; | |
95 | ||
6618c3ad | 96 | static struct pmx_dev_mode pmx_gpio_pin0_modes[] = { |
70f4c0bf | 97 | { |
98 | .ids = 0xffffffff, | |
99 | .mask = PMX_GPIO_PIN0_MASK, | |
100 | }, | |
101 | }; | |
102 | ||
6618c3ad | 103 | struct pmx_dev spear3xx_pmx_gpio_pin0 = { |
70f4c0bf | 104 | .name = "gpio_pin0", |
105 | .modes = pmx_gpio_pin0_modes, | |
106 | .mode_count = ARRAY_SIZE(pmx_gpio_pin0_modes), | |
107 | .enb_on_reset = 0, | |
108 | }; | |
109 | ||
6618c3ad | 110 | static struct pmx_dev_mode pmx_gpio_pin1_modes[] = { |
70f4c0bf | 111 | { |
112 | .ids = 0xffffffff, | |
113 | .mask = PMX_GPIO_PIN1_MASK, | |
114 | }, | |
115 | }; | |
116 | ||
6618c3ad | 117 | struct pmx_dev spear3xx_pmx_gpio_pin1 = { |
70f4c0bf | 118 | .name = "gpio_pin1", |
119 | .modes = pmx_gpio_pin1_modes, | |
120 | .mode_count = ARRAY_SIZE(pmx_gpio_pin1_modes), | |
121 | .enb_on_reset = 0, | |
122 | }; | |
123 | ||
6618c3ad | 124 | static struct pmx_dev_mode pmx_gpio_pin2_modes[] = { |
70f4c0bf | 125 | { |
126 | .ids = 0xffffffff, | |
127 | .mask = PMX_GPIO_PIN2_MASK, | |
128 | }, | |
129 | }; | |
130 | ||
6618c3ad | 131 | struct pmx_dev spear3xx_pmx_gpio_pin2 = { |
70f4c0bf | 132 | .name = "gpio_pin2", |
133 | .modes = pmx_gpio_pin2_modes, | |
134 | .mode_count = ARRAY_SIZE(pmx_gpio_pin2_modes), | |
135 | .enb_on_reset = 0, | |
136 | }; | |
137 | ||
6618c3ad | 138 | static struct pmx_dev_mode pmx_gpio_pin3_modes[] = { |
70f4c0bf | 139 | { |
140 | .ids = 0xffffffff, | |
141 | .mask = PMX_GPIO_PIN3_MASK, | |
142 | }, | |
143 | }; | |
144 | ||
6618c3ad | 145 | struct pmx_dev spear3xx_pmx_gpio_pin3 = { |
70f4c0bf | 146 | .name = "gpio_pin3", |
147 | .modes = pmx_gpio_pin3_modes, | |
148 | .mode_count = ARRAY_SIZE(pmx_gpio_pin3_modes), | |
149 | .enb_on_reset = 0, | |
150 | }; | |
151 | ||
6618c3ad | 152 | static struct pmx_dev_mode pmx_gpio_pin4_modes[] = { |
70f4c0bf | 153 | { |
154 | .ids = 0xffffffff, | |
155 | .mask = PMX_GPIO_PIN4_MASK, | |
156 | }, | |
157 | }; | |
158 | ||
6618c3ad | 159 | struct pmx_dev spear3xx_pmx_gpio_pin4 = { |
70f4c0bf | 160 | .name = "gpio_pin4", |
161 | .modes = pmx_gpio_pin4_modes, | |
162 | .mode_count = ARRAY_SIZE(pmx_gpio_pin4_modes), | |
163 | .enb_on_reset = 0, | |
164 | }; | |
165 | ||
6618c3ad | 166 | static struct pmx_dev_mode pmx_gpio_pin5_modes[] = { |
70f4c0bf | 167 | { |
168 | .ids = 0xffffffff, | |
169 | .mask = PMX_GPIO_PIN5_MASK, | |
170 | }, | |
171 | }; | |
172 | ||
6618c3ad | 173 | struct pmx_dev spear3xx_pmx_gpio_pin5 = { |
70f4c0bf | 174 | .name = "gpio_pin5", |
175 | .modes = pmx_gpio_pin5_modes, | |
176 | .mode_count = ARRAY_SIZE(pmx_gpio_pin5_modes), | |
177 | .enb_on_reset = 0, | |
178 | }; | |
179 | ||
6618c3ad | 180 | static struct pmx_dev_mode pmx_uart0_modem_modes[] = { |
70f4c0bf | 181 | { |
182 | .ids = 0xffffffff, | |
183 | .mask = PMX_UART0_MODEM_MASK, | |
184 | }, | |
185 | }; | |
186 | ||
6618c3ad | 187 | struct pmx_dev spear3xx_pmx_uart0_modem = { |
70f4c0bf | 188 | .name = "uart0_modem", |
189 | .modes = pmx_uart0_modem_modes, | |
190 | .mode_count = ARRAY_SIZE(pmx_uart0_modem_modes), | |
191 | .enb_on_reset = 0, | |
192 | }; | |
193 | ||
6618c3ad | 194 | static struct pmx_dev_mode pmx_uart0_modes[] = { |
70f4c0bf | 195 | { |
196 | .ids = 0xffffffff, | |
197 | .mask = PMX_UART0_MASK, | |
198 | }, | |
199 | }; | |
200 | ||
6618c3ad | 201 | struct pmx_dev spear3xx_pmx_uart0 = { |
70f4c0bf | 202 | .name = "uart0", |
203 | .modes = pmx_uart0_modes, | |
204 | .mode_count = ARRAY_SIZE(pmx_uart0_modes), | |
205 | .enb_on_reset = 0, | |
206 | }; | |
207 | ||
6618c3ad | 208 | static struct pmx_dev_mode pmx_timer_3_4_modes[] = { |
70f4c0bf | 209 | { |
210 | .ids = 0xffffffff, | |
211 | .mask = PMX_TIMER_3_4_MASK, | |
212 | }, | |
213 | }; | |
214 | ||
6618c3ad | 215 | struct pmx_dev spear3xx_pmx_timer_3_4 = { |
70f4c0bf | 216 | .name = "timer_3_4", |
217 | .modes = pmx_timer_3_4_modes, | |
218 | .mode_count = ARRAY_SIZE(pmx_timer_3_4_modes), | |
219 | .enb_on_reset = 0, | |
220 | }; | |
221 | ||
6618c3ad | 222 | static struct pmx_dev_mode pmx_timer_1_2_modes[] = { |
70f4c0bf | 223 | { |
224 | .ids = 0xffffffff, | |
225 | .mask = PMX_TIMER_1_2_MASK, | |
226 | }, | |
227 | }; | |
228 | ||
6618c3ad | 229 | struct pmx_dev spear3xx_pmx_timer_1_2 = { |
70f4c0bf | 230 | .name = "timer_1_2", |
231 | .modes = pmx_timer_1_2_modes, | |
232 | .mode_count = ARRAY_SIZE(pmx_timer_1_2_modes), | |
233 | .enb_on_reset = 0, | |
234 | }; | |
235 | ||
236 | #if defined(CONFIG_MACH_SPEAR310) || defined(CONFIG_MACH_SPEAR320) | |
237 | /* plgpios devices */ | |
6618c3ad | 238 | static struct pmx_dev_mode pmx_plgpio_0_1_modes[] = { |
70f4c0bf | 239 | { |
240 | .ids = 0x00, | |
241 | .mask = PMX_FIRDA_MASK, | |
242 | }, | |
243 | }; | |
244 | ||
6618c3ad | 245 | struct pmx_dev spear3xx_pmx_plgpio_0_1 = { |
70f4c0bf | 246 | .name = "plgpio 0 and 1", |
247 | .modes = pmx_plgpio_0_1_modes, | |
248 | .mode_count = ARRAY_SIZE(pmx_plgpio_0_1_modes), | |
249 | .enb_on_reset = 1, | |
250 | }; | |
251 | ||
6618c3ad | 252 | static struct pmx_dev_mode pmx_plgpio_2_3_modes[] = { |
70f4c0bf | 253 | { |
254 | .ids = 0x00, | |
255 | .mask = PMX_UART0_MASK, | |
256 | }, | |
257 | }; | |
258 | ||
6618c3ad | 259 | struct pmx_dev spear3xx_pmx_plgpio_2_3 = { |
70f4c0bf | 260 | .name = "plgpio 2 and 3", |
261 | .modes = pmx_plgpio_2_3_modes, | |
262 | .mode_count = ARRAY_SIZE(pmx_plgpio_2_3_modes), | |
263 | .enb_on_reset = 1, | |
264 | }; | |
265 | ||
6618c3ad | 266 | static struct pmx_dev_mode pmx_plgpio_4_5_modes[] = { |
70f4c0bf | 267 | { |
268 | .ids = 0x00, | |
269 | .mask = PMX_I2C_MASK, | |
270 | }, | |
271 | }; | |
272 | ||
6618c3ad | 273 | struct pmx_dev spear3xx_pmx_plgpio_4_5 = { |
70f4c0bf | 274 | .name = "plgpio 4 and 5", |
275 | .modes = pmx_plgpio_4_5_modes, | |
276 | .mode_count = ARRAY_SIZE(pmx_plgpio_4_5_modes), | |
277 | .enb_on_reset = 1, | |
278 | }; | |
279 | ||
6618c3ad | 280 | static struct pmx_dev_mode pmx_plgpio_6_9_modes[] = { |
70f4c0bf | 281 | { |
282 | .ids = 0x00, | |
283 | .mask = PMX_SSP_MASK, | |
284 | }, | |
285 | }; | |
286 | ||
6618c3ad | 287 | struct pmx_dev spear3xx_pmx_plgpio_6_9 = { |
70f4c0bf | 288 | .name = "plgpio 6 to 9", |
289 | .modes = pmx_plgpio_6_9_modes, | |
290 | .mode_count = ARRAY_SIZE(pmx_plgpio_6_9_modes), | |
291 | .enb_on_reset = 1, | |
292 | }; | |
293 | ||
6618c3ad | 294 | static struct pmx_dev_mode pmx_plgpio_10_27_modes[] = { |
70f4c0bf | 295 | { |
296 | .ids = 0x00, | |
297 | .mask = PMX_MII_MASK, | |
298 | }, | |
299 | }; | |
300 | ||
6618c3ad | 301 | struct pmx_dev spear3xx_pmx_plgpio_10_27 = { |
70f4c0bf | 302 | .name = "plgpio 10 to 27", |
303 | .modes = pmx_plgpio_10_27_modes, | |
304 | .mode_count = ARRAY_SIZE(pmx_plgpio_10_27_modes), | |
305 | .enb_on_reset = 1, | |
306 | }; | |
307 | ||
6618c3ad | 308 | static struct pmx_dev_mode pmx_plgpio_28_modes[] = { |
70f4c0bf | 309 | { |
310 | .ids = 0x00, | |
311 | .mask = PMX_GPIO_PIN0_MASK, | |
312 | }, | |
313 | }; | |
314 | ||
6618c3ad | 315 | struct pmx_dev spear3xx_pmx_plgpio_28 = { |
70f4c0bf | 316 | .name = "plgpio 28", |
317 | .modes = pmx_plgpio_28_modes, | |
318 | .mode_count = ARRAY_SIZE(pmx_plgpio_28_modes), | |
319 | .enb_on_reset = 1, | |
320 | }; | |
321 | ||
6618c3ad | 322 | static struct pmx_dev_mode pmx_plgpio_29_modes[] = { |
70f4c0bf | 323 | { |
324 | .ids = 0x00, | |
325 | .mask = PMX_GPIO_PIN1_MASK, | |
326 | }, | |
327 | }; | |
328 | ||
6618c3ad | 329 | struct pmx_dev spear3xx_pmx_plgpio_29 = { |
70f4c0bf | 330 | .name = "plgpio 29", |
331 | .modes = pmx_plgpio_29_modes, | |
332 | .mode_count = ARRAY_SIZE(pmx_plgpio_29_modes), | |
333 | .enb_on_reset = 1, | |
334 | }; | |
335 | ||
6618c3ad | 336 | static struct pmx_dev_mode pmx_plgpio_30_modes[] = { |
70f4c0bf | 337 | { |
338 | .ids = 0x00, | |
339 | .mask = PMX_GPIO_PIN2_MASK, | |
340 | }, | |
341 | }; | |
342 | ||
6618c3ad | 343 | struct pmx_dev spear3xx_pmx_plgpio_30 = { |
70f4c0bf | 344 | .name = "plgpio 30", |
345 | .modes = pmx_plgpio_30_modes, | |
346 | .mode_count = ARRAY_SIZE(pmx_plgpio_30_modes), | |
347 | .enb_on_reset = 1, | |
348 | }; | |
349 | ||
6618c3ad | 350 | static struct pmx_dev_mode pmx_plgpio_31_modes[] = { |
70f4c0bf | 351 | { |
352 | .ids = 0x00, | |
353 | .mask = PMX_GPIO_PIN3_MASK, | |
354 | }, | |
355 | }; | |
356 | ||
6618c3ad | 357 | struct pmx_dev spear3xx_pmx_plgpio_31 = { |
70f4c0bf | 358 | .name = "plgpio 31", |
359 | .modes = pmx_plgpio_31_modes, | |
360 | .mode_count = ARRAY_SIZE(pmx_plgpio_31_modes), | |
361 | .enb_on_reset = 1, | |
362 | }; | |
363 | ||
6618c3ad | 364 | static struct pmx_dev_mode pmx_plgpio_32_modes[] = { |
70f4c0bf | 365 | { |
366 | .ids = 0x00, | |
367 | .mask = PMX_GPIO_PIN4_MASK, | |
368 | }, | |
369 | }; | |
370 | ||
6618c3ad | 371 | struct pmx_dev spear3xx_pmx_plgpio_32 = { |
70f4c0bf | 372 | .name = "plgpio 32", |
373 | .modes = pmx_plgpio_32_modes, | |
374 | .mode_count = ARRAY_SIZE(pmx_plgpio_32_modes), | |
375 | .enb_on_reset = 1, | |
376 | }; | |
377 | ||
6618c3ad | 378 | static struct pmx_dev_mode pmx_plgpio_33_modes[] = { |
70f4c0bf | 379 | { |
380 | .ids = 0x00, | |
381 | .mask = PMX_GPIO_PIN5_MASK, | |
382 | }, | |
383 | }; | |
384 | ||
6618c3ad | 385 | struct pmx_dev spear3xx_pmx_plgpio_33 = { |
70f4c0bf | 386 | .name = "plgpio 33", |
387 | .modes = pmx_plgpio_33_modes, | |
388 | .mode_count = ARRAY_SIZE(pmx_plgpio_33_modes), | |
389 | .enb_on_reset = 1, | |
390 | }; | |
391 | ||
6618c3ad | 392 | static struct pmx_dev_mode pmx_plgpio_34_36_modes[] = { |
70f4c0bf | 393 | { |
394 | .ids = 0x00, | |
395 | .mask = PMX_SSP_CS_MASK, | |
396 | }, | |
397 | }; | |
398 | ||
6618c3ad | 399 | struct pmx_dev spear3xx_pmx_plgpio_34_36 = { |
70f4c0bf | 400 | .name = "plgpio 34 to 36", |
401 | .modes = pmx_plgpio_34_36_modes, | |
402 | .mode_count = ARRAY_SIZE(pmx_plgpio_34_36_modes), | |
403 | .enb_on_reset = 1, | |
404 | }; | |
405 | ||
6618c3ad | 406 | static struct pmx_dev_mode pmx_plgpio_37_42_modes[] = { |
70f4c0bf | 407 | { |
408 | .ids = 0x00, | |
409 | .mask = PMX_UART0_MODEM_MASK, | |
410 | }, | |
411 | }; | |
412 | ||
6618c3ad | 413 | struct pmx_dev spear3xx_pmx_plgpio_37_42 = { |
70f4c0bf | 414 | .name = "plgpio 37 to 42", |
415 | .modes = pmx_plgpio_37_42_modes, | |
416 | .mode_count = ARRAY_SIZE(pmx_plgpio_37_42_modes), | |
417 | .enb_on_reset = 1, | |
418 | }; | |
419 | ||
6618c3ad | 420 | static struct pmx_dev_mode pmx_plgpio_43_44_47_48_modes[] = { |
70f4c0bf | 421 | { |
422 | .ids = 0x00, | |
423 | .mask = PMX_TIMER_1_2_MASK, | |
424 | }, | |
425 | }; | |
426 | ||
6618c3ad | 427 | struct pmx_dev spear3xx_pmx_plgpio_43_44_47_48 = { |
70f4c0bf | 428 | .name = "plgpio 43, 44, 47 and 48", |
429 | .modes = pmx_plgpio_43_44_47_48_modes, | |
430 | .mode_count = ARRAY_SIZE(pmx_plgpio_43_44_47_48_modes), | |
431 | .enb_on_reset = 1, | |
432 | }; | |
433 | ||
6618c3ad | 434 | static struct pmx_dev_mode pmx_plgpio_45_46_49_50_modes[] = { |
70f4c0bf | 435 | { |
436 | .ids = 0x00, | |
437 | .mask = PMX_TIMER_3_4_MASK, | |
438 | }, | |
439 | }; | |
440 | ||
6618c3ad | 441 | struct pmx_dev spear3xx_pmx_plgpio_45_46_49_50 = { |
70f4c0bf | 442 | .name = "plgpio 45, 46, 49 and 50", |
443 | .modes = pmx_plgpio_45_46_49_50_modes, | |
444 | .mode_count = ARRAY_SIZE(pmx_plgpio_45_46_49_50_modes), | |
445 | .enb_on_reset = 1, | |
446 | }; | |
5c881d9a | 447 | #endif /* CONFIG_MACH_SPEAR310 || CONFIG_MACH_SPEAR320 */ |
70f4c0bf | 448 | |
c5fa4fdc VK |
449 | /* ssp device registration */ |
450 | struct pl022_ssp_controller pl022_plat_data = { | |
451 | .bus_id = 0, | |
452 | .enable_dma = 1, | |
453 | .dma_filter = pl08x_filter_id, | |
454 | .dma_tx_param = "ssp0_tx", | |
455 | .dma_rx_param = "ssp0_rx", | |
456 | /* | |
457 | * This is number of spi devices that can be connected to spi. There are | |
458 | * two type of chipselects on which slave devices can work. One is chip | |
459 | * select provided by spi masters other is controlled through external | |
460 | * gpio's. We can't use chipselect provided from spi master (because as | |
461 | * soon as FIFO becomes empty, CS is disabled and transfer ends). So | |
462 | * this number now depends on number of gpios available for spi. each | |
463 | * slave on each master requires a separate gpio pin. | |
464 | */ | |
465 | .num_chipselect = 2, | |
466 | }; | |
467 | ||
468 | /* | |
469 | * Following will create 16MB static virtual/physical mappings | |
470 | * PHYSICAL VIRTUAL | |
471 | * 0xD0000000 0xFD000000 | |
472 | * 0xFC000000 0xFC000000 | |
473 | */ | |
474 | struct map_desc spear3xx_io_desc[] __initdata = { | |
475 | { | |
476 | .virtual = VA_SPEAR3XX_ICM1_2_BASE, | |
477 | .pfn = __phys_to_pfn(SPEAR3XX_ICM1_2_BASE), | |
478 | .length = SZ_16M, | |
479 | .type = MT_DEVICE | |
480 | }, { | |
481 | .virtual = VA_SPEAR3XX_ICM3_SMI_CTRL_BASE, | |
482 | .pfn = __phys_to_pfn(SPEAR3XX_ICM3_SMI_CTRL_BASE), | |
483 | .length = SZ_16M, | |
484 | .type = MT_DEVICE | |
485 | }, | |
486 | }; | |
487 | ||
488 | /* This will create static memory mapping for selected devices */ | |
489 | void __init spear3xx_map_io(void) | |
490 | { | |
491 | iotable_init(spear3xx_io_desc, ARRAY_SIZE(spear3xx_io_desc)); | |
492 | } | |
493 | ||
5c881d9a SH |
494 | static void __init spear3xx_timer_init(void) |
495 | { | |
496 | char pclk_name[] = "pll3_48m_clk"; | |
497 | struct clk *gpt_clk, *pclk; | |
498 | ||
499 | /* get the system timer clock */ | |
500 | gpt_clk = clk_get_sys("gpt0", NULL); | |
501 | if (IS_ERR(gpt_clk)) { | |
502 | pr_err("%s:couldn't get clk for gpt\n", __func__); | |
503 | BUG(); | |
504 | } | |
505 | ||
506 | /* get the suitable parent clock for timer*/ | |
507 | pclk = clk_get(NULL, pclk_name); | |
508 | if (IS_ERR(pclk)) { | |
509 | pr_err("%s:couldn't get %s as parent for gpt\n", | |
510 | __func__, pclk_name); | |
511 | BUG(); | |
512 | } | |
513 | ||
514 | clk_set_parent(gpt_clk, pclk); | |
515 | clk_put(gpt_clk); | |
516 | clk_put(pclk); | |
517 | ||
518 | spear_setup_timer(); | |
519 | } | |
520 | ||
521 | struct sys_timer spear3xx_timer = { | |
522 | .init = spear3xx_timer_init, | |
523 | }; | |
c5fa4fdc VK |
524 | |
525 | static const struct of_device_id vic_of_match[] __initconst = { | |
526 | { .compatible = "arm,pl190-vic", .data = vic_of_init, }, | |
527 | { /* Sentinel */ } | |
528 | }; | |
529 | ||
530 | void __init spear3xx_dt_init_irq(void) | |
531 | { | |
532 | of_irq_init(vic_of_match); | |
533 | } |