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Clk:spear3xx:Fix: Rename clk ids within predefined limit
[deliverable/linux.git] / arch / arm / mach-spear6xx / spear6xx.c
CommitLineData
8f590d45 1/*
2 * arch/arm/mach-spear6xx/spear6xx.c
3 *
4 * SPEAr6XX machines common source file
5 *
6 * Copyright (C) 2009 ST Microelectronics
7 * Rajeev Kumar<rajeev-dlh.kumar@st.com>
8 *
9652e8bd
SR		 9 * Copyright 2012 Stefan Roese <sr@denx.de>
10 *
8f590d45 11 * This file is licensed under the terms of the GNU General Public
12 * License version 2. This program is licensed "as is" without any
13 * warranty of any kind, whether express or implied.
14 */
15
0b7ee717 16#include <linux/amba/pl08x.h>
5019f0b1
AB		 17#include <linux/clk.h>
18#include <linux/err.h>
9652e8bd
SR		 19#include <linux/of.h>
20#include <linux/of_address.h>
21#include <linux/of_irq.h>
22#include <linux/of_platform.h>
0b7ee717 23#include <asm/hardware/pl080.h>
8f590d45 24#include <asm/hardware/vic.h>
8f590d45 25#include <asm/mach/arch.h>
5019f0b1
AB		 26#include <asm/mach/time.h>
27#include <asm/mach/map.h>
0b7ee717 28#include <plat/pl080.h>
8f590d45 29#include <mach/generic.h>
5019f0b1 30#include <mach/spear.h>
8f590d45 31
0b7ee717
VK		 32/* dmac device registration */
33static struct pl08x_channel_data spear600_dma_info[] = {
34 {
35 .bus_id = "ssp1_rx",
36 .min_signal = 0,
37 .max_signal = 0,
38 .muxval = 0,
39 .cctl = 0,
40 .periph_buses = PL08X_AHB1,
41 }, {
42 .bus_id = "ssp1_tx",
43 .min_signal = 1,
44 .max_signal = 1,
45 .muxval = 0,
46 .cctl = 0,
47 .periph_buses = PL08X_AHB1,
48 }, {
49 .bus_id = "uart0_rx",
50 .min_signal = 2,
51 .max_signal = 2,
52 .muxval = 0,
53 .cctl = 0,
54 .periph_buses = PL08X_AHB1,
55 }, {
56 .bus_id = "uart0_tx",
57 .min_signal = 3,
58 .max_signal = 3,
59 .muxval = 0,
60 .cctl = 0,
61 .periph_buses = PL08X_AHB1,
62 }, {
63 .bus_id = "uart1_rx",
64 .min_signal = 4,
65 .max_signal = 4,
66 .muxval = 0,
67 .cctl = 0,
68 .periph_buses = PL08X_AHB1,
69 }, {
70 .bus_id = "uart1_tx",
71 .min_signal = 5,
72 .max_signal = 5,
73 .muxval = 0,
74 .cctl = 0,
75 .periph_buses = PL08X_AHB1,
76 }, {
77 .bus_id = "ssp2_rx",
78 .min_signal = 6,
79 .max_signal = 6,
80 .muxval = 0,
81 .cctl = 0,
82 .periph_buses = PL08X_AHB2,
83 }, {
84 .bus_id = "ssp2_tx",
85 .min_signal = 7,
86 .max_signal = 7,
87 .muxval = 0,
88 .cctl = 0,
89 .periph_buses = PL08X_AHB2,
90 }, {
91 .bus_id = "ssp0_rx",
92 .min_signal = 8,
93 .max_signal = 8,
94 .muxval = 0,
95 .cctl = 0,
96 .periph_buses = PL08X_AHB1,
97 }, {
98 .bus_id = "ssp0_tx",
99 .min_signal = 9,
100 .max_signal = 9,
101 .muxval = 0,
102 .cctl = 0,
103 .periph_buses = PL08X_AHB1,
104 }, {
105 .bus_id = "i2c_rx",
106 .min_signal = 10,
107 .max_signal = 10,
108 .muxval = 0,
109 .cctl = 0,
110 .periph_buses = PL08X_AHB1,
111 }, {
112 .bus_id = "i2c_tx",
113 .min_signal = 11,
114 .max_signal = 11,
115 .muxval = 0,
116 .cctl = 0,
117 .periph_buses = PL08X_AHB1,
118 }, {
119 .bus_id = "irda",
120 .min_signal = 12,
121 .max_signal = 12,
122 .muxval = 0,
123 .cctl = 0,
124 .periph_buses = PL08X_AHB1,
125 }, {
126 .bus_id = "adc",
127 .min_signal = 13,
128 .max_signal = 13,
129 .muxval = 0,
130 .cctl = 0,
131 .periph_buses = PL08X_AHB2,
132 }, {
133 .bus_id = "to_jpeg",
134 .min_signal = 14,
135 .max_signal = 14,
136 .muxval = 0,
137 .cctl = 0,
138 .periph_buses = PL08X_AHB1,
139 }, {
140 .bus_id = "from_jpeg",
141 .min_signal = 15,
142 .max_signal = 15,
143 .muxval = 0,
144 .cctl = 0,
145 .periph_buses = PL08X_AHB1,
146 }, {
147 .bus_id = "ras0_rx",
148 .min_signal = 0,
149 .max_signal = 0,
150 .muxval = 1,
151 .cctl = 0,
152 .periph_buses = PL08X_AHB1,
153 }, {
154 .bus_id = "ras0_tx",
155 .min_signal = 1,
156 .max_signal = 1,
157 .muxval = 1,
158 .cctl = 0,
159 .periph_buses = PL08X_AHB1,
160 }, {
161 .bus_id = "ras1_rx",
162 .min_signal = 2,
163 .max_signal = 2,
164 .muxval = 1,
165 .cctl = 0,
166 .periph_buses = PL08X_AHB1,
167 }, {
168 .bus_id = "ras1_tx",
169 .min_signal = 3,
170 .max_signal = 3,
171 .muxval = 1,
172 .cctl = 0,
173 .periph_buses = PL08X_AHB1,
174 }, {
175 .bus_id = "ras2_rx",
176 .min_signal = 4,
177 .max_signal = 4,
178 .muxval = 1,
179 .cctl = 0,
180 .periph_buses = PL08X_AHB1,
181 }, {
182 .bus_id = "ras2_tx",
183 .min_signal = 5,
184 .max_signal = 5,
185 .muxval = 1,
186 .cctl = 0,
187 .periph_buses = PL08X_AHB1,
188 }, {
189 .bus_id = "ras3_rx",
190 .min_signal = 6,
191 .max_signal = 6,
192 .muxval = 1,
193 .cctl = 0,
194 .periph_buses = PL08X_AHB1,
195 }, {
196 .bus_id = "ras3_tx",
197 .min_signal = 7,
198 .max_signal = 7,
199 .muxval = 1,
200 .cctl = 0,
201 .periph_buses = PL08X_AHB1,
202 }, {
203 .bus_id = "ras4_rx",
204 .min_signal = 8,
205 .max_signal = 8,
206 .muxval = 1,
207 .cctl = 0,
208 .periph_buses = PL08X_AHB1,
209 }, {
210 .bus_id = "ras4_tx",
211 .min_signal = 9,
212 .max_signal = 9,
213 .muxval = 1,
214 .cctl = 0,
215 .periph_buses = PL08X_AHB1,
216 }, {
217 .bus_id = "ras5_rx",
218 .min_signal = 10,
219 .max_signal = 10,
220 .muxval = 1,
221 .cctl = 0,
222 .periph_buses = PL08X_AHB1,
223 }, {
224 .bus_id = "ras5_tx",
225 .min_signal = 11,
226 .max_signal = 11,
227 .muxval = 1,
228 .cctl = 0,
229 .periph_buses = PL08X_AHB1,
230 }, {
231 .bus_id = "ras6_rx",
232 .min_signal = 12,
233 .max_signal = 12,
234 .muxval = 1,
235 .cctl = 0,
236 .periph_buses = PL08X_AHB1,
237 }, {
238 .bus_id = "ras6_tx",
239 .min_signal = 13,
240 .max_signal = 13,
241 .muxval = 1,
242 .cctl = 0,
243 .periph_buses = PL08X_AHB1,
244 }, {
245 .bus_id = "ras7_rx",
246 .min_signal = 14,
247 .max_signal = 14,
248 .muxval = 1,
249 .cctl = 0,
250 .periph_buses = PL08X_AHB1,
251 }, {
252 .bus_id = "ras7_tx",
253 .min_signal = 15,
254 .max_signal = 15,
255 .muxval = 1,
256 .cctl = 0,
257 .periph_buses = PL08X_AHB1,
258 }, {
259 .bus_id = "ext0_rx",
260 .min_signal = 0,
261 .max_signal = 0,
262 .muxval = 2,
263 .cctl = 0,
264 .periph_buses = PL08X_AHB2,
265 }, {
266 .bus_id = "ext0_tx",
267 .min_signal = 1,
268 .max_signal = 1,
269 .muxval = 2,
270 .cctl = 0,
271 .periph_buses = PL08X_AHB2,
272 }, {
273 .bus_id = "ext1_rx",
274 .min_signal = 2,
275 .max_signal = 2,
276 .muxval = 2,
277 .cctl = 0,
278 .periph_buses = PL08X_AHB2,
279 }, {
280 .bus_id = "ext1_tx",
281 .min_signal = 3,
282 .max_signal = 3,
283 .muxval = 2,
284 .cctl = 0,
285 .periph_buses = PL08X_AHB2,
286 }, {
287 .bus_id = "ext2_rx",
288 .min_signal = 4,
289 .max_signal = 4,
290 .muxval = 2,
291 .cctl = 0,
292 .periph_buses = PL08X_AHB2,
293 }, {
294 .bus_id = "ext2_tx",
295 .min_signal = 5,
296 .max_signal = 5,
297 .muxval = 2,
298 .cctl = 0,
299 .periph_buses = PL08X_AHB2,
300 }, {
301 .bus_id = "ext3_rx",
302 .min_signal = 6,
303 .max_signal = 6,
304 .muxval = 2,
305 .cctl = 0,
306 .periph_buses = PL08X_AHB2,
307 }, {
308 .bus_id = "ext3_tx",
309 .min_signal = 7,
310 .max_signal = 7,
311 .muxval = 2,
312 .cctl = 0,
313 .periph_buses = PL08X_AHB2,
314 }, {
315 .bus_id = "ext4_rx",
316 .min_signal = 8,
317 .max_signal = 8,
318 .muxval = 2,
319 .cctl = 0,
320 .periph_buses = PL08X_AHB2,
321 }, {
322 .bus_id = "ext4_tx",
323 .min_signal = 9,
324 .max_signal = 9,
325 .muxval = 2,
326 .cctl = 0,
327 .periph_buses = PL08X_AHB2,
328 }, {
329 .bus_id = "ext5_rx",
330 .min_signal = 10,
331 .max_signal = 10,
332 .muxval = 2,
333 .cctl = 0,
334 .periph_buses = PL08X_AHB2,
335 }, {
336 .bus_id = "ext5_tx",
337 .min_signal = 11,
338 .max_signal = 11,
339 .muxval = 2,
340 .cctl = 0,
341 .periph_buses = PL08X_AHB2,
342 }, {
343 .bus_id = "ext6_rx",
344 .min_signal = 12,
345 .max_signal = 12,
346 .muxval = 2,
347 .cctl = 0,
348 .periph_buses = PL08X_AHB2,
349 }, {
350 .bus_id = "ext6_tx",
351 .min_signal = 13,
352 .max_signal = 13,
353 .muxval = 2,
354 .cctl = 0,
355 .periph_buses = PL08X_AHB2,
356 }, {
357 .bus_id = "ext7_rx",
358 .min_signal = 14,
359 .max_signal = 14,
360 .muxval = 2,
361 .cctl = 0,
362 .periph_buses = PL08X_AHB2,
363 }, {
364 .bus_id = "ext7_tx",
365 .min_signal = 15,
366 .max_signal = 15,
367 .muxval = 2,
368 .cctl = 0,
369 .periph_buses = PL08X_AHB2,
370 },
371};
372
373struct pl08x_platform_data pl080_plat_data = {
374 .memcpy_channel = {
375 .bus_id = "memcpy",
376 .cctl = (PL080_BSIZE_16 << PL080_CONTROL_SB_SIZE_SHIFT | \
377 PL080_BSIZE_16 << PL080_CONTROL_DB_SIZE_SHIFT | \
378 PL080_WIDTH_32BIT << PL080_CONTROL_SWIDTH_SHIFT | \
379 PL080_WIDTH_32BIT << PL080_CONTROL_DWIDTH_SHIFT | \
380 PL080_CONTROL_PROT_BUFF | PL080_CONTROL_PROT_CACHE | \
381 PL080_CONTROL_PROT_SYS),
382 },
383 .lli_buses = PL08X_AHB1,
384 .mem_buses = PL08X_AHB1,
385 .get_signal = pl080_get_signal,
386 .put_signal = pl080_put_signal,
387 .slave_channels = spear600_dma_info,
388 .num_slave_channels = ARRAY_SIZE(spear600_dma_info),
389};
390
5019f0b1
AB		 391/*
392 * Following will create 16MB static virtual/physical mappings
393 * PHYSICAL VIRTUAL
394 * 0xF0000000 0xF0000000
395 * 0xF1000000 0xF1000000
396 * 0xD0000000 0xFD000000
397 * 0xFC000000 0xFC000000
398 */
399struct map_desc spear6xx_io_desc[] __initdata = {
8f590d45 400 {
5019f0b1
AB		 401 .virtual = VA_SPEAR6XX_ML_CPU_BASE,
402 .pfn = __phys_to_pfn(SPEAR6XX_ML_CPU_BASE),
403 .length = 2 * SZ_16M,
8f590d45 404 .type = MT_DEVICE
5019f0b1
AB		 405 }, {
406 .virtual = VA_SPEAR6XX_ICM1_BASE,
407 .pfn = __phys_to_pfn(SPEAR6XX_ICM1_BASE),
408 .length = SZ_16M,
8f590d45 409 .type = MT_DEVICE
410 }, {
5019f0b1
AB		 411 .virtual = VA_SPEAR6XX_ICM3_SMI_CTRL_BASE,
412 .pfn = __phys_to_pfn(SPEAR6XX_ICM3_SMI_CTRL_BASE),
413 .length = SZ_16M,
8f590d45 414 .type = MT_DEVICE
415 },
416};
417
418/* This will create static memory mapping for selected devices */
419void __init spear6xx_map_io(void)
420{
421 iotable_init(spear6xx_io_desc, ARRAY_SIZE(spear6xx_io_desc));
8f590d45 422}
5c881d9a
SH		 423
424static void __init spear6xx_timer_init(void)
425{
426 char pclk_name[] = "pll3_48m_clk";
427 struct clk *gpt_clk, *pclk;
428
5df33a62
VK		 429 spear6xx_clk_init();
430
5c881d9a
SH		 431 /* get the system timer clock */
432 gpt_clk = clk_get_sys("gpt0", NULL);
433 if (IS_ERR(gpt_clk)) {
434 pr_err("%s:couldn't get clk for gpt\n", __func__);
435 BUG();
436 }
437
438 /* get the suitable parent clock for timer*/
439 pclk = clk_get(NULL, pclk_name);
440 if (IS_ERR(pclk)) {
441 pr_err("%s:couldn't get %s as parent for gpt\n",
442 __func__, pclk_name);
443 BUG();
444 }
445
446 clk_set_parent(gpt_clk, pclk);
447 clk_put(gpt_clk);
448 clk_put(pclk);
449
30551c01 450 spear_setup_of_timer();
5c881d9a
SH		 451}
452
453struct sys_timer spear6xx_timer = {
454 .init = spear6xx_timer_init,
455};
9652e8bd 456
0b7ee717
VK		 457/* Add auxdata to pass platform data */
458struct of_dev_auxdata spear6xx_auxdata_lookup[] __initdata = {
459 OF_DEV_AUXDATA("arm,pl080", SPEAR6XX_ICM3_DMA_BASE, NULL,
460 &pl080_plat_data),
461 {}
462};
463
9652e8bd
SR		 464static void __init spear600_dt_init(void)
465{
0b7ee717
VK		 466 of_platform_populate(NULL, of_default_bus_match_table,
467 spear6xx_auxdata_lookup, NULL);
9652e8bd
SR		 468}
469
470static const char *spear600_dt_board_compat[] = {
471 "st,spear600",
472 NULL
473};
474
475static const struct of_device_id vic_of_match[] __initconst = {
476 { .compatible = "arm,pl190-vic", .data = vic_of_init, },
477 { /* Sentinel */ }
478};
479
480static void __init spear6xx_dt_init_irq(void)
481{
482 of_irq_init(vic_of_match);
483}
484
485DT_MACHINE_START(SPEAR600_DT, "ST SPEAr600 (Flattened Device Tree)")
486 .map_io = spear6xx_map_io,
487 .init_irq = spear6xx_dt_init_irq,
488 .handle_irq = vic_handle_irq,
489 .timer = &spear6xx_timer,
490 .init_machine = spear600_dt_init,
491 .restart = spear_restart,
492 .dt_compat = spear600_dt_board_compat,
493MACHINE_END
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