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cca414b2 MR |
1 | /* |
2 | * arch/arm/mach-tegra/board-trimslice.c | |
3 | * | |
4 | * Copyright (C) 2011 CompuLab, Ltd. | |
5 | * Author: Mike Rapoport <mike@compulab.co.il> | |
6 | * | |
7 | * Based on board-harmony.c | |
8 | * Copyright (C) 2010 Google, Inc. | |
9 | * | |
10 | * This software is licensed under the terms of the GNU General Public | |
11 | * License version 2, as published by the Free Software Foundation, and | |
12 | * may be copied, distributed, and modified under those terms. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | */ | |
20 | ||
21 | #include <linux/kernel.h> | |
22 | #include <linux/init.h> | |
23 | #include <linux/platform_device.h> | |
24 | #include <linux/serial_8250.h> | |
25 | #include <linux/io.h> | |
bea2d6b8 MR |
26 | #include <linux/i2c.h> |
27 | #include <linux/i2c-tegra.h> | |
4c755997 MR |
28 | #include <linux/platform_data/tegra_usb.h> |
29 | #include <linux/gpio.h> | |
cca414b2 MR |
30 | |
31 | #include <asm/mach-types.h> | |
32 | #include <asm/mach/arch.h> | |
33 | #include <asm/setup.h> | |
34 | ||
35 | #include <mach/iomap.h> | |
f02726a7 | 36 | #include <mach/sdhci.h> |
4c755997 MR |
37 | #include <mach/usb_phy.h> |
38 | #include <mach/gpio.h> | |
cca414b2 MR |
39 | |
40 | #include "board.h" | |
41 | #include "clock.h" | |
f02726a7 MR |
42 | #include "devices.h" |
43 | #include "gpio-names.h" | |
cca414b2 MR |
44 | |
45 | #include "board-trimslice.h" | |
46 | ||
47 | static struct plat_serial8250_port debug_uart_platform_data[] = { | |
48 | { | |
49 | .membase = IO_ADDRESS(TEGRA_UARTA_BASE), | |
50 | .mapbase = TEGRA_UARTA_BASE, | |
51 | .irq = INT_UARTA, | |
52 | .flags = UPF_BOOT_AUTOCONF, | |
53 | .iotype = UPIO_MEM, | |
54 | .regshift = 2, | |
55 | .uartclk = 216000000, | |
56 | }, { | |
57 | .flags = 0 | |
58 | } | |
59 | }; | |
60 | ||
61 | static struct platform_device debug_uart = { | |
62 | .name = "serial8250", | |
63 | .id = PLAT8250_DEV_PLATFORM, | |
64 | .dev = { | |
65 | .platform_data = debug_uart_platform_data, | |
66 | }, | |
67 | }; | |
f02726a7 MR |
68 | static struct tegra_sdhci_platform_data sdhci_pdata1 = { |
69 | .cd_gpio = -1, | |
70 | .wp_gpio = -1, | |
71 | .power_gpio = -1, | |
72 | }; | |
73 | ||
74 | static struct tegra_sdhci_platform_data sdhci_pdata4 = { | |
75 | .cd_gpio = TRIMSLICE_GPIO_SD4_CD, | |
76 | .wp_gpio = TRIMSLICE_GPIO_SD4_WP, | |
77 | .power_gpio = -1, | |
78 | }; | |
cca414b2 | 79 | |
9504940a MR |
80 | static struct platform_device trimslice_audio_device = { |
81 | .name = "tegra-snd-trimslice", | |
82 | .id = 0, | |
83 | }; | |
84 | ||
cca414b2 MR |
85 | static struct platform_device *trimslice_devices[] __initdata = { |
86 | &debug_uart, | |
f02726a7 MR |
87 | &tegra_sdhci_device1, |
88 | &tegra_sdhci_device4, | |
9504940a MR |
89 | &tegra_i2s_device1, |
90 | &tegra_das_device, | |
91 | &tegra_pcm_device, | |
92 | &trimslice_audio_device, | |
cca414b2 MR |
93 | }; |
94 | ||
bea2d6b8 MR |
95 | static struct tegra_i2c_platform_data trimslice_i2c1_platform_data = { |
96 | .bus_clk_rate = 400000, | |
97 | }; | |
98 | ||
99 | static struct tegra_i2c_platform_data trimslice_i2c2_platform_data = { | |
100 | .bus_clk_rate = 400000, | |
101 | }; | |
102 | ||
103 | static struct tegra_i2c_platform_data trimslice_i2c3_platform_data = { | |
104 | .bus_clk_rate = 400000, | |
105 | }; | |
106 | ||
107 | static struct i2c_board_info trimslice_i2c3_board_info[] = { | |
108 | { | |
109 | I2C_BOARD_INFO("tlv320aic23", 0x1a), | |
110 | }, | |
111 | { | |
112 | I2C_BOARD_INFO("em3027", 0x56), | |
113 | }, | |
114 | }; | |
115 | ||
116 | static void trimslice_i2c_init(void) | |
117 | { | |
118 | tegra_i2c_device1.dev.platform_data = &trimslice_i2c1_platform_data; | |
119 | tegra_i2c_device2.dev.platform_data = &trimslice_i2c2_platform_data; | |
120 | tegra_i2c_device3.dev.platform_data = &trimslice_i2c3_platform_data; | |
121 | ||
122 | platform_device_register(&tegra_i2c_device1); | |
123 | platform_device_register(&tegra_i2c_device2); | |
124 | platform_device_register(&tegra_i2c_device3); | |
125 | ||
126 | i2c_register_board_info(2, trimslice_i2c3_board_info, | |
127 | ARRAY_SIZE(trimslice_i2c3_board_info)); | |
128 | } | |
129 | ||
4c755997 MR |
130 | struct tegra_ulpi_config ehci2_phy_config = { |
131 | .reset_gpio = TRIMSLICE_GPIO_USB2_RST, | |
132 | .clk = "cdev2", | |
133 | }; | |
134 | ||
135 | static struct tegra_ehci_platform_data ehci_ulpi_data = { | |
136 | .operating_mode = TEGRA_USB_HOST, | |
137 | .phy_config = &ehci2_phy_config, | |
138 | }; | |
139 | ||
140 | static struct tegra_ehci_platform_data ehci_utmi_data = { | |
141 | .operating_mode = TEGRA_USB_HOST, | |
142 | }; | |
143 | ||
144 | static void trimslice_usb_init(void) | |
145 | { | |
146 | int err; | |
147 | ||
148 | tegra_ehci3_device.dev.platform_data = &ehci_utmi_data; | |
149 | platform_device_register(&tegra_ehci3_device); | |
150 | ||
151 | tegra_ehci2_device.dev.platform_data = &ehci_ulpi_data; | |
152 | platform_device_register(&tegra_ehci2_device); | |
153 | ||
154 | err = gpio_request_one(TRIMSLICE_GPIO_USB1_MODE, GPIOF_OUT_INIT_HIGH, | |
155 | "usb1mode"); | |
156 | if (err) { | |
157 | pr_err("TrimSlice: failed to obtain USB1 mode gpio: %d\n", err); | |
158 | return; | |
159 | } | |
160 | ||
161 | tegra_ehci1_device.dev.platform_data = &ehci_utmi_data; | |
162 | platform_device_register(&tegra_ehci1_device); | |
163 | } | |
164 | ||
cca414b2 MR |
165 | static void __init tegra_trimslice_fixup(struct machine_desc *desc, |
166 | struct tag *tags, char **cmdline, struct meminfo *mi) | |
167 | { | |
168 | mi->nr_banks = 2; | |
169 | mi->bank[0].start = PHYS_OFFSET; | |
170 | mi->bank[0].size = 448 * SZ_1M; | |
171 | mi->bank[1].start = SZ_512M; | |
172 | mi->bank[1].size = SZ_512M; | |
173 | } | |
174 | ||
175 | static __initdata struct tegra_clk_init_table trimslice_clk_init_table[] = { | |
176 | /* name parent rate enabled */ | |
177 | { "uarta", "pll_p", 216000000, true }, | |
9504940a MR |
178 | { "pll_a", "pll_p_out1", 56448000, true }, |
179 | { "pll_a_out0", "pll_a", 11289600, true }, | |
180 | { "cdev1", NULL, 0, true }, | |
181 | { "i2s1", "pll_a_out0", 11289600, false}, | |
cca414b2 MR |
182 | { NULL, NULL, 0, 0}, |
183 | }; | |
184 | ||
185 | static int __init tegra_trimslice_pci_init(void) | |
186 | { | |
d5fdafd3 MR |
187 | if (!machine_is_trimslice()) |
188 | return 0; | |
189 | ||
cca414b2 MR |
190 | return tegra_pcie_init(true, true); |
191 | } | |
192 | subsys_initcall(tegra_trimslice_pci_init); | |
193 | ||
194 | static void __init tegra_trimslice_init(void) | |
195 | { | |
cca414b2 MR |
196 | tegra_clk_init_from_table(trimslice_clk_init_table); |
197 | ||
198 | trimslice_pinmux_init(); | |
199 | ||
f02726a7 MR |
200 | tegra_sdhci_device1.dev.platform_data = &sdhci_pdata1; |
201 | tegra_sdhci_device4.dev.platform_data = &sdhci_pdata4; | |
202 | ||
cca414b2 | 203 | platform_add_devices(trimslice_devices, ARRAY_SIZE(trimslice_devices)); |
bea2d6b8 MR |
204 | |
205 | trimslice_i2c_init(); | |
4c755997 | 206 | trimslice_usb_init(); |
cca414b2 MR |
207 | } |
208 | ||
209 | MACHINE_START(TRIMSLICE, "trimslice") | |
210 | .boot_params = 0x00000100, | |
211 | .fixup = tegra_trimslice_fixup, | |
cca414b2 | 212 | .map_io = tegra_map_common_io, |
0cf6230a CC |
213 | .init_early = tegra_init_early, |
214 | .init_irq = tegra_init_irq, | |
cca414b2 | 215 | .timer = &tegra_timer, |
0cf6230a | 216 | .init_machine = tegra_trimslice_init, |
cca414b2 | 217 | MACHINE_END |