projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| c5f80065 EG |
1 | /* |
| 2 | * arch/arm/mach-tegra/board-harmony.c | |
| 3 | * | |
| 4 | * Copyright (C) 2010 Google, Inc. | |
| 5 | * | |
| 6 | * Author: | |
| 7 | * Colin Cross <ccross@android.com> | |
| 8 | * | |
| 9 | * This software is licensed under the terms of the GNU General Public | |
| 10 | * License version 2, as published by the Free Software Foundation, and | |
| 11 | * may be copied, distributed, and modified under those terms. | |
| 12 | * | |
| 13 | * This program is distributed in the hope that it will be useful, | |
| 14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 16 | * GNU General Public License for more details. | |
| 17 | * | |
| 18 | */ | |
| 19 | ||
| 20 | #include <linux/init.h> | |
| 21 | #include <linux/io.h> | |
| 4de3a8fa CC |
22 | #include <linux/clk.h> |
| 23 | #include <linux/delay.h> | |
| c5f80065 EG |
24 | |
| 25 | #include <asm/hardware/cache-l2x0.h> | |
| 26 | ||
| 27 | #include <mach/iomap.h> | |
| 699fe145 | 28 | #include <mach/system.h> |
| c5f80065 EG |
29 | |
| 30 | #include "board.h" | |
| d8611961 | 31 | #include "clock.h" |
| 73625e3e | 32 | #include "fuse.h" |
| d8611961 | 33 | |
| 699fe145 CC |
34 | void (*arch_reset)(char mode, const char *cmd) = tegra_assert_system_reset; |
| 35 | ||
| 36 | void tegra_assert_system_reset(char mode, const char *cmd) | |
| 37 | { | |
| 38 | void __iomem *reset = IO_ADDRESS(TEGRA_CLK_RESET_BASE + 0x04); | |
| 39 | u32 reg; | |
| 40 | ||
| 375b19cd SG |
41 | /* use *_related to avoid spinlock since caches are off */ |
| 42 | reg = readl_relaxed(reset); | |
| 699fe145 | 43 | reg |= 0x04; |
| 375b19cd | 44 | writel_relaxed(reg, reset); |
| 699fe145 CC |
45 | } |
| 46 | ||
| d8611961 CC |
47 | static __initdata struct tegra_clk_init_table common_clk_init_table[] = { |
| 48 | /* name parent rate enabled */ | |
| 49 | { "clk_m", NULL, 0, true }, | |
| 50 | { "pll_p", "clk_m", 216000000, true }, | |
| 51 | { "pll_p_out1", "pll_p", 28800000, true }, | |
| 52 | { "pll_p_out2", "pll_p", 48000000, true }, | |
| 53 | { "pll_p_out3", "pll_p", 72000000, true }, | |
| 54 | { "pll_p_out4", "pll_p", 108000000, true }, | |
| 8486bddc CC |
55 | { "sclk", "pll_p_out4", 108000000, true }, |
| 56 | { "hclk", "sclk", 108000000, true }, | |
| d8611961 | 57 | { "pclk", "hclk", 54000000, true }, |
| cd51d0ed CC |
58 | { "csite", NULL, 0, true }, |
| 59 | { "emc", NULL, 0, true }, | |
| 60 | { "cpu", NULL, 0, true }, | |
| d8611961 CC |
61 | { NULL, NULL, 0, 0}, |
| 62 | }; | |
| c5f80065 EG |
63 | |
| 64 | void __init tegra_init_cache(void) | |
| 65 | { | |
| 66 | #ifdef CONFIG_CACHE_L2X0 | |
| 67 | void __iomem *p = IO_ADDRESS(TEGRA_ARM_PERIF_BASE) + 0x3000; | |
| 68 | ||
| 535371c3 CC |
69 | writel_relaxed(0x331, p + L2X0_TAG_LATENCY_CTRL); |
| 70 | writel_relaxed(0x441, p + L2X0_DATA_LATENCY_CTRL); | |
| c5f80065 EG |
71 | |
| 72 | l2x0_init(p, 0x6C080001, 0x8200c3fe); | |
| 73 | #endif | |
| 4de3a8fa | 74 | |
| c5f80065 EG |
75 | } |
| 76 | ||
| 0cf6230a | 77 | void __init tegra_init_early(void) |
| c5f80065 | 78 | { |
| 73625e3e | 79 | tegra_init_fuse(); |
| d8611961 CC |
80 | tegra_init_clock(); |
| 81 | tegra_clk_init_from_table(common_clk_init_table); | |
| c5f80065 EG |
82 | tegra_init_cache(); |
| 83 | } |