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3c92db9a EG |
1 | /* |
2 | * arch/arm/mach-tegra/gpio.c | |
3 | * | |
4 | * Copyright (c) 2010 Google, Inc | |
5 | * | |
6 | * Author: | |
7 | * Erik Gilling <konkers@google.com> | |
8 | * | |
9 | * This software is licensed under the terms of the GNU General Public | |
10 | * License version 2, as published by the Free Software Foundation, and | |
11 | * may be copied, distributed, and modified under those terms. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | */ | |
19 | ||
20 | #include <linux/init.h> | |
21 | #include <linux/irq.h> | |
2e47b8b3 | 22 | #include <linux/interrupt.h> |
3c92db9a EG |
23 | |
24 | #include <linux/io.h> | |
25 | #include <linux/gpio.h> | |
26 | ||
27 | #include <mach/iomap.h> | |
28 | ||
29 | #define GPIO_BANK(x) ((x) >> 5) | |
30 | #define GPIO_PORT(x) (((x) >> 3) & 0x3) | |
31 | #define GPIO_BIT(x) ((x) & 0x7) | |
32 | ||
33 | #define GPIO_REG(x) (IO_TO_VIRT(TEGRA_GPIO_BASE) + \ | |
34 | GPIO_BANK(x) * 0x80 + \ | |
35 | GPIO_PORT(x) * 4) | |
36 | ||
37 | #define GPIO_CNF(x) (GPIO_REG(x) + 0x00) | |
38 | #define GPIO_OE(x) (GPIO_REG(x) + 0x10) | |
39 | #define GPIO_OUT(x) (GPIO_REG(x) + 0X20) | |
40 | #define GPIO_IN(x) (GPIO_REG(x) + 0x30) | |
41 | #define GPIO_INT_STA(x) (GPIO_REG(x) + 0x40) | |
42 | #define GPIO_INT_ENB(x) (GPIO_REG(x) + 0x50) | |
43 | #define GPIO_INT_LVL(x) (GPIO_REG(x) + 0x60) | |
44 | #define GPIO_INT_CLR(x) (GPIO_REG(x) + 0x70) | |
45 | ||
46 | #define GPIO_MSK_CNF(x) (GPIO_REG(x) + 0x800) | |
47 | #define GPIO_MSK_OE(x) (GPIO_REG(x) + 0x810) | |
48 | #define GPIO_MSK_OUT(x) (GPIO_REG(x) + 0X820) | |
49 | #define GPIO_MSK_INT_STA(x) (GPIO_REG(x) + 0x840) | |
50 | #define GPIO_MSK_INT_ENB(x) (GPIO_REG(x) + 0x850) | |
51 | #define GPIO_MSK_INT_LVL(x) (GPIO_REG(x) + 0x860) | |
52 | ||
53 | #define GPIO_INT_LVL_MASK 0x010101 | |
54 | #define GPIO_INT_LVL_EDGE_RISING 0x000101 | |
55 | #define GPIO_INT_LVL_EDGE_FALLING 0x000100 | |
56 | #define GPIO_INT_LVL_EDGE_BOTH 0x010100 | |
57 | #define GPIO_INT_LVL_LEVEL_HIGH 0x000001 | |
58 | #define GPIO_INT_LVL_LEVEL_LOW 0x000000 | |
59 | ||
60 | struct tegra_gpio_bank { | |
61 | int bank; | |
62 | int irq; | |
63 | spinlock_t lvl_lock[4]; | |
2e47b8b3 CC |
64 | #ifdef CONFIG_PM |
65 | u32 cnf[4]; | |
66 | u32 out[4]; | |
67 | u32 oe[4]; | |
68 | u32 int_enb[4]; | |
69 | u32 int_lvl[4]; | |
70 | #endif | |
3c92db9a EG |
71 | }; |
72 | ||
73 | ||
74 | static struct tegra_gpio_bank tegra_gpio_banks[] = { | |
75 | {.bank = 0, .irq = INT_GPIO1}, | |
76 | {.bank = 1, .irq = INT_GPIO2}, | |
77 | {.bank = 2, .irq = INT_GPIO3}, | |
78 | {.bank = 3, .irq = INT_GPIO4}, | |
79 | {.bank = 4, .irq = INT_GPIO5}, | |
80 | {.bank = 5, .irq = INT_GPIO6}, | |
81 | {.bank = 6, .irq = INT_GPIO7}, | |
82 | }; | |
83 | ||
84 | static int tegra_gpio_compose(int bank, int port, int bit) | |
85 | { | |
86 | return (bank << 5) | ((port & 0x3) << 3) | (bit & 0x7); | |
87 | } | |
88 | ||
89 | static void tegra_gpio_mask_write(u32 reg, int gpio, int value) | |
90 | { | |
91 | u32 val; | |
92 | ||
93 | val = 0x100 << GPIO_BIT(gpio); | |
94 | if (value) | |
95 | val |= 1 << GPIO_BIT(gpio); | |
96 | __raw_writel(val, reg); | |
97 | } | |
98 | ||
99 | void tegra_gpio_enable(int gpio) | |
100 | { | |
101 | tegra_gpio_mask_write(GPIO_MSK_CNF(gpio), gpio, 1); | |
102 | } | |
103 | ||
104 | void tegra_gpio_disable(int gpio) | |
105 | { | |
106 | tegra_gpio_mask_write(GPIO_MSK_CNF(gpio), gpio, 0); | |
107 | } | |
108 | ||
109 | static void tegra_gpio_set(struct gpio_chip *chip, unsigned offset, int value) | |
110 | { | |
111 | tegra_gpio_mask_write(GPIO_MSK_OUT(offset), offset, value); | |
112 | } | |
113 | ||
114 | static int tegra_gpio_get(struct gpio_chip *chip, unsigned offset) | |
115 | { | |
116 | return (__raw_readl(GPIO_IN(offset)) >> GPIO_BIT(offset)) & 0x1; | |
117 | } | |
118 | ||
119 | static int tegra_gpio_direction_input(struct gpio_chip *chip, unsigned offset) | |
120 | { | |
121 | tegra_gpio_mask_write(GPIO_MSK_OE(offset), offset, 0); | |
122 | return 0; | |
123 | } | |
124 | ||
125 | static int tegra_gpio_direction_output(struct gpio_chip *chip, unsigned offset, | |
126 | int value) | |
127 | { | |
128 | tegra_gpio_set(chip, offset, value); | |
129 | tegra_gpio_mask_write(GPIO_MSK_OE(offset), offset, 1); | |
130 | return 0; | |
131 | } | |
132 | ||
133 | ||
134 | ||
135 | static struct gpio_chip tegra_gpio_chip = { | |
136 | .label = "tegra-gpio", | |
137 | .direction_input = tegra_gpio_direction_input, | |
138 | .get = tegra_gpio_get, | |
139 | .direction_output = tegra_gpio_direction_output, | |
140 | .set = tegra_gpio_set, | |
141 | .base = 0, | |
2e47b8b3 | 142 | .ngpio = TEGRA_NR_GPIOS, |
3c92db9a EG |
143 | }; |
144 | ||
145 | static void tegra_gpio_irq_ack(unsigned int irq) | |
146 | { | |
147 | int gpio = irq - INT_GPIO_BASE; | |
148 | ||
149 | __raw_writel(1 << GPIO_BIT(gpio), GPIO_INT_CLR(gpio)); | |
150 | } | |
151 | ||
152 | static void tegra_gpio_irq_mask(unsigned int irq) | |
153 | { | |
154 | int gpio = irq - INT_GPIO_BASE; | |
155 | ||
156 | tegra_gpio_mask_write(GPIO_MSK_INT_ENB(gpio), gpio, 0); | |
157 | } | |
158 | ||
159 | static void tegra_gpio_irq_unmask(unsigned int irq) | |
160 | { | |
161 | int gpio = irq - INT_GPIO_BASE; | |
162 | ||
163 | tegra_gpio_mask_write(GPIO_MSK_INT_ENB(gpio), gpio, 1); | |
164 | } | |
165 | ||
166 | static int tegra_gpio_irq_set_type(unsigned int irq, unsigned int type) | |
167 | { | |
168 | int gpio = irq - INT_GPIO_BASE; | |
169 | struct tegra_gpio_bank *bank = get_irq_chip_data(irq); | |
170 | int port = GPIO_PORT(gpio); | |
171 | int lvl_type; | |
172 | int val; | |
173 | unsigned long flags; | |
174 | ||
175 | switch (type & IRQ_TYPE_SENSE_MASK) { | |
176 | case IRQ_TYPE_EDGE_RISING: | |
177 | lvl_type = GPIO_INT_LVL_EDGE_RISING; | |
178 | break; | |
179 | ||
180 | case IRQ_TYPE_EDGE_FALLING: | |
181 | lvl_type = GPIO_INT_LVL_EDGE_FALLING; | |
182 | break; | |
183 | ||
184 | case IRQ_TYPE_EDGE_BOTH: | |
185 | lvl_type = GPIO_INT_LVL_EDGE_BOTH; | |
186 | break; | |
187 | ||
188 | case IRQ_TYPE_LEVEL_HIGH: | |
189 | lvl_type = GPIO_INT_LVL_LEVEL_HIGH; | |
190 | break; | |
191 | ||
192 | case IRQ_TYPE_LEVEL_LOW: | |
193 | lvl_type = GPIO_INT_LVL_LEVEL_LOW; | |
194 | break; | |
195 | ||
196 | default: | |
197 | return -EINVAL; | |
198 | } | |
199 | ||
200 | spin_lock_irqsave(&bank->lvl_lock[port], flags); | |
201 | ||
202 | val = __raw_readl(GPIO_INT_LVL(gpio)); | |
203 | val &= ~(GPIO_INT_LVL_MASK << GPIO_BIT(gpio)); | |
204 | val |= lvl_type << GPIO_BIT(gpio); | |
205 | __raw_writel(val, GPIO_INT_LVL(gpio)); | |
206 | ||
207 | spin_unlock_irqrestore(&bank->lvl_lock[port], flags); | |
208 | ||
209 | if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH)) | |
210 | __set_irq_handler_unlocked(irq, handle_level_irq); | |
211 | else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING)) | |
212 | __set_irq_handler_unlocked(irq, handle_edge_irq); | |
213 | ||
214 | return 0; | |
215 | } | |
216 | ||
217 | static void tegra_gpio_irq_handler(unsigned int irq, struct irq_desc *desc) | |
218 | { | |
219 | struct tegra_gpio_bank *bank; | |
220 | int port; | |
221 | int pin; | |
222 | int unmasked = 0; | |
223 | ||
224 | desc->chip->ack(irq); | |
225 | ||
226 | bank = get_irq_data(irq); | |
227 | ||
228 | for (port = 0; port < 4; port++) { | |
229 | int gpio = tegra_gpio_compose(bank->bank, port, 0); | |
230 | unsigned long sta = __raw_readl(GPIO_INT_STA(gpio)) & | |
231 | __raw_readl(GPIO_INT_ENB(gpio)); | |
232 | u32 lvl = __raw_readl(GPIO_INT_LVL(gpio)); | |
233 | ||
234 | for_each_set_bit(pin, &sta, 8) { | |
235 | __raw_writel(1 << pin, GPIO_INT_CLR(gpio)); | |
236 | ||
237 | /* if gpio is edge triggered, clear condition | |
238 | * before executing the hander so that we don't | |
239 | * miss edges | |
240 | */ | |
241 | if (lvl & (0x100 << pin)) { | |
242 | unmasked = 1; | |
243 | desc->chip->unmask(irq); | |
244 | } | |
245 | ||
246 | generic_handle_irq(gpio_to_irq(gpio + pin)); | |
247 | } | |
248 | } | |
249 | ||
250 | if (!unmasked) | |
251 | desc->chip->unmask(irq); | |
252 | ||
253 | } | |
254 | ||
2e47b8b3 CC |
255 | #ifdef CONFIG_PM |
256 | void tegra_gpio_resume(void) | |
257 | { | |
258 | unsigned long flags; | |
259 | int b, p, i; | |
260 | ||
261 | local_irq_save(flags); | |
262 | ||
263 | for (b = 0; b < ARRAY_SIZE(tegra_gpio_banks); b++) { | |
264 | struct tegra_gpio_bank *bank = &tegra_gpio_banks[b]; | |
265 | ||
266 | for (p = 0; p < ARRAY_SIZE(bank->oe); p++) { | |
267 | unsigned int gpio = (b<<5) | (p<<3); | |
268 | __raw_writel(bank->cnf[p], GPIO_CNF(gpio)); | |
269 | __raw_writel(bank->out[p], GPIO_OUT(gpio)); | |
270 | __raw_writel(bank->oe[p], GPIO_OE(gpio)); | |
271 | __raw_writel(bank->int_lvl[p], GPIO_INT_LVL(gpio)); | |
272 | __raw_writel(bank->int_enb[p], GPIO_INT_ENB(gpio)); | |
273 | } | |
274 | } | |
275 | ||
276 | local_irq_restore(flags); | |
277 | ||
278 | for (i = INT_GPIO_BASE; i < (INT_GPIO_BASE + TEGRA_NR_GPIOS); i++) { | |
279 | struct irq_desc *desc = irq_to_desc(i); | |
280 | if (!desc || (desc->status & IRQ_WAKEUP)) | |
281 | continue; | |
282 | enable_irq(i); | |
283 | } | |
284 | } | |
285 | ||
286 | void tegra_gpio_suspend(void) | |
287 | { | |
288 | unsigned long flags; | |
289 | int b, p, i; | |
290 | ||
291 | for (i = INT_GPIO_BASE; i < (INT_GPIO_BASE + TEGRA_NR_GPIOS); i++) { | |
292 | struct irq_desc *desc = irq_to_desc(i); | |
293 | if (!desc) | |
294 | continue; | |
295 | if (desc->status & IRQ_WAKEUP) { | |
296 | int gpio = i - INT_GPIO_BASE; | |
297 | pr_debug("gpio %d.%d is wakeup\n", gpio/8, gpio&7); | |
298 | continue; | |
299 | } | |
300 | disable_irq(i); | |
301 | } | |
302 | ||
303 | local_irq_save(flags); | |
304 | for (b = 0; b < ARRAY_SIZE(tegra_gpio_banks); b++) { | |
305 | struct tegra_gpio_bank *bank = &tegra_gpio_banks[b]; | |
306 | ||
307 | for (p = 0; p < ARRAY_SIZE(bank->oe); p++) { | |
308 | unsigned int gpio = (b<<5) | (p<<3); | |
309 | bank->cnf[p] = __raw_readl(GPIO_CNF(gpio)); | |
310 | bank->out[p] = __raw_readl(GPIO_OUT(gpio)); | |
311 | bank->oe[p] = __raw_readl(GPIO_OE(gpio)); | |
312 | bank->int_enb[p] = __raw_readl(GPIO_INT_ENB(gpio)); | |
313 | bank->int_lvl[p] = __raw_readl(GPIO_INT_LVL(gpio)); | |
314 | } | |
315 | } | |
316 | local_irq_restore(flags); | |
317 | } | |
318 | ||
319 | static int tegra_gpio_wake_enable(unsigned int irq, unsigned int enable) | |
320 | { | |
321 | struct tegra_gpio_bank *bank = get_irq_chip_data(irq); | |
322 | return set_irq_wake(bank->irq, enable); | |
323 | } | |
324 | #endif | |
3c92db9a EG |
325 | |
326 | static struct irq_chip tegra_gpio_irq_chip = { | |
327 | .name = "GPIO", | |
328 | .ack = tegra_gpio_irq_ack, | |
329 | .mask = tegra_gpio_irq_mask, | |
330 | .unmask = tegra_gpio_irq_unmask, | |
331 | .set_type = tegra_gpio_irq_set_type, | |
2e47b8b3 CC |
332 | #ifdef CONFIG_PM |
333 | .set_wake = tegra_gpio_wake_enable, | |
334 | #endif | |
3c92db9a EG |
335 | }; |
336 | ||
337 | ||
338 | /* This lock class tells lockdep that GPIO irqs are in a different | |
339 | * category than their parents, so it won't report false recursion. | |
340 | */ | |
341 | static struct lock_class_key gpio_lock_class; | |
342 | ||
343 | static int __init tegra_gpio_init(void) | |
344 | { | |
345 | struct tegra_gpio_bank *bank; | |
346 | int i; | |
347 | int j; | |
348 | ||
349 | for (i = 0; i < 7; i++) { | |
350 | for (j = 0; j < 4; j++) { | |
351 | int gpio = tegra_gpio_compose(i, j, 0); | |
352 | __raw_writel(0x00, GPIO_INT_ENB(gpio)); | |
353 | } | |
354 | } | |
355 | ||
356 | gpiochip_add(&tegra_gpio_chip); | |
357 | ||
2e47b8b3 | 358 | for (i = INT_GPIO_BASE; i < (INT_GPIO_BASE + TEGRA_NR_GPIOS); i++) { |
3c92db9a EG |
359 | bank = &tegra_gpio_banks[GPIO_BANK(irq_to_gpio(i))]; |
360 | ||
361 | lockdep_set_class(&irq_desc[i].lock, &gpio_lock_class); | |
362 | set_irq_chip_data(i, bank); | |
363 | set_irq_chip(i, &tegra_gpio_irq_chip); | |
364 | set_irq_handler(i, handle_simple_irq); | |
365 | set_irq_flags(i, IRQF_VALID); | |
366 | } | |
367 | ||
368 | for (i = 0; i < ARRAY_SIZE(tegra_gpio_banks); i++) { | |
369 | bank = &tegra_gpio_banks[i]; | |
370 | ||
371 | set_irq_chained_handler(bank->irq, tegra_gpio_irq_handler); | |
372 | set_irq_data(bank->irq, bank); | |
373 | ||
374 | for (j = 0; j < 4; j++) | |
375 | spin_lock_init(&bank->lvl_lock[j]); | |
376 | } | |
377 | ||
378 | return 0; | |
379 | } | |
380 | ||
381 | postcore_initcall(tegra_gpio_init); | |
382 | ||
383 | #ifdef CONFIG_DEBUG_FS | |
384 | ||
385 | #include <linux/debugfs.h> | |
386 | #include <linux/seq_file.h> | |
387 | ||
388 | static int dbg_gpio_show(struct seq_file *s, void *unused) | |
389 | { | |
390 | int i; | |
391 | int j; | |
392 | ||
393 | for (i = 0; i < 7; i++) { | |
394 | for (j = 0; j < 4; j++) { | |
395 | int gpio = tegra_gpio_compose(i, j, 0); | |
2e47b8b3 CC |
396 | seq_printf(s, |
397 | "%d:%d %02x %02x %02x %02x %02x %02x %06x\n", | |
398 | i, j, | |
399 | __raw_readl(GPIO_CNF(gpio)), | |
400 | __raw_readl(GPIO_OE(gpio)), | |
401 | __raw_readl(GPIO_OUT(gpio)), | |
402 | __raw_readl(GPIO_IN(gpio)), | |
403 | __raw_readl(GPIO_INT_STA(gpio)), | |
404 | __raw_readl(GPIO_INT_ENB(gpio)), | |
405 | __raw_readl(GPIO_INT_LVL(gpio))); | |
3c92db9a EG |
406 | } |
407 | } | |
408 | return 0; | |
409 | } | |
410 | ||
411 | static int dbg_gpio_open(struct inode *inode, struct file *file) | |
412 | { | |
413 | return single_open(file, dbg_gpio_show, &inode->i_private); | |
414 | } | |
415 | ||
416 | static const struct file_operations debug_fops = { | |
417 | .open = dbg_gpio_open, | |
418 | .read = seq_read, | |
419 | .llseek = seq_lseek, | |
420 | .release = single_release, | |
421 | }; | |
422 | ||
423 | static int __init tegra_gpio_debuginit(void) | |
424 | { | |
425 | (void) debugfs_create_file("tegra_gpio", S_IRUGO, | |
426 | NULL, NULL, &debug_fops); | |
427 | return 0; | |
428 | } | |
429 | late_initcall(tegra_gpio_debuginit); | |
430 | #endif |