[deliverable/linux.git] / arch / arm / mach-tegra / sleep.h

/*
 * Copyright (c) 2010-2013, NVIDIA Corporation. All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
 * version 2, as published by the Free Software Foundation.
 *
 * This program is distributed in the hope it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 */

#ifndef __MACH_TEGRA_SLEEP_H
#define __MACH_TEGRA_SLEEP_H

#include "iomap.h"
#include "irammap.h"

#define TEGRA_ARM_PERIF_VIRT (TEGRA_ARM_PERIF_BASE - IO_CPU_PHYS \
					+ IO_CPU_VIRT)
#define TEGRA_FLOW_CTRL_VIRT (TEGRA_FLOW_CTRL_BASE - IO_PPSB_PHYS \
					+ IO_PPSB_VIRT)
#define TEGRA_CLK_RESET_VIRT (TEGRA_CLK_RESET_BASE - IO_PPSB_PHYS \
					+ IO_PPSB_VIRT)
#define TEGRA_APB_MISC_VIRT (TEGRA_APB_MISC_BASE - IO_APB_PHYS \
					+ IO_APB_VIRT)
#define TEGRA_PMC_VIRT	(TEGRA_PMC_BASE - IO_APB_PHYS + IO_APB_VIRT)

#define TEGRA_IRAM_RESET_BASE_VIRT (IO_IRAM_VIRT + \
				TEGRA_IRAM_RESET_HANDLER_OFFSET)

/* PMC_SCRATCH37-39 and 41 are used for tegra_pen_lock and idle */
#define PMC_SCRATCH37	0x130
#define PMC_SCRATCH38	0x134
#define PMC_SCRATCH39	0x138
#define PMC_SCRATCH41	0x140

#ifdef CONFIG_ARCH_TEGRA_2x_SOC
#define CPU_RESETTABLE		2
#define CPU_RESETTABLE_SOON	1
#define CPU_NOT_RESETTABLE	0
#endif

/* flag of tegra_disable_clean_inv_dcache to do LoUIS or all */
#define TEGRA_FLUSH_CACHE_LOUIS	0
#define TEGRA_FLUSH_CACHE_ALL	1

#ifdef __ASSEMBLY__
/* waits until the microsecond counter (base) is > rn */
.macro wait_until, rn, base, tmp
	add	\rn, \rn, #1
1001:	ldr	\tmp, [\base]
	cmp	\tmp, \rn
	bmi	1001b
.endm

/* returns the offset of the flow controller halt register for a cpu */
.macro cpu_to_halt_reg rd, rcpu
	cmp	\rcpu, #0
	subne	\rd, \rcpu, #1
	movne	\rd, \rd, lsl #3
	addne	\rd, \rd, #0x14
	moveq	\rd, #0
.endm

/* returns the offset of the flow controller csr register for a cpu */
.macro cpu_to_csr_reg rd, rcpu
	cmp	\rcpu, #0
	subne	\rd, \rcpu, #1
	movne	\rd, \rd, lsl #3
	addne	\rd, \rd, #0x18
	moveq	\rd, #8
.endm

/* returns the ID of the current processor */
.macro cpu_id, rd
	mrc	p15, 0, \rd, c0, c0, 5
	and	\rd, \rd, #0xF
.endm

/* loads a 32-bit value into a register without a data access */
.macro mov32, reg, val
	movw	\reg, #:lower16:\val
	movt	\reg, #:upper16:\val
.endm

/* Marco to check CPU part num */
.macro check_cpu_part_num part_num, tmp1, tmp2
	mrc	p15, 0, \tmp1, c0, c0, 0
	ubfx	\tmp1, \tmp1, #4, #12
	mov32	\tmp2, \part_num
	cmp	\tmp1, \tmp2
.endm

/* Macro to exit SMP coherency. */
.macro exit_smp, tmp1, tmp2
	mrc	p15, 0, \tmp1, c1, c0, 1	@ ACTLR
	bic	\tmp1, \tmp1, #(1<<6) | (1<<0)	@ clear ACTLR.SMP | ACTLR.FW
	mcr	p15, 0, \tmp1, c1, c0, 1	@ ACTLR
	isb
#ifdef CONFIG_HAVE_ARM_SCU
	check_cpu_part_num 0xc09, \tmp1, \tmp2
	mrceq	p15, 0, \tmp1, c0, c0, 5
	andeq	\tmp1, \tmp1, #0xF
	moveq	\tmp1, \tmp1, lsl #2
	moveq	\tmp2, #0xf
	moveq	\tmp2, \tmp2, lsl \tmp1
	ldreq	\tmp1, =(TEGRA_ARM_PERIF_VIRT + 0xC)
	streq	\tmp2, [\tmp1]			@ invalidate SCU tags for CPU
	dsb
#endif
.endm

/* Macro to check Tegra revision */
#define APB_MISC_GP_HIDREV	0x804
.macro tegra_get_soc_id base, tmp1
	mov32	\tmp1, \base
	ldr	\tmp1, [\tmp1, #APB_MISC_GP_HIDREV]
	and	\tmp1, \tmp1, #0xff00
	mov	\tmp1, \tmp1, lsr #8
.endm

#else
void tegra_pen_lock(void);
void tegra_pen_unlock(void);
void tegra_resume(void);
int tegra_sleep_cpu_finish(unsigned long);
void tegra_disable_clean_inv_dcache(u32 flag);

#ifdef CONFIG_HOTPLUG_CPU
void tegra20_hotplug_shutdown(void);
void tegra30_hotplug_shutdown(void);
#endif

void tegra20_cpu_shutdown(int cpu);
int tegra20_cpu_is_resettable_soon(void);
void tegra20_cpu_clear_resettable(void);
#ifdef CONFIG_ARCH_TEGRA_2x_SOC
void tegra20_cpu_set_resettable_soon(void);
#else
static inline void tegra20_cpu_set_resettable_soon(void) {}
#endif

int tegra20_sleep_cpu_secondary_finish(unsigned long);
void tegra20_tear_down_cpu(void);
int tegra30_sleep_cpu_secondary_finish(unsigned long);
void tegra30_tear_down_cpu(void);

#endif
#endif
Commit	Line	Data
c2be5bfc	1	/*
7469688e	2	* Copyright (c) 2010-2013, NVIDIA Corporation. All rights reserved.
c2be5bfc JL	3	*
	4	* This program is free software; you can redistribute it and/or modify it
	5	* under the terms and conditions of the GNU General Public License,
	6	* version 2, as published by the Free Software Foundation.
	7	*
	8	* This program is distributed in the hope it will be useful, but WITHOUT
	9	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	10	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	11	* more details.
	12	*
	13	* You should have received a copy of the GNU General Public License
	14	* along with this program. If not, see <http://www.gnu.org/licenses/>.
	15	*/
	16
	17	#ifndef __MACH_TEGRA_SLEEP_H
	18	#define __MACH_TEGRA_SLEEP_H
	19
2be39c07	20	#include "iomap.h"
4d48edb3	21	#include "irammap.h"
c2be5bfc	22
59b0f682 JL	23	#define TEGRA_ARM_PERIF_VIRT (TEGRA_ARM_PERIF_BASE - IO_CPU_PHYS \
59b0f682 JL	24	+ IO_CPU_VIRT)
c2be5bfc JL	25	#define TEGRA_FLOW_CTRL_VIRT (TEGRA_FLOW_CTRL_BASE - IO_PPSB_PHYS \
c2be5bfc JL	26	+ IO_PPSB_VIRT)
453689e4 JL	27	#define TEGRA_CLK_RESET_VIRT (TEGRA_CLK_RESET_BASE - IO_PPSB_PHYS \
453689e4 JL	28	+ IO_PPSB_VIRT)
33d5c019 JL	29	#define TEGRA_APB_MISC_VIRT (TEGRA_APB_MISC_BASE - IO_APB_PHYS \
33d5c019 JL	30	+ IO_APB_VIRT)
5c1350bd JL	31	#define TEGRA_PMC_VIRT (TEGRA_PMC_BASE - IO_APB_PHYS + IO_APB_VIRT)
5c1350bd JL	32
4d48edb3 DO	33	#define TEGRA_IRAM_RESET_BASE_VIRT (IO_IRAM_VIRT + \
	34	TEGRA_IRAM_RESET_HANDLER_OFFSET)
	35
5c1350bd JL	36	/* PMC_SCRATCH37-39 and 41 are used for tegra_pen_lock and idle */
	37	#define PMC_SCRATCH37 0x130
	38	#define PMC_SCRATCH38 0x134
	39	#define PMC_SCRATCH39 0x138
	40	#define PMC_SCRATCH41 0x140
	41
	42	#ifdef CONFIG_ARCH_TEGRA_2x_SOC
	43	#define CPU_RESETTABLE 2
	44	#define CPU_RESETTABLE_SOON 1
	45	#define CPU_NOT_RESETTABLE 0
	46	#endif
c2be5bfc	47
ac2527bf JL	48	/* flag of tegra_disable_clean_inv_dcache to do LoUIS or all */
	49	#define TEGRA_FLUSH_CACHE_LOUIS 0
	50	#define TEGRA_FLUSH_CACHE_ALL 1
	51
c2be5bfc	52	#ifdef __ASSEMBLY__
e7a932b1 JL	53	/* waits until the microsecond counter (base) is > rn */
	54	.macro wait_until, rn, base, tmp
	55	add \rn, \rn, #1
	56	1001: ldr \tmp, [\base]
	57	cmp \tmp, \rn
	58	bmi 1001b
	59	.endm
	60
c2be5bfc JL	61	/* returns the offset of the flow controller halt register for a cpu */
	62	.macro cpu_to_halt_reg rd, rcpu
	63	cmp \rcpu, #0
	64	subne \rd, \rcpu, #1
	65	movne \rd, \rd, lsl #3
	66	addne \rd, \rd, #0x14
	67	moveq \rd, #0
	68	.endm
	69
	70	/* returns the offset of the flow controller csr register for a cpu */
	71	.macro cpu_to_csr_reg rd, rcpu
	72	cmp \rcpu, #0
	73	subne \rd, \rcpu, #1
	74	movne \rd, \rd, lsl #3
	75	addne \rd, \rd, #0x18
	76	moveq \rd, #8
	77	.endm
	78
	79	/* returns the ID of the current processor */
	80	.macro cpu_id, rd
	81	mrc p15, 0, \rd, c0, c0, 5
	82	and \rd, \rd, #0xF
	83	.endm
	84
	85	/* loads a 32-bit value into a register without a data access */
	86	.macro mov32, reg, val
	87	movw \reg, #:lower16:\val
	88	movt \reg, #:upper16:\val
	89	.endm
59b0f682	90
f6d06f33 JL	91	/* Marco to check CPU part num */
	92	.macro check_cpu_part_num part_num, tmp1, tmp2
	93	mrc p15, 0, \tmp1, c0, c0, 0
	94	ubfx \tmp1, \tmp1, #4, #12
	95	mov32 \tmp2, \part_num
	96	cmp \tmp1, \tmp2
	97	.endm
	98
59b0f682 JL	99	/* Macro to exit SMP coherency. */
	100	.macro exit_smp, tmp1, tmp2
	101	mrc p15, 0, \tmp1, c1, c0, 1 @ ACTLR
	102	bic \tmp1, \tmp1, #(1<<6) \| (1<<0) @ clear ACTLR.SMP \| ACTLR.FW
	103	mcr p15, 0, \tmp1, c1, c0, 1 @ ACTLR
	104	isb
f6d06f33 JL	105	#ifdef CONFIG_HAVE_ARM_SCU
	106	check_cpu_part_num 0xc09, \tmp1, \tmp2
	107	mrceq p15, 0, \tmp1, c0, c0, 5
	108	andeq \tmp1, \tmp1, #0xF
	109	moveq \tmp1, \tmp1, lsl #2
	110	moveq \tmp2, #0xf
	111	moveq \tmp2, \tmp2, lsl \tmp1
	112	ldreq \tmp1, =(TEGRA_ARM_PERIF_VIRT + 0xC)
	113	streq \tmp2, [\tmp1] @ invalidate SCU tags for CPU
59b0f682	114	dsb
f6d06f33	115	#endif
59b0f682	116	.endm
29a0e7be	117
4b3e2eda JL	118	/* Macro to check Tegra revision */
	119	#define APB_MISC_GP_HIDREV 0x804
	120	.macro tegra_get_soc_id base, tmp1
	121	mov32 \tmp1, \base
	122	ldr \tmp1, [\tmp1, #APB_MISC_GP_HIDREV]
	123	and \tmp1, \tmp1, #0xff00
	124	mov \tmp1, \tmp1, lsr #8
	125	.endm
	126
59b0f682	127	#else
5c1350bd JL	128	void tegra_pen_lock(void);
5c1350bd JL	129	void tegra_pen_unlock(void);
d3f29365	130	void tegra_resume(void);
d552920a	131	int tegra_sleep_cpu_finish(unsigned long);
ac2527bf	132	void tegra_disable_clean_inv_dcache(u32 flag);
59b0f682 JL	133
59b0f682 JL	134	#ifdef CONFIG_HOTPLUG_CPU
7469688e HD	135	void tegra20_hotplug_shutdown(void);
7469688e HD	136	void tegra30_hotplug_shutdown(void);
59b0f682 JL	137	#endif
59b0f682 JL	138
1d328606 JL	139	void tegra20_cpu_shutdown(int cpu);
1d328606 JL	140	int tegra20_cpu_is_resettable_soon(void);
5c1350bd JL	141	void tegra20_cpu_clear_resettable(void);
	142	#ifdef CONFIG_ARCH_TEGRA_2x_SOC
	143	void tegra20_cpu_set_resettable_soon(void);
	144	#else
	145	static inline void tegra20_cpu_set_resettable_soon(void) {}
	146	#endif
	147
	148	int tegra20_sleep_cpu_secondary_finish(unsigned long);
1d328606	149	void tegra20_tear_down_cpu(void);
d457ef35	150	int tegra30_sleep_cpu_secondary_finish(unsigned long);
d552920a	151	void tegra30_tear_down_cpu(void);
d457ef35	152
c2be5bfc JL	153	#endif
c2be5bfc JL	154	#endif