Commit | Line | Data |
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d8611961 CC |
1 | /* |
2 | * arch/arm/mach-tegra/tegra2_clocks.c | |
3 | * | |
4 | * Copyright (C) 2010 Google, Inc. | |
5 | * | |
6 | * Author: | |
7 | * Colin Cross <ccross@google.com> | |
8 | * | |
9 | * This software is licensed under the terms of the GNU General Public | |
10 | * License version 2, as published by the Free Software Foundation, and | |
11 | * may be copied, distributed, and modified under those terms. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | */ | |
19 | ||
20 | #include <linux/kernel.h> | |
21 | #include <linux/module.h> | |
22 | #include <linux/list.h> | |
23 | #include <linux/spinlock.h> | |
24 | #include <linux/delay.h> | |
25 | #include <linux/io.h> | |
6d803ba7 | 26 | #include <linux/clkdev.h> |
4729fd7a | 27 | #include <linux/clk.h> |
d8611961 CC |
28 | |
29 | #include <mach/iomap.h> | |
2ea67fd1 | 30 | #include <mach/suspend.h> |
d8611961 CC |
31 | |
32 | #include "clock.h" | |
71fc84cc | 33 | #include "fuse.h" |
6d296828 | 34 | #include "tegra2_emc.h" |
d8611961 CC |
35 | |
36 | #define RST_DEVICES 0x004 | |
37 | #define RST_DEVICES_SET 0x300 | |
38 | #define RST_DEVICES_CLR 0x304 | |
71fc84cc | 39 | #define RST_DEVICES_NUM 3 |
d8611961 CC |
40 | |
41 | #define CLK_OUT_ENB 0x010 | |
42 | #define CLK_OUT_ENB_SET 0x320 | |
43 | #define CLK_OUT_ENB_CLR 0x324 | |
71fc84cc CC |
44 | #define CLK_OUT_ENB_NUM 3 |
45 | ||
46 | #define CLK_MASK_ARM 0x44 | |
47 | #define MISC_CLK_ENB 0x48 | |
d8611961 CC |
48 | |
49 | #define OSC_CTRL 0x50 | |
50 | #define OSC_CTRL_OSC_FREQ_MASK (3<<30) | |
51 | #define OSC_CTRL_OSC_FREQ_13MHZ (0<<30) | |
52 | #define OSC_CTRL_OSC_FREQ_19_2MHZ (1<<30) | |
53 | #define OSC_CTRL_OSC_FREQ_12MHZ (2<<30) | |
54 | #define OSC_CTRL_OSC_FREQ_26MHZ (3<<30) | |
cea62c87 | 55 | #define OSC_CTRL_MASK (0x3f2 | OSC_CTRL_OSC_FREQ_MASK) |
d8611961 CC |
56 | |
57 | #define OSC_FREQ_DET 0x58 | |
58 | #define OSC_FREQ_DET_TRIG (1<<31) | |
59 | ||
60 | #define OSC_FREQ_DET_STATUS 0x5C | |
61 | #define OSC_FREQ_DET_BUSY (1<<31) | |
62 | #define OSC_FREQ_DET_CNT_MASK 0xFFFF | |
63 | ||
71fc84cc CC |
64 | #define PERIPH_CLK_SOURCE_I2S1 0x100 |
65 | #define PERIPH_CLK_SOURCE_EMC 0x19c | |
66 | #define PERIPH_CLK_SOURCE_OSC 0x1fc | |
67 | #define PERIPH_CLK_SOURCE_NUM \ | |
68 | ((PERIPH_CLK_SOURCE_OSC - PERIPH_CLK_SOURCE_I2S1) / 4) | |
69 | ||
d8611961 CC |
70 | #define PERIPH_CLK_SOURCE_MASK (3<<30) |
71 | #define PERIPH_CLK_SOURCE_SHIFT 30 | |
72 | #define PERIPH_CLK_SOURCE_ENABLE (1<<28) | |
71fc84cc CC |
73 | #define PERIPH_CLK_SOURCE_DIVU71_MASK 0xFF |
74 | #define PERIPH_CLK_SOURCE_DIVU16_MASK 0xFFFF | |
d8611961 CC |
75 | #define PERIPH_CLK_SOURCE_DIV_SHIFT 0 |
76 | ||
9743b389 CC |
77 | #define SDMMC_CLK_INT_FB_SEL (1 << 23) |
78 | #define SDMMC_CLK_INT_FB_DLY_SHIFT 16 | |
79 | #define SDMMC_CLK_INT_FB_DLY_MASK (0xF << SDMMC_CLK_INT_FB_DLY_SHIFT) | |
80 | ||
d8611961 CC |
81 | #define PLL_BASE 0x0 |
82 | #define PLL_BASE_BYPASS (1<<31) | |
83 | #define PLL_BASE_ENABLE (1<<30) | |
84 | #define PLL_BASE_REF_ENABLE (1<<29) | |
85 | #define PLL_BASE_OVERRIDE (1<<28) | |
d8611961 CC |
86 | #define PLL_BASE_DIVP_MASK (0x7<<20) |
87 | #define PLL_BASE_DIVP_SHIFT 20 | |
88 | #define PLL_BASE_DIVN_MASK (0x3FF<<8) | |
89 | #define PLL_BASE_DIVN_SHIFT 8 | |
90 | #define PLL_BASE_DIVM_MASK (0x1F) | |
91 | #define PLL_BASE_DIVM_SHIFT 0 | |
92 | ||
93 | #define PLL_OUT_RATIO_MASK (0xFF<<8) | |
94 | #define PLL_OUT_RATIO_SHIFT 8 | |
95 | #define PLL_OUT_OVERRIDE (1<<2) | |
96 | #define PLL_OUT_CLKEN (1<<1) | |
97 | #define PLL_OUT_RESET_DISABLE (1<<0) | |
98 | ||
99 | #define PLL_MISC(c) (((c)->flags & PLL_ALT_MISC_REG) ? 0x4 : 0xc) | |
71fc84cc | 100 | |
d8611961 | 101 | #define PLL_MISC_DCCON_SHIFT 20 |
d8611961 CC |
102 | #define PLL_MISC_CPCON_SHIFT 8 |
103 | #define PLL_MISC_CPCON_MASK (0xF<<PLL_MISC_CPCON_SHIFT) | |
104 | #define PLL_MISC_LFCON_SHIFT 4 | |
105 | #define PLL_MISC_LFCON_MASK (0xF<<PLL_MISC_LFCON_SHIFT) | |
106 | #define PLL_MISC_VCOCON_SHIFT 0 | |
107 | #define PLL_MISC_VCOCON_MASK (0xF<<PLL_MISC_VCOCON_SHIFT) | |
108 | ||
71fc84cc CC |
109 | #define PLLU_BASE_POST_DIV (1<<20) |
110 | ||
d8611961 CC |
111 | #define PLLD_MISC_CLKENABLE (1<<30) |
112 | #define PLLD_MISC_DIV_RST (1<<23) | |
113 | #define PLLD_MISC_DCCON_SHIFT 12 | |
114 | ||
8d685bc5 MR |
115 | #define PLLE_MISC_READY (1 << 15) |
116 | ||
f1519611 CC |
117 | #define PERIPH_CLK_TO_ENB_REG(c) ((c->u.periph.clk_num / 32) * 4) |
118 | #define PERIPH_CLK_TO_ENB_SET_REG(c) ((c->u.periph.clk_num / 32) * 8) | |
119 | #define PERIPH_CLK_TO_ENB_BIT(c) (1 << (c->u.periph.clk_num % 32)) | |
d8611961 CC |
120 | |
121 | #define SUPER_CLK_MUX 0x00 | |
122 | #define SUPER_STATE_SHIFT 28 | |
123 | #define SUPER_STATE_MASK (0xF << SUPER_STATE_SHIFT) | |
124 | #define SUPER_STATE_STANDBY (0x0 << SUPER_STATE_SHIFT) | |
125 | #define SUPER_STATE_IDLE (0x1 << SUPER_STATE_SHIFT) | |
126 | #define SUPER_STATE_RUN (0x2 << SUPER_STATE_SHIFT) | |
127 | #define SUPER_STATE_IRQ (0x3 << SUPER_STATE_SHIFT) | |
128 | #define SUPER_STATE_FIQ (0x4 << SUPER_STATE_SHIFT) | |
129 | #define SUPER_SOURCE_MASK 0xF | |
130 | #define SUPER_FIQ_SOURCE_SHIFT 12 | |
131 | #define SUPER_IRQ_SOURCE_SHIFT 8 | |
132 | #define SUPER_RUN_SOURCE_SHIFT 4 | |
133 | #define SUPER_IDLE_SOURCE_SHIFT 0 | |
134 | ||
135 | #define SUPER_CLK_DIVIDER 0x04 | |
136 | ||
137 | #define BUS_CLK_DISABLE (1<<3) | |
138 | #define BUS_CLK_DIV_MASK 0x3 | |
139 | ||
cea62c87 CC |
140 | #define PMC_CTRL 0x0 |
141 | #define PMC_CTRL_BLINK_ENB (1 << 7) | |
142 | ||
143 | #define PMC_DPD_PADS_ORIDE 0x1c | |
144 | #define PMC_DPD_PADS_ORIDE_BLINK_ENB (1 << 20) | |
145 | ||
146 | #define PMC_BLINK_TIMER_DATA_ON_SHIFT 0 | |
147 | #define PMC_BLINK_TIMER_DATA_ON_MASK 0x7fff | |
148 | #define PMC_BLINK_TIMER_ENB (1 << 15) | |
149 | #define PMC_BLINK_TIMER_DATA_OFF_SHIFT 16 | |
150 | #define PMC_BLINK_TIMER_DATA_OFF_MASK 0xffff | |
151 | ||
d8611961 | 152 | static void __iomem *reg_clk_base = IO_ADDRESS(TEGRA_CLK_RESET_BASE); |
cea62c87 | 153 | static void __iomem *reg_pmc_base = IO_ADDRESS(TEGRA_PMC_BASE); |
d8611961 | 154 | |
4729fd7a CC |
155 | /* |
156 | * Some clocks share a register with other clocks. Any clock op that | |
157 | * non-atomically modifies a register used by another clock must lock | |
158 | * clock_register_lock first. | |
159 | */ | |
160 | static DEFINE_SPINLOCK(clock_register_lock); | |
161 | ||
78f379b5 CC |
162 | /* |
163 | * Some peripheral clocks share an enable bit, so refcount the enable bits | |
164 | * in registers CLK_ENABLE_L, CLK_ENABLE_H, and CLK_ENABLE_U | |
165 | */ | |
166 | static int tegra_periph_clk_enable_refcount[3 * 32]; | |
167 | ||
d8611961 CC |
168 | #define clk_writel(value, reg) \ |
169 | __raw_writel(value, (u32)reg_clk_base + (reg)) | |
170 | #define clk_readl(reg) \ | |
171 | __raw_readl((u32)reg_clk_base + (reg)) | |
cea62c87 CC |
172 | #define pmc_writel(value, reg) \ |
173 | __raw_writel(value, (u32)reg_pmc_base + (reg)) | |
174 | #define pmc_readl(reg) \ | |
175 | __raw_readl((u32)reg_pmc_base + (reg)) | |
d8611961 CC |
176 | |
177 | unsigned long clk_measure_input_freq(void) | |
178 | { | |
179 | u32 clock_autodetect; | |
180 | clk_writel(OSC_FREQ_DET_TRIG | 1, OSC_FREQ_DET); | |
181 | do {} while (clk_readl(OSC_FREQ_DET_STATUS) & OSC_FREQ_DET_BUSY); | |
182 | clock_autodetect = clk_readl(OSC_FREQ_DET_STATUS); | |
183 | if (clock_autodetect >= 732 - 3 && clock_autodetect <= 732 + 3) { | |
184 | return 12000000; | |
185 | } else if (clock_autodetect >= 794 - 3 && clock_autodetect <= 794 + 3) { | |
186 | return 13000000; | |
187 | } else if (clock_autodetect >= 1172 - 3 && clock_autodetect <= 1172 + 3) { | |
188 | return 19200000; | |
189 | } else if (clock_autodetect >= 1587 - 3 && clock_autodetect <= 1587 + 3) { | |
190 | return 26000000; | |
191 | } else { | |
192 | pr_err("%s: Unexpected clock autodetect value %d", __func__, clock_autodetect); | |
193 | BUG(); | |
194 | return 0; | |
195 | } | |
196 | } | |
197 | ||
71fc84cc | 198 | static int clk_div71_get_divider(unsigned long parent_rate, unsigned long rate) |
d8611961 | 199 | { |
71fc84cc CC |
200 | s64 divider_u71 = parent_rate * 2; |
201 | divider_u71 += rate - 1; | |
202 | do_div(divider_u71, rate); | |
d8611961 | 203 | |
71fc84cc CC |
204 | if (divider_u71 - 2 < 0) |
205 | return 0; | |
d8611961 | 206 | |
71fc84cc | 207 | if (divider_u71 - 2 > 255) |
d8611961 CC |
208 | return -EINVAL; |
209 | ||
210 | return divider_u71 - 2; | |
211 | } | |
212 | ||
71fc84cc | 213 | static int clk_div16_get_divider(unsigned long parent_rate, unsigned long rate) |
d8611961 | 214 | { |
71fc84cc | 215 | s64 divider_u16; |
d8611961 | 216 | |
71fc84cc CC |
217 | divider_u16 = parent_rate; |
218 | divider_u16 += rate - 1; | |
219 | do_div(divider_u16, rate); | |
d8611961 | 220 | |
71fc84cc CC |
221 | if (divider_u16 - 1 < 0) |
222 | return 0; | |
223 | ||
224 | if (divider_u16 - 1 > 255) | |
225 | return -EINVAL; | |
226 | ||
227 | return divider_u16 - 1; | |
228 | } | |
d8611961 CC |
229 | |
230 | /* clk_m functions */ | |
231 | static unsigned long tegra2_clk_m_autodetect_rate(struct clk *c) | |
232 | { | |
233 | u32 auto_clock_control = clk_readl(OSC_CTRL) & ~OSC_CTRL_OSC_FREQ_MASK; | |
234 | ||
235 | c->rate = clk_measure_input_freq(); | |
236 | switch (c->rate) { | |
237 | case 12000000: | |
238 | auto_clock_control |= OSC_CTRL_OSC_FREQ_12MHZ; | |
239 | break; | |
240 | case 13000000: | |
241 | auto_clock_control |= OSC_CTRL_OSC_FREQ_13MHZ; | |
242 | break; | |
243 | case 19200000: | |
244 | auto_clock_control |= OSC_CTRL_OSC_FREQ_19_2MHZ; | |
245 | break; | |
246 | case 26000000: | |
247 | auto_clock_control |= OSC_CTRL_OSC_FREQ_26MHZ; | |
248 | break; | |
249 | default: | |
250 | pr_err("%s: Unexpected clock rate %ld", __func__, c->rate); | |
251 | BUG(); | |
252 | } | |
253 | clk_writel(auto_clock_control, OSC_CTRL); | |
254 | return c->rate; | |
255 | } | |
256 | ||
257 | static void tegra2_clk_m_init(struct clk *c) | |
258 | { | |
259 | pr_debug("%s on clock %s\n", __func__, c->name); | |
260 | tegra2_clk_m_autodetect_rate(c); | |
261 | } | |
262 | ||
263 | static int tegra2_clk_m_enable(struct clk *c) | |
264 | { | |
265 | pr_debug("%s on clock %s\n", __func__, c->name); | |
266 | return 0; | |
267 | } | |
268 | ||
269 | static void tegra2_clk_m_disable(struct clk *c) | |
270 | { | |
271 | pr_debug("%s on clock %s\n", __func__, c->name); | |
272 | BUG(); | |
273 | } | |
274 | ||
275 | static struct clk_ops tegra_clk_m_ops = { | |
276 | .init = tegra2_clk_m_init, | |
277 | .enable = tegra2_clk_m_enable, | |
278 | .disable = tegra2_clk_m_disable, | |
279 | }; | |
280 | ||
2b84cb4f DZ |
281 | void tegra2_periph_reset_assert(struct clk *c) |
282 | { | |
283 | BUG_ON(!c->ops->reset); | |
284 | c->ops->reset(c, true); | |
285 | } | |
286 | ||
287 | void tegra2_periph_reset_deassert(struct clk *c) | |
288 | { | |
289 | BUG_ON(!c->ops->reset); | |
290 | c->ops->reset(c, false); | |
291 | } | |
292 | ||
d8611961 CC |
293 | /* super clock functions */ |
294 | /* "super clocks" on tegra have two-stage muxes and a clock skipping | |
295 | * super divider. We will ignore the clock skipping divider, since we | |
296 | * can't lower the voltage when using the clock skip, but we can if we | |
297 | * lower the PLL frequency. | |
298 | */ | |
299 | static void tegra2_super_clk_init(struct clk *c) | |
300 | { | |
301 | u32 val; | |
302 | int source; | |
303 | int shift; | |
304 | const struct clk_mux_sel *sel; | |
305 | val = clk_readl(c->reg + SUPER_CLK_MUX); | |
306 | c->state = ON; | |
307 | BUG_ON(((val & SUPER_STATE_MASK) != SUPER_STATE_RUN) && | |
308 | ((val & SUPER_STATE_MASK) != SUPER_STATE_IDLE)); | |
309 | shift = ((val & SUPER_STATE_MASK) == SUPER_STATE_IDLE) ? | |
310 | SUPER_IDLE_SOURCE_SHIFT : SUPER_RUN_SOURCE_SHIFT; | |
311 | source = (val >> shift) & SUPER_SOURCE_MASK; | |
312 | for (sel = c->inputs; sel->input != NULL; sel++) { | |
313 | if (sel->value == source) | |
314 | break; | |
315 | } | |
316 | BUG_ON(sel->input == NULL); | |
317 | c->parent = sel->input; | |
d8611961 CC |
318 | } |
319 | ||
320 | static int tegra2_super_clk_enable(struct clk *c) | |
321 | { | |
322 | clk_writel(0, c->reg + SUPER_CLK_DIVIDER); | |
323 | return 0; | |
324 | } | |
325 | ||
326 | static void tegra2_super_clk_disable(struct clk *c) | |
327 | { | |
328 | pr_debug("%s on clock %s\n", __func__, c->name); | |
329 | ||
330 | /* oops - don't disable the CPU clock! */ | |
331 | BUG(); | |
332 | } | |
333 | ||
334 | static int tegra2_super_clk_set_parent(struct clk *c, struct clk *p) | |
335 | { | |
336 | u32 val; | |
337 | const struct clk_mux_sel *sel; | |
338 | int shift; | |
71fc84cc | 339 | |
6eab04a8 | 340 | val = clk_readl(c->reg + SUPER_CLK_MUX); |
d8611961 CC |
341 | BUG_ON(((val & SUPER_STATE_MASK) != SUPER_STATE_RUN) && |
342 | ((val & SUPER_STATE_MASK) != SUPER_STATE_IDLE)); | |
343 | shift = ((val & SUPER_STATE_MASK) == SUPER_STATE_IDLE) ? | |
344 | SUPER_IDLE_SOURCE_SHIFT : SUPER_RUN_SOURCE_SHIFT; | |
345 | for (sel = c->inputs; sel->input != NULL; sel++) { | |
346 | if (sel->input == p) { | |
d8611961 CC |
347 | val &= ~(SUPER_SOURCE_MASK << shift); |
348 | val |= sel->value << shift; | |
71fc84cc CC |
349 | |
350 | if (c->refcnt) | |
4729fd7a | 351 | clk_enable(p); |
71fc84cc | 352 | |
d8611961 | 353 | clk_writel(val, c->reg); |
71fc84cc CC |
354 | |
355 | if (c->refcnt && c->parent) | |
4729fd7a | 356 | clk_disable(c->parent); |
71fc84cc CC |
357 | |
358 | clk_reparent(c, p); | |
d8611961 CC |
359 | return 0; |
360 | } | |
361 | } | |
362 | return -EINVAL; | |
363 | } | |
364 | ||
9c7dc562 CC |
365 | /* |
366 | * Super clocks have "clock skippers" instead of dividers. Dividing using | |
367 | * a clock skipper does not allow the voltage to be scaled down, so instead | |
368 | * adjust the rate of the parent clock. This requires that the parent of a | |
369 | * super clock have no other children, otherwise the rate will change | |
370 | * underneath the other children. | |
371 | */ | |
372 | static int tegra2_super_clk_set_rate(struct clk *c, unsigned long rate) | |
373 | { | |
374 | return clk_set_rate(c->parent, rate); | |
375 | } | |
376 | ||
d8611961 CC |
377 | static struct clk_ops tegra_super_ops = { |
378 | .init = tegra2_super_clk_init, | |
379 | .enable = tegra2_super_clk_enable, | |
380 | .disable = tegra2_super_clk_disable, | |
381 | .set_parent = tegra2_super_clk_set_parent, | |
9c7dc562 | 382 | .set_rate = tegra2_super_clk_set_rate, |
71fc84cc CC |
383 | }; |
384 | ||
385 | /* virtual cpu clock functions */ | |
386 | /* some clocks can not be stopped (cpu, memory bus) while the SoC is running. | |
387 | To change the frequency of these clocks, the parent pll may need to be | |
388 | reprogrammed, so the clock must be moved off the pll, the pll reprogrammed, | |
389 | and then the clock moved back to the pll. To hide this sequence, a virtual | |
390 | clock handles it. | |
391 | */ | |
392 | static void tegra2_cpu_clk_init(struct clk *c) | |
393 | { | |
394 | } | |
395 | ||
396 | static int tegra2_cpu_clk_enable(struct clk *c) | |
397 | { | |
398 | return 0; | |
399 | } | |
400 | ||
401 | static void tegra2_cpu_clk_disable(struct clk *c) | |
402 | { | |
403 | pr_debug("%s on clock %s\n", __func__, c->name); | |
404 | ||
405 | /* oops - don't disable the CPU clock! */ | |
406 | BUG(); | |
407 | } | |
408 | ||
409 | static int tegra2_cpu_clk_set_rate(struct clk *c, unsigned long rate) | |
410 | { | |
411 | int ret; | |
89a5fb84 CC |
412 | /* |
413 | * Take an extra reference to the main pll so it doesn't turn | |
414 | * off when we move the cpu off of it | |
415 | */ | |
416 | clk_enable(c->u.cpu.main); | |
417 | ||
4729fd7a | 418 | ret = clk_set_parent(c->parent, c->u.cpu.backup); |
71fc84cc | 419 | if (ret) { |
f1519611 | 420 | pr_err("Failed to switch cpu to clock %s\n", c->u.cpu.backup->name); |
89a5fb84 | 421 | goto out; |
71fc84cc CC |
422 | } |
423 | ||
4729fd7a | 424 | if (rate == clk_get_rate(c->u.cpu.backup)) |
cea62c87 CC |
425 | goto out; |
426 | ||
4729fd7a | 427 | ret = clk_set_rate(c->u.cpu.main, rate); |
71fc84cc CC |
428 | if (ret) { |
429 | pr_err("Failed to change cpu pll to %lu\n", rate); | |
89a5fb84 | 430 | goto out; |
71fc84cc CC |
431 | } |
432 | ||
4729fd7a | 433 | ret = clk_set_parent(c->parent, c->u.cpu.main); |
71fc84cc | 434 | if (ret) { |
f1519611 | 435 | pr_err("Failed to switch cpu to clock %s\n", c->u.cpu.main->name); |
89a5fb84 | 436 | goto out; |
71fc84cc CC |
437 | } |
438 | ||
cea62c87 | 439 | out: |
89a5fb84 CC |
440 | clk_disable(c->u.cpu.main); |
441 | return ret; | |
71fc84cc CC |
442 | } |
443 | ||
444 | static struct clk_ops tegra_cpu_ops = { | |
445 | .init = tegra2_cpu_clk_init, | |
446 | .enable = tegra2_cpu_clk_enable, | |
447 | .disable = tegra2_cpu_clk_disable, | |
448 | .set_rate = tegra2_cpu_clk_set_rate, | |
d8611961 CC |
449 | }; |
450 | ||
9c7dc562 CC |
451 | /* virtual cop clock functions. Used to acquire the fake 'cop' clock to |
452 | * reset the COP block (i.e. AVP) */ | |
453 | static void tegra2_cop_clk_reset(struct clk *c, bool assert) | |
454 | { | |
455 | unsigned long reg = assert ? RST_DEVICES_SET : RST_DEVICES_CLR; | |
456 | ||
457 | pr_debug("%s %s\n", __func__, assert ? "assert" : "deassert"); | |
458 | clk_writel(1 << 1, reg); | |
459 | } | |
460 | ||
461 | static struct clk_ops tegra_cop_ops = { | |
462 | .reset = tegra2_cop_clk_reset, | |
463 | }; | |
464 | ||
d8611961 CC |
465 | /* bus clock functions */ |
466 | static void tegra2_bus_clk_init(struct clk *c) | |
467 | { | |
468 | u32 val = clk_readl(c->reg); | |
469 | c->state = ((val >> c->reg_shift) & BUS_CLK_DISABLE) ? OFF : ON; | |
470 | c->div = ((val >> c->reg_shift) & BUS_CLK_DIV_MASK) + 1; | |
471 | c->mul = 1; | |
d8611961 CC |
472 | } |
473 | ||
474 | static int tegra2_bus_clk_enable(struct clk *c) | |
475 | { | |
4729fd7a CC |
476 | u32 val; |
477 | unsigned long flags; | |
478 | ||
479 | spin_lock_irqsave(&clock_register_lock, flags); | |
480 | ||
481 | val = clk_readl(c->reg); | |
d8611961 CC |
482 | val &= ~(BUS_CLK_DISABLE << c->reg_shift); |
483 | clk_writel(val, c->reg); | |
4729fd7a CC |
484 | |
485 | spin_unlock_irqrestore(&clock_register_lock, flags); | |
486 | ||
d8611961 CC |
487 | return 0; |
488 | } | |
489 | ||
490 | static void tegra2_bus_clk_disable(struct clk *c) | |
491 | { | |
4729fd7a CC |
492 | u32 val; |
493 | unsigned long flags; | |
494 | ||
495 | spin_lock_irqsave(&clock_register_lock, flags); | |
496 | ||
497 | val = clk_readl(c->reg); | |
d8611961 CC |
498 | val |= BUS_CLK_DISABLE << c->reg_shift; |
499 | clk_writel(val, c->reg); | |
4729fd7a CC |
500 | |
501 | spin_unlock_irqrestore(&clock_register_lock, flags); | |
d8611961 CC |
502 | } |
503 | ||
504 | static int tegra2_bus_clk_set_rate(struct clk *c, unsigned long rate) | |
505 | { | |
4729fd7a CC |
506 | u32 val; |
507 | unsigned long parent_rate = clk_get_rate(c->parent); | |
508 | unsigned long flags; | |
509 | int ret = -EINVAL; | |
d8611961 | 510 | int i; |
4729fd7a CC |
511 | |
512 | spin_lock_irqsave(&clock_register_lock, flags); | |
513 | ||
514 | val = clk_readl(c->reg); | |
d8611961 CC |
515 | for (i = 1; i <= 4; i++) { |
516 | if (rate == parent_rate / i) { | |
517 | val &= ~(BUS_CLK_DIV_MASK << c->reg_shift); | |
518 | val |= (i - 1) << c->reg_shift; | |
519 | clk_writel(val, c->reg); | |
520 | c->div = i; | |
521 | c->mul = 1; | |
4729fd7a CC |
522 | ret = 0; |
523 | break; | |
d8611961 CC |
524 | } |
525 | } | |
4729fd7a CC |
526 | |
527 | spin_unlock_irqrestore(&clock_register_lock, flags); | |
528 | ||
529 | return ret; | |
d8611961 CC |
530 | } |
531 | ||
532 | static struct clk_ops tegra_bus_ops = { | |
533 | .init = tegra2_bus_clk_init, | |
534 | .enable = tegra2_bus_clk_enable, | |
535 | .disable = tegra2_bus_clk_disable, | |
536 | .set_rate = tegra2_bus_clk_set_rate, | |
d8611961 CC |
537 | }; |
538 | ||
cea62c87 CC |
539 | /* Blink output functions */ |
540 | ||
541 | static void tegra2_blink_clk_init(struct clk *c) | |
542 | { | |
543 | u32 val; | |
544 | ||
545 | val = pmc_readl(PMC_CTRL); | |
546 | c->state = (val & PMC_CTRL_BLINK_ENB) ? ON : OFF; | |
547 | c->mul = 1; | |
548 | val = pmc_readl(c->reg); | |
549 | ||
550 | if (val & PMC_BLINK_TIMER_ENB) { | |
551 | unsigned int on_off; | |
552 | ||
553 | on_off = (val >> PMC_BLINK_TIMER_DATA_ON_SHIFT) & | |
554 | PMC_BLINK_TIMER_DATA_ON_MASK; | |
555 | val >>= PMC_BLINK_TIMER_DATA_OFF_SHIFT; | |
556 | val &= PMC_BLINK_TIMER_DATA_OFF_MASK; | |
557 | on_off += val; | |
558 | /* each tick in the blink timer is 4 32KHz clocks */ | |
559 | c->div = on_off * 4; | |
560 | } else { | |
561 | c->div = 1; | |
562 | } | |
563 | } | |
564 | ||
565 | static int tegra2_blink_clk_enable(struct clk *c) | |
566 | { | |
567 | u32 val; | |
568 | ||
569 | val = pmc_readl(PMC_DPD_PADS_ORIDE); | |
570 | pmc_writel(val | PMC_DPD_PADS_ORIDE_BLINK_ENB, PMC_DPD_PADS_ORIDE); | |
571 | ||
572 | val = pmc_readl(PMC_CTRL); | |
573 | pmc_writel(val | PMC_CTRL_BLINK_ENB, PMC_CTRL); | |
574 | ||
575 | return 0; | |
576 | } | |
577 | ||
578 | static void tegra2_blink_clk_disable(struct clk *c) | |
579 | { | |
580 | u32 val; | |
581 | ||
582 | val = pmc_readl(PMC_CTRL); | |
583 | pmc_writel(val & ~PMC_CTRL_BLINK_ENB, PMC_CTRL); | |
584 | ||
585 | val = pmc_readl(PMC_DPD_PADS_ORIDE); | |
586 | pmc_writel(val & ~PMC_DPD_PADS_ORIDE_BLINK_ENB, PMC_DPD_PADS_ORIDE); | |
587 | } | |
588 | ||
589 | static int tegra2_blink_clk_set_rate(struct clk *c, unsigned long rate) | |
590 | { | |
4729fd7a CC |
591 | unsigned long parent_rate = clk_get_rate(c->parent); |
592 | if (rate >= parent_rate) { | |
cea62c87 CC |
593 | c->div = 1; |
594 | pmc_writel(0, c->reg); | |
595 | } else { | |
596 | unsigned int on_off; | |
597 | u32 val; | |
598 | ||
4729fd7a | 599 | on_off = DIV_ROUND_UP(parent_rate / 8, rate); |
cea62c87 CC |
600 | c->div = on_off * 8; |
601 | ||
602 | val = (on_off & PMC_BLINK_TIMER_DATA_ON_MASK) << | |
603 | PMC_BLINK_TIMER_DATA_ON_SHIFT; | |
604 | on_off &= PMC_BLINK_TIMER_DATA_OFF_MASK; | |
605 | on_off <<= PMC_BLINK_TIMER_DATA_OFF_SHIFT; | |
606 | val |= on_off; | |
607 | val |= PMC_BLINK_TIMER_ENB; | |
608 | pmc_writel(val, c->reg); | |
609 | } | |
610 | ||
611 | return 0; | |
612 | } | |
613 | ||
614 | static struct clk_ops tegra_blink_clk_ops = { | |
615 | .init = &tegra2_blink_clk_init, | |
616 | .enable = &tegra2_blink_clk_enable, | |
617 | .disable = &tegra2_blink_clk_disable, | |
618 | .set_rate = &tegra2_blink_clk_set_rate, | |
619 | }; | |
620 | ||
d8611961 | 621 | /* PLL Functions */ |
d8611961 CC |
622 | static int tegra2_pll_clk_wait_for_lock(struct clk *c) |
623 | { | |
f1519611 | 624 | udelay(c->u.pll.lock_delay); |
d8611961 CC |
625 | |
626 | return 0; | |
627 | } | |
628 | ||
629 | static void tegra2_pll_clk_init(struct clk *c) | |
630 | { | |
631 | u32 val = clk_readl(c->reg + PLL_BASE); | |
632 | ||
633 | c->state = (val & PLL_BASE_ENABLE) ? ON : OFF; | |
634 | ||
635 | if (c->flags & PLL_FIXED && !(val & PLL_BASE_OVERRIDE)) { | |
636 | pr_warning("Clock %s has unknown fixed frequency\n", c->name); | |
71fc84cc CC |
637 | c->mul = 1; |
638 | c->div = 1; | |
d8611961 | 639 | } else if (val & PLL_BASE_BYPASS) { |
71fc84cc CC |
640 | c->mul = 1; |
641 | c->div = 1; | |
d8611961 | 642 | } else { |
71fc84cc CC |
643 | c->mul = (val & PLL_BASE_DIVN_MASK) >> PLL_BASE_DIVN_SHIFT; |
644 | c->div = (val & PLL_BASE_DIVM_MASK) >> PLL_BASE_DIVM_SHIFT; | |
645 | if (c->flags & PLLU) | |
646 | c->div *= (val & PLLU_BASE_POST_DIV) ? 1 : 2; | |
647 | else | |
648 | c->div *= (val & PLL_BASE_DIVP_MASK) ? 2 : 1; | |
d8611961 | 649 | } |
d8611961 CC |
650 | } |
651 | ||
652 | static int tegra2_pll_clk_enable(struct clk *c) | |
653 | { | |
654 | u32 val; | |
655 | pr_debug("%s on clock %s\n", __func__, c->name); | |
656 | ||
657 | val = clk_readl(c->reg + PLL_BASE); | |
658 | val &= ~PLL_BASE_BYPASS; | |
659 | val |= PLL_BASE_ENABLE; | |
660 | clk_writel(val, c->reg + PLL_BASE); | |
661 | ||
d8611961 CC |
662 | tegra2_pll_clk_wait_for_lock(c); |
663 | ||
664 | return 0; | |
665 | } | |
666 | ||
667 | static void tegra2_pll_clk_disable(struct clk *c) | |
668 | { | |
669 | u32 val; | |
670 | pr_debug("%s on clock %s\n", __func__, c->name); | |
671 | ||
672 | val = clk_readl(c->reg); | |
673 | val &= ~(PLL_BASE_BYPASS | PLL_BASE_ENABLE); | |
674 | clk_writel(val, c->reg); | |
675 | } | |
676 | ||
677 | static int tegra2_pll_clk_set_rate(struct clk *c, unsigned long rate) | |
678 | { | |
679 | u32 val; | |
680 | unsigned long input_rate; | |
f1519611 | 681 | const struct clk_pll_freq_table *sel; |
d8611961 CC |
682 | |
683 | pr_debug("%s: %s %lu\n", __func__, c->name, rate); | |
d8611961 | 684 | |
4729fd7a | 685 | input_rate = clk_get_rate(c->parent); |
f1519611 | 686 | for (sel = c->u.pll.freq_table; sel->input_rate != 0; sel++) { |
d8611961 | 687 | if (sel->input_rate == input_rate && sel->output_rate == rate) { |
71fc84cc CC |
688 | c->mul = sel->n; |
689 | c->div = sel->m * sel->p; | |
d8611961 CC |
690 | |
691 | val = clk_readl(c->reg + PLL_BASE); | |
692 | if (c->flags & PLL_FIXED) | |
693 | val |= PLL_BASE_OVERRIDE; | |
694 | val &= ~(PLL_BASE_DIVP_MASK | PLL_BASE_DIVN_MASK | | |
695 | PLL_BASE_DIVM_MASK); | |
71fc84cc CC |
696 | val |= (sel->m << PLL_BASE_DIVM_SHIFT) | |
697 | (sel->n << PLL_BASE_DIVN_SHIFT); | |
698 | BUG_ON(sel->p < 1 || sel->p > 2); | |
699 | if (c->flags & PLLU) { | |
700 | if (sel->p == 1) | |
701 | val |= PLLU_BASE_POST_DIV; | |
702 | } else { | |
703 | if (sel->p == 2) | |
704 | val |= 1 << PLL_BASE_DIVP_SHIFT; | |
705 | } | |
d8611961 CC |
706 | clk_writel(val, c->reg + PLL_BASE); |
707 | ||
708 | if (c->flags & PLL_HAS_CPCON) { | |
71fc84cc CC |
709 | val = clk_readl(c->reg + PLL_MISC(c)); |
710 | val &= ~PLL_MISC_CPCON_MASK; | |
711 | val |= sel->cpcon << PLL_MISC_CPCON_SHIFT; | |
d8611961 CC |
712 | clk_writel(val, c->reg + PLL_MISC(c)); |
713 | } | |
714 | ||
715 | if (c->state == ON) | |
716 | tegra2_pll_clk_enable(c); | |
717 | ||
d8611961 CC |
718 | return 0; |
719 | } | |
720 | } | |
721 | return -EINVAL; | |
722 | } | |
723 | ||
724 | static struct clk_ops tegra_pll_ops = { | |
725 | .init = tegra2_pll_clk_init, | |
726 | .enable = tegra2_pll_clk_enable, | |
727 | .disable = tegra2_pll_clk_disable, | |
728 | .set_rate = tegra2_pll_clk_set_rate, | |
71fc84cc CC |
729 | }; |
730 | ||
731 | static void tegra2_pllx_clk_init(struct clk *c) | |
732 | { | |
733 | tegra2_pll_clk_init(c); | |
734 | ||
735 | if (tegra_sku_id() == 7) | |
736 | c->max_rate = 750000000; | |
737 | } | |
738 | ||
739 | static struct clk_ops tegra_pllx_ops = { | |
740 | .init = tegra2_pllx_clk_init, | |
741 | .enable = tegra2_pll_clk_enable, | |
742 | .disable = tegra2_pll_clk_disable, | |
743 | .set_rate = tegra2_pll_clk_set_rate, | |
d8611961 CC |
744 | }; |
745 | ||
8d685bc5 MR |
746 | static int tegra2_plle_clk_enable(struct clk *c) |
747 | { | |
748 | u32 val; | |
749 | ||
750 | pr_debug("%s on clock %s\n", __func__, c->name); | |
751 | ||
752 | mdelay(1); | |
753 | ||
754 | val = clk_readl(c->reg + PLL_BASE); | |
755 | if (!(val & PLLE_MISC_READY)) | |
756 | return -EBUSY; | |
757 | ||
758 | val = clk_readl(c->reg + PLL_BASE); | |
759 | val |= PLL_BASE_ENABLE | PLL_BASE_BYPASS; | |
760 | clk_writel(val, c->reg + PLL_BASE); | |
761 | ||
762 | return 0; | |
763 | } | |
764 | ||
765 | static struct clk_ops tegra_plle_ops = { | |
766 | .init = tegra2_pll_clk_init, | |
767 | .enable = tegra2_plle_clk_enable, | |
768 | .set_rate = tegra2_pll_clk_set_rate, | |
769 | }; | |
770 | ||
d8611961 CC |
771 | /* Clock divider ops */ |
772 | static void tegra2_pll_div_clk_init(struct clk *c) | |
773 | { | |
774 | u32 val = clk_readl(c->reg); | |
775 | u32 divu71; | |
776 | val >>= c->reg_shift; | |
777 | c->state = (val & PLL_OUT_CLKEN) ? ON : OFF; | |
778 | if (!(val & PLL_OUT_RESET_DISABLE)) | |
779 | c->state = OFF; | |
780 | ||
781 | if (c->flags & DIV_U71) { | |
782 | divu71 = (val & PLL_OUT_RATIO_MASK) >> PLL_OUT_RATIO_SHIFT; | |
783 | c->div = (divu71 + 2); | |
784 | c->mul = 2; | |
785 | } else if (c->flags & DIV_2) { | |
786 | c->div = 2; | |
787 | c->mul = 1; | |
788 | } else { | |
789 | c->div = 1; | |
790 | c->mul = 1; | |
791 | } | |
d8611961 CC |
792 | } |
793 | ||
794 | static int tegra2_pll_div_clk_enable(struct clk *c) | |
795 | { | |
796 | u32 val; | |
797 | u32 new_val; | |
4729fd7a | 798 | unsigned long flags; |
d8611961 CC |
799 | |
800 | pr_debug("%s: %s\n", __func__, c->name); | |
801 | if (c->flags & DIV_U71) { | |
4729fd7a | 802 | spin_lock_irqsave(&clock_register_lock, flags); |
d8611961 CC |
803 | val = clk_readl(c->reg); |
804 | new_val = val >> c->reg_shift; | |
805 | new_val &= 0xFFFF; | |
806 | ||
807 | new_val |= PLL_OUT_CLKEN | PLL_OUT_RESET_DISABLE; | |
808 | ||
809 | val &= ~(0xFFFF << c->reg_shift); | |
810 | val |= new_val << c->reg_shift; | |
811 | clk_writel(val, c->reg); | |
4729fd7a | 812 | spin_unlock_irqrestore(&clock_register_lock, flags); |
d8611961 CC |
813 | return 0; |
814 | } else if (c->flags & DIV_2) { | |
815 | BUG_ON(!(c->flags & PLLD)); | |
4729fd7a | 816 | spin_lock_irqsave(&clock_register_lock, flags); |
d8611961 CC |
817 | val = clk_readl(c->reg); |
818 | val &= ~PLLD_MISC_DIV_RST; | |
819 | clk_writel(val, c->reg); | |
4729fd7a | 820 | spin_unlock_irqrestore(&clock_register_lock, flags); |
d8611961 CC |
821 | return 0; |
822 | } | |
823 | return -EINVAL; | |
824 | } | |
825 | ||
826 | static void tegra2_pll_div_clk_disable(struct clk *c) | |
827 | { | |
828 | u32 val; | |
829 | u32 new_val; | |
4729fd7a | 830 | unsigned long flags; |
d8611961 CC |
831 | |
832 | pr_debug("%s: %s\n", __func__, c->name); | |
833 | if (c->flags & DIV_U71) { | |
4729fd7a | 834 | spin_lock_irqsave(&clock_register_lock, flags); |
d8611961 CC |
835 | val = clk_readl(c->reg); |
836 | new_val = val >> c->reg_shift; | |
837 | new_val &= 0xFFFF; | |
838 | ||
839 | new_val &= ~(PLL_OUT_CLKEN | PLL_OUT_RESET_DISABLE); | |
840 | ||
841 | val &= ~(0xFFFF << c->reg_shift); | |
842 | val |= new_val << c->reg_shift; | |
843 | clk_writel(val, c->reg); | |
4729fd7a | 844 | spin_unlock_irqrestore(&clock_register_lock, flags); |
d8611961 CC |
845 | } else if (c->flags & DIV_2) { |
846 | BUG_ON(!(c->flags & PLLD)); | |
4729fd7a | 847 | spin_lock_irqsave(&clock_register_lock, flags); |
d8611961 CC |
848 | val = clk_readl(c->reg); |
849 | val |= PLLD_MISC_DIV_RST; | |
850 | clk_writel(val, c->reg); | |
4729fd7a | 851 | spin_unlock_irqrestore(&clock_register_lock, flags); |
d8611961 CC |
852 | } |
853 | } | |
854 | ||
855 | static int tegra2_pll_div_clk_set_rate(struct clk *c, unsigned long rate) | |
856 | { | |
857 | u32 val; | |
858 | u32 new_val; | |
859 | int divider_u71; | |
4729fd7a CC |
860 | unsigned long parent_rate = clk_get_rate(c->parent); |
861 | unsigned long flags; | |
862 | ||
d8611961 CC |
863 | pr_debug("%s: %s %lu\n", __func__, c->name, rate); |
864 | if (c->flags & DIV_U71) { | |
4729fd7a | 865 | divider_u71 = clk_div71_get_divider(parent_rate, rate); |
d8611961 | 866 | if (divider_u71 >= 0) { |
4729fd7a | 867 | spin_lock_irqsave(&clock_register_lock, flags); |
d8611961 CC |
868 | val = clk_readl(c->reg); |
869 | new_val = val >> c->reg_shift; | |
870 | new_val &= 0xFFFF; | |
871 | if (c->flags & DIV_U71_FIXED) | |
872 | new_val |= PLL_OUT_OVERRIDE; | |
873 | new_val &= ~PLL_OUT_RATIO_MASK; | |
874 | new_val |= divider_u71 << PLL_OUT_RATIO_SHIFT; | |
875 | ||
876 | val &= ~(0xFFFF << c->reg_shift); | |
877 | val |= new_val << c->reg_shift; | |
878 | clk_writel(val, c->reg); | |
879 | c->div = divider_u71 + 2; | |
880 | c->mul = 2; | |
4729fd7a | 881 | spin_unlock_irqrestore(&clock_register_lock, flags); |
d8611961 CC |
882 | return 0; |
883 | } | |
884 | } else if (c->flags & DIV_2) { | |
4729fd7a | 885 | if (parent_rate == rate * 2) |
d8611961 | 886 | return 0; |
d8611961 CC |
887 | } |
888 | return -EINVAL; | |
889 | } | |
890 | ||
71fc84cc CC |
891 | static long tegra2_pll_div_clk_round_rate(struct clk *c, unsigned long rate) |
892 | { | |
893 | int divider; | |
4729fd7a | 894 | unsigned long parent_rate = clk_get_rate(c->parent); |
71fc84cc CC |
895 | pr_debug("%s: %s %lu\n", __func__, c->name, rate); |
896 | ||
897 | if (c->flags & DIV_U71) { | |
4729fd7a | 898 | divider = clk_div71_get_divider(parent_rate, rate); |
71fc84cc CC |
899 | if (divider < 0) |
900 | return divider; | |
421186e7 | 901 | return DIV_ROUND_UP(parent_rate * 2, divider + 2); |
71fc84cc | 902 | } else if (c->flags & DIV_2) { |
421186e7 | 903 | return DIV_ROUND_UP(parent_rate, 2); |
71fc84cc CC |
904 | } |
905 | return -EINVAL; | |
906 | } | |
d8611961 CC |
907 | |
908 | static struct clk_ops tegra_pll_div_ops = { | |
909 | .init = tegra2_pll_div_clk_init, | |
910 | .enable = tegra2_pll_div_clk_enable, | |
911 | .disable = tegra2_pll_div_clk_disable, | |
912 | .set_rate = tegra2_pll_div_clk_set_rate, | |
71fc84cc | 913 | .round_rate = tegra2_pll_div_clk_round_rate, |
d8611961 CC |
914 | }; |
915 | ||
916 | /* Periph clk ops */ | |
917 | ||
918 | static void tegra2_periph_clk_init(struct clk *c) | |
919 | { | |
920 | u32 val = clk_readl(c->reg); | |
921 | const struct clk_mux_sel *mux = 0; | |
922 | const struct clk_mux_sel *sel; | |
923 | if (c->flags & MUX) { | |
924 | for (sel = c->inputs; sel->input != NULL; sel++) { | |
925 | if (val >> PERIPH_CLK_SOURCE_SHIFT == sel->value) | |
926 | mux = sel; | |
927 | } | |
928 | BUG_ON(!mux); | |
929 | ||
930 | c->parent = mux->input; | |
931 | } else { | |
932 | c->parent = c->inputs[0].input; | |
933 | } | |
934 | ||
935 | if (c->flags & DIV_U71) { | |
71fc84cc | 936 | u32 divu71 = val & PERIPH_CLK_SOURCE_DIVU71_MASK; |
d8611961 CC |
937 | c->div = divu71 + 2; |
938 | c->mul = 2; | |
71fc84cc CC |
939 | } else if (c->flags & DIV_U16) { |
940 | u32 divu16 = val & PERIPH_CLK_SOURCE_DIVU16_MASK; | |
941 | c->div = divu16 + 1; | |
942 | c->mul = 1; | |
d8611961 CC |
943 | } else { |
944 | c->div = 1; | |
945 | c->mul = 1; | |
946 | } | |
947 | ||
948 | c->state = ON; | |
1be3d053 CC |
949 | |
950 | if (!c->u.periph.clk_num) | |
951 | return; | |
952 | ||
d8611961 CC |
953 | if (!(clk_readl(CLK_OUT_ENB + PERIPH_CLK_TO_ENB_REG(c)) & |
954 | PERIPH_CLK_TO_ENB_BIT(c))) | |
955 | c->state = OFF; | |
1be3d053 | 956 | |
d8611961 CC |
957 | if (!(c->flags & PERIPH_NO_RESET)) |
958 | if (clk_readl(RST_DEVICES + PERIPH_CLK_TO_ENB_REG(c)) & | |
959 | PERIPH_CLK_TO_ENB_BIT(c)) | |
960 | c->state = OFF; | |
d8611961 CC |
961 | } |
962 | ||
963 | static int tegra2_periph_clk_enable(struct clk *c) | |
964 | { | |
965 | u32 val; | |
78f379b5 CC |
966 | unsigned long flags; |
967 | int refcount; | |
d8611961 CC |
968 | pr_debug("%s on clock %s\n", __func__, c->name); |
969 | ||
1be3d053 CC |
970 | if (!c->u.periph.clk_num) |
971 | return 0; | |
972 | ||
78f379b5 CC |
973 | spin_lock_irqsave(&clock_register_lock, flags); |
974 | ||
975 | refcount = tegra_periph_clk_enable_refcount[c->u.periph.clk_num]++; | |
976 | ||
977 | if (refcount > 1) | |
978 | goto out; | |
979 | ||
d8611961 CC |
980 | clk_writel(PERIPH_CLK_TO_ENB_BIT(c), |
981 | CLK_OUT_ENB_SET + PERIPH_CLK_TO_ENB_SET_REG(c)); | |
982 | if (!(c->flags & PERIPH_NO_RESET) && !(c->flags & PERIPH_MANUAL_RESET)) | |
983 | clk_writel(PERIPH_CLK_TO_ENB_BIT(c), | |
984 | RST_DEVICES_CLR + PERIPH_CLK_TO_ENB_SET_REG(c)); | |
985 | if (c->flags & PERIPH_EMC_ENB) { | |
986 | /* The EMC peripheral clock has 2 extra enable bits */ | |
987 | /* FIXME: Do they need to be disabled? */ | |
988 | val = clk_readl(c->reg); | |
989 | val |= 0x3 << 24; | |
990 | clk_writel(val, c->reg); | |
991 | } | |
78f379b5 CC |
992 | |
993 | out: | |
994 | spin_unlock_irqrestore(&clock_register_lock, flags); | |
995 | ||
d8611961 CC |
996 | return 0; |
997 | } | |
998 | ||
999 | static void tegra2_periph_clk_disable(struct clk *c) | |
1000 | { | |
78f379b5 CC |
1001 | unsigned long flags; |
1002 | ||
d8611961 CC |
1003 | pr_debug("%s on clock %s\n", __func__, c->name); |
1004 | ||
1be3d053 CC |
1005 | if (!c->u.periph.clk_num) |
1006 | return; | |
1007 | ||
78f379b5 CC |
1008 | spin_lock_irqsave(&clock_register_lock, flags); |
1009 | ||
1010 | if (c->refcnt) | |
1011 | tegra_periph_clk_enable_refcount[c->u.periph.clk_num]--; | |
1012 | ||
1013 | if (tegra_periph_clk_enable_refcount[c->u.periph.clk_num] == 0) | |
1014 | clk_writel(PERIPH_CLK_TO_ENB_BIT(c), | |
1015 | CLK_OUT_ENB_CLR + PERIPH_CLK_TO_ENB_SET_REG(c)); | |
1016 | ||
1017 | spin_unlock_irqrestore(&clock_register_lock, flags); | |
d8611961 CC |
1018 | } |
1019 | ||
2b84cb4f | 1020 | static void tegra2_periph_clk_reset(struct clk *c, bool assert) |
d8611961 | 1021 | { |
2b84cb4f | 1022 | unsigned long base = assert ? RST_DEVICES_SET : RST_DEVICES_CLR; |
d8611961 | 1023 | |
2b84cb4f DZ |
1024 | pr_debug("%s %s on clock %s\n", __func__, |
1025 | assert ? "assert" : "deassert", c->name); | |
1be3d053 CC |
1026 | |
1027 | BUG_ON(!c->u.periph.clk_num); | |
1028 | ||
d8611961 CC |
1029 | if (!(c->flags & PERIPH_NO_RESET)) |
1030 | clk_writel(PERIPH_CLK_TO_ENB_BIT(c), | |
2b84cb4f | 1031 | base + PERIPH_CLK_TO_ENB_SET_REG(c)); |
d8611961 CC |
1032 | } |
1033 | ||
d8611961 CC |
1034 | static int tegra2_periph_clk_set_parent(struct clk *c, struct clk *p) |
1035 | { | |
1036 | u32 val; | |
1037 | const struct clk_mux_sel *sel; | |
1038 | pr_debug("%s: %s %s\n", __func__, c->name, p->name); | |
1039 | for (sel = c->inputs; sel->input != NULL; sel++) { | |
1040 | if (sel->input == p) { | |
d8611961 CC |
1041 | val = clk_readl(c->reg); |
1042 | val &= ~PERIPH_CLK_SOURCE_MASK; | |
1043 | val |= (sel->value) << PERIPH_CLK_SOURCE_SHIFT; | |
71fc84cc CC |
1044 | |
1045 | if (c->refcnt) | |
4729fd7a | 1046 | clk_enable(p); |
71fc84cc | 1047 | |
d8611961 | 1048 | clk_writel(val, c->reg); |
71fc84cc CC |
1049 | |
1050 | if (c->refcnt && c->parent) | |
4729fd7a | 1051 | clk_disable(c->parent); |
71fc84cc CC |
1052 | |
1053 | clk_reparent(c, p); | |
d8611961 CC |
1054 | return 0; |
1055 | } | |
1056 | } | |
1057 | ||
1058 | return -EINVAL; | |
1059 | } | |
1060 | ||
1061 | static int tegra2_periph_clk_set_rate(struct clk *c, unsigned long rate) | |
1062 | { | |
1063 | u32 val; | |
71fc84cc | 1064 | int divider; |
4729fd7a CC |
1065 | unsigned long parent_rate = clk_get_rate(c->parent); |
1066 | ||
d8611961 | 1067 | if (c->flags & DIV_U71) { |
4729fd7a | 1068 | divider = clk_div71_get_divider(parent_rate, rate); |
71fc84cc | 1069 | if (divider >= 0) { |
d8611961 | 1070 | val = clk_readl(c->reg); |
71fc84cc CC |
1071 | val &= ~PERIPH_CLK_SOURCE_DIVU71_MASK; |
1072 | val |= divider; | |
d8611961 | 1073 | clk_writel(val, c->reg); |
71fc84cc | 1074 | c->div = divider + 2; |
d8611961 | 1075 | c->mul = 2; |
d8611961 CC |
1076 | return 0; |
1077 | } | |
71fc84cc | 1078 | } else if (c->flags & DIV_U16) { |
4729fd7a | 1079 | divider = clk_div16_get_divider(parent_rate, rate); |
71fc84cc CC |
1080 | if (divider >= 0) { |
1081 | val = clk_readl(c->reg); | |
1082 | val &= ~PERIPH_CLK_SOURCE_DIVU16_MASK; | |
1083 | val |= divider; | |
1084 | clk_writel(val, c->reg); | |
1085 | c->div = divider + 1; | |
1086 | c->mul = 1; | |
1087 | return 0; | |
1088 | } | |
4729fd7a | 1089 | } else if (parent_rate <= rate) { |
71fc84cc CC |
1090 | c->div = 1; |
1091 | c->mul = 1; | |
1092 | return 0; | |
1093 | } | |
1094 | return -EINVAL; | |
1095 | } | |
1096 | ||
1097 | static long tegra2_periph_clk_round_rate(struct clk *c, | |
1098 | unsigned long rate) | |
1099 | { | |
1100 | int divider; | |
4729fd7a | 1101 | unsigned long parent_rate = clk_get_rate(c->parent); |
71fc84cc CC |
1102 | pr_debug("%s: %s %lu\n", __func__, c->name, rate); |
1103 | ||
1104 | if (c->flags & DIV_U71) { | |
4729fd7a | 1105 | divider = clk_div71_get_divider(parent_rate, rate); |
71fc84cc CC |
1106 | if (divider < 0) |
1107 | return divider; | |
1108 | ||
421186e7 | 1109 | return DIV_ROUND_UP(parent_rate * 2, divider + 2); |
71fc84cc | 1110 | } else if (c->flags & DIV_U16) { |
4729fd7a | 1111 | divider = clk_div16_get_divider(parent_rate, rate); |
71fc84cc CC |
1112 | if (divider < 0) |
1113 | return divider; | |
421186e7 | 1114 | return DIV_ROUND_UP(parent_rate, divider + 1); |
d8611961 CC |
1115 | } |
1116 | return -EINVAL; | |
1117 | } | |
1118 | ||
1119 | static struct clk_ops tegra_periph_clk_ops = { | |
1120 | .init = &tegra2_periph_clk_init, | |
1121 | .enable = &tegra2_periph_clk_enable, | |
1122 | .disable = &tegra2_periph_clk_disable, | |
1123 | .set_parent = &tegra2_periph_clk_set_parent, | |
1124 | .set_rate = &tegra2_periph_clk_set_rate, | |
71fc84cc | 1125 | .round_rate = &tegra2_periph_clk_round_rate, |
2b84cb4f | 1126 | .reset = &tegra2_periph_clk_reset, |
d8611961 CC |
1127 | }; |
1128 | ||
9743b389 CC |
1129 | /* The SDMMC controllers have extra bits in the clock source register that |
1130 | * adjust the delay between the clock and data to compenstate for delays | |
1131 | * on the PCB. */ | |
1132 | void tegra2_sdmmc_tap_delay(struct clk *c, int delay) | |
1133 | { | |
1134 | u32 reg; | |
1135 | ||
1136 | delay = clamp(delay, 0, 15); | |
1137 | reg = clk_readl(c->reg); | |
1138 | reg &= ~SDMMC_CLK_INT_FB_DLY_MASK; | |
1139 | reg |= SDMMC_CLK_INT_FB_SEL; | |
1140 | reg |= delay << SDMMC_CLK_INT_FB_DLY_SHIFT; | |
1141 | clk_writel(reg, c->reg); | |
1142 | } | |
1143 | ||
6d296828 CC |
1144 | /* External memory controller clock ops */ |
1145 | static void tegra2_emc_clk_init(struct clk *c) | |
1146 | { | |
1147 | tegra2_periph_clk_init(c); | |
1148 | c->max_rate = clk_get_rate_locked(c); | |
1149 | } | |
1150 | ||
1151 | static long tegra2_emc_clk_round_rate(struct clk *c, unsigned long rate) | |
1152 | { | |
1153 | long new_rate = rate; | |
1154 | ||
1155 | new_rate = tegra_emc_round_rate(new_rate); | |
1156 | if (new_rate < 0) | |
1157 | return c->max_rate; | |
1158 | ||
1159 | BUG_ON(new_rate != tegra2_periph_clk_round_rate(c, new_rate)); | |
1160 | ||
1161 | return new_rate; | |
1162 | } | |
1163 | ||
1164 | static int tegra2_emc_clk_set_rate(struct clk *c, unsigned long rate) | |
1165 | { | |
1166 | int ret; | |
1167 | /* | |
1168 | * The Tegra2 memory controller has an interlock with the clock | |
1169 | * block that allows memory shadowed registers to be updated, | |
1170 | * and then transfer them to the main registers at the same | |
1171 | * time as the clock update without glitches. | |
1172 | */ | |
1173 | ret = tegra_emc_set_rate(rate); | |
1174 | if (ret < 0) | |
1175 | return ret; | |
1176 | ||
1177 | ret = tegra2_periph_clk_set_rate(c, rate); | |
1178 | udelay(1); | |
1179 | ||
1180 | return ret; | |
1181 | } | |
1182 | ||
1183 | static struct clk_ops tegra_emc_clk_ops = { | |
1184 | .init = &tegra2_emc_clk_init, | |
1185 | .enable = &tegra2_periph_clk_enable, | |
1186 | .disable = &tegra2_periph_clk_disable, | |
1187 | .set_parent = &tegra2_periph_clk_set_parent, | |
1188 | .set_rate = &tegra2_emc_clk_set_rate, | |
1189 | .round_rate = &tegra2_emc_clk_round_rate, | |
1190 | .reset = &tegra2_periph_clk_reset, | |
1191 | }; | |
1192 | ||
d8611961 CC |
1193 | /* Clock doubler ops */ |
1194 | static void tegra2_clk_double_init(struct clk *c) | |
1195 | { | |
1196 | c->mul = 2; | |
1197 | c->div = 1; | |
1198 | c->state = ON; | |
1be3d053 CC |
1199 | |
1200 | if (!c->u.periph.clk_num) | |
1201 | return; | |
1202 | ||
d8611961 CC |
1203 | if (!(clk_readl(CLK_OUT_ENB + PERIPH_CLK_TO_ENB_REG(c)) & |
1204 | PERIPH_CLK_TO_ENB_BIT(c))) | |
1205 | c->state = OFF; | |
d8611961 CC |
1206 | }; |
1207 | ||
71fc84cc CC |
1208 | static int tegra2_clk_double_set_rate(struct clk *c, unsigned long rate) |
1209 | { | |
4729fd7a | 1210 | if (rate != 2 * clk_get_rate(c->parent)) |
71fc84cc CC |
1211 | return -EINVAL; |
1212 | c->mul = 2; | |
1213 | c->div = 1; | |
1214 | return 0; | |
1215 | } | |
1216 | ||
d8611961 CC |
1217 | static struct clk_ops tegra_clk_double_ops = { |
1218 | .init = &tegra2_clk_double_init, | |
1219 | .enable = &tegra2_periph_clk_enable, | |
1220 | .disable = &tegra2_periph_clk_disable, | |
71fc84cc CC |
1221 | .set_rate = &tegra2_clk_double_set_rate, |
1222 | }; | |
1223 | ||
cea62c87 | 1224 | /* Audio sync clock ops */ |
71fc84cc CC |
1225 | static void tegra2_audio_sync_clk_init(struct clk *c) |
1226 | { | |
1227 | int source; | |
1228 | const struct clk_mux_sel *sel; | |
1229 | u32 val = clk_readl(c->reg); | |
1230 | c->state = (val & (1<<4)) ? OFF : ON; | |
1231 | source = val & 0xf; | |
1232 | for (sel = c->inputs; sel->input != NULL; sel++) | |
1233 | if (sel->value == source) | |
1234 | break; | |
1235 | BUG_ON(sel->input == NULL); | |
1236 | c->parent = sel->input; | |
1237 | } | |
1238 | ||
1239 | static int tegra2_audio_sync_clk_enable(struct clk *c) | |
1240 | { | |
1241 | clk_writel(0, c->reg); | |
1242 | return 0; | |
1243 | } | |
1244 | ||
1245 | static void tegra2_audio_sync_clk_disable(struct clk *c) | |
1246 | { | |
1247 | clk_writel(1, c->reg); | |
1248 | } | |
1249 | ||
1250 | static int tegra2_audio_sync_clk_set_parent(struct clk *c, struct clk *p) | |
1251 | { | |
1252 | u32 val; | |
1253 | const struct clk_mux_sel *sel; | |
1254 | for (sel = c->inputs; sel->input != NULL; sel++) { | |
1255 | if (sel->input == p) { | |
1256 | val = clk_readl(c->reg); | |
1257 | val &= ~0xf; | |
1258 | val |= sel->value; | |
1259 | ||
1260 | if (c->refcnt) | |
4729fd7a | 1261 | clk_enable(p); |
71fc84cc CC |
1262 | |
1263 | clk_writel(val, c->reg); | |
1264 | ||
1265 | if (c->refcnt && c->parent) | |
4729fd7a | 1266 | clk_disable(c->parent); |
71fc84cc CC |
1267 | |
1268 | clk_reparent(c, p); | |
1269 | return 0; | |
1270 | } | |
1271 | } | |
1272 | ||
1273 | return -EINVAL; | |
1274 | } | |
1275 | ||
71fc84cc CC |
1276 | static struct clk_ops tegra_audio_sync_clk_ops = { |
1277 | .init = tegra2_audio_sync_clk_init, | |
1278 | .enable = tegra2_audio_sync_clk_enable, | |
1279 | .disable = tegra2_audio_sync_clk_disable, | |
71fc84cc | 1280 | .set_parent = tegra2_audio_sync_clk_set_parent, |
d8611961 CC |
1281 | }; |
1282 | ||
cea62c87 CC |
1283 | /* cdev1 and cdev2 (dap_mclk1 and dap_mclk2) ops */ |
1284 | ||
1285 | static void tegra2_cdev_clk_init(struct clk *c) | |
1286 | { | |
1287 | /* We could un-tristate the cdev1 or cdev2 pingroup here; this is | |
1288 | * currently done in the pinmux code. */ | |
1289 | c->state = ON; | |
1be3d053 CC |
1290 | |
1291 | BUG_ON(!c->u.periph.clk_num); | |
1292 | ||
cea62c87 CC |
1293 | if (!(clk_readl(CLK_OUT_ENB + PERIPH_CLK_TO_ENB_REG(c)) & |
1294 | PERIPH_CLK_TO_ENB_BIT(c))) | |
1295 | c->state = OFF; | |
1296 | } | |
1297 | ||
1298 | static int tegra2_cdev_clk_enable(struct clk *c) | |
1299 | { | |
1be3d053 CC |
1300 | BUG_ON(!c->u.periph.clk_num); |
1301 | ||
cea62c87 CC |
1302 | clk_writel(PERIPH_CLK_TO_ENB_BIT(c), |
1303 | CLK_OUT_ENB_SET + PERIPH_CLK_TO_ENB_SET_REG(c)); | |
1304 | return 0; | |
1305 | } | |
1306 | ||
1307 | static void tegra2_cdev_clk_disable(struct clk *c) | |
1308 | { | |
1be3d053 CC |
1309 | BUG_ON(!c->u.periph.clk_num); |
1310 | ||
cea62c87 CC |
1311 | clk_writel(PERIPH_CLK_TO_ENB_BIT(c), |
1312 | CLK_OUT_ENB_CLR + PERIPH_CLK_TO_ENB_SET_REG(c)); | |
1313 | } | |
1314 | ||
1315 | static struct clk_ops tegra_cdev_clk_ops = { | |
1316 | .init = &tegra2_cdev_clk_init, | |
1317 | .enable = &tegra2_cdev_clk_enable, | |
1318 | .disable = &tegra2_cdev_clk_disable, | |
1319 | }; | |
1320 | ||
310992ca CC |
1321 | /* shared bus ops */ |
1322 | /* | |
1323 | * Some clocks may have multiple downstream users that need to request a | |
1324 | * higher clock rate. Shared bus clocks provide a unique shared_bus_user | |
1325 | * clock to each user. The frequency of the bus is set to the highest | |
1326 | * enabled shared_bus_user clock, with a minimum value set by the | |
1327 | * shared bus. | |
1328 | */ | |
1329 | static int tegra_clk_shared_bus_update(struct clk *bus) | |
1330 | { | |
1331 | struct clk *c; | |
1332 | unsigned long rate = bus->min_rate; | |
1333 | ||
1334 | list_for_each_entry(c, &bus->shared_bus_list, u.shared_bus_user.node) | |
1335 | if (c->u.shared_bus_user.enabled) | |
1336 | rate = max(c->u.shared_bus_user.rate, rate); | |
1337 | ||
1338 | if (rate == clk_get_rate_locked(bus)) | |
1339 | return 0; | |
1340 | ||
1341 | return clk_set_rate_locked(bus, rate); | |
1342 | }; | |
1343 | ||
1344 | static void tegra_clk_shared_bus_init(struct clk *c) | |
1345 | { | |
1346 | unsigned long flags; | |
1347 | ||
1348 | c->max_rate = c->parent->max_rate; | |
1349 | c->u.shared_bus_user.rate = c->parent->max_rate; | |
1350 | c->state = OFF; | |
310992ca | 1351 | c->set = true; |
310992ca CC |
1352 | |
1353 | spin_lock_irqsave(&c->parent->spinlock, flags); | |
1354 | ||
1355 | list_add_tail(&c->u.shared_bus_user.node, | |
1356 | &c->parent->shared_bus_list); | |
1357 | ||
1358 | spin_unlock_irqrestore(&c->parent->spinlock, flags); | |
1359 | } | |
1360 | ||
1361 | static int tegra_clk_shared_bus_set_rate(struct clk *c, unsigned long rate) | |
1362 | { | |
1363 | unsigned long flags; | |
1364 | int ret; | |
1365 | ||
1366 | rate = clk_round_rate(c->parent, rate); | |
1367 | if (rate < 0) | |
1368 | return rate; | |
1369 | ||
1370 | spin_lock_irqsave(&c->parent->spinlock, flags); | |
1371 | ||
1372 | c->u.shared_bus_user.rate = rate; | |
1373 | ret = tegra_clk_shared_bus_update(c->parent); | |
1374 | ||
1375 | spin_unlock_irqrestore(&c->parent->spinlock, flags); | |
1376 | ||
1377 | return ret; | |
1378 | } | |
1379 | ||
1380 | static long tegra_clk_shared_bus_round_rate(struct clk *c, unsigned long rate) | |
1381 | { | |
1382 | return clk_round_rate(c->parent, rate); | |
1383 | } | |
1384 | ||
1385 | static int tegra_clk_shared_bus_enable(struct clk *c) | |
1386 | { | |
1387 | unsigned long flags; | |
1388 | int ret; | |
1389 | ||
1390 | spin_lock_irqsave(&c->parent->spinlock, flags); | |
1391 | ||
1392 | c->u.shared_bus_user.enabled = true; | |
1393 | ret = tegra_clk_shared_bus_update(c->parent); | |
1394 | ||
1395 | spin_unlock_irqrestore(&c->parent->spinlock, flags); | |
1396 | ||
1397 | return ret; | |
1398 | } | |
1399 | ||
1400 | static void tegra_clk_shared_bus_disable(struct clk *c) | |
1401 | { | |
1402 | unsigned long flags; | |
1403 | int ret; | |
1404 | ||
1405 | spin_lock_irqsave(&c->parent->spinlock, flags); | |
1406 | ||
1407 | c->u.shared_bus_user.enabled = false; | |
1408 | ret = tegra_clk_shared_bus_update(c->parent); | |
1409 | WARN_ON_ONCE(ret); | |
1410 | ||
1411 | spin_unlock_irqrestore(&c->parent->spinlock, flags); | |
1412 | } | |
1413 | ||
1414 | static struct clk_ops tegra_clk_shared_bus_ops = { | |
1415 | .init = tegra_clk_shared_bus_init, | |
1416 | .enable = tegra_clk_shared_bus_enable, | |
1417 | .disable = tegra_clk_shared_bus_disable, | |
1418 | .set_rate = tegra_clk_shared_bus_set_rate, | |
1419 | .round_rate = tegra_clk_shared_bus_round_rate, | |
1420 | }; | |
1421 | ||
1422 | ||
d8611961 CC |
1423 | /* Clock definitions */ |
1424 | static struct clk tegra_clk_32k = { | |
1425 | .name = "clk_32k", | |
71fc84cc | 1426 | .rate = 32768, |
d8611961 | 1427 | .ops = NULL, |
71fc84cc | 1428 | .max_rate = 32768, |
d8611961 CC |
1429 | }; |
1430 | ||
f1519611 | 1431 | static struct clk_pll_freq_table tegra_pll_s_freq_table[] = { |
d8611961 CC |
1432 | {32768, 12000000, 366, 1, 1, 0}, |
1433 | {32768, 13000000, 397, 1, 1, 0}, | |
1434 | {32768, 19200000, 586, 1, 1, 0}, | |
1435 | {32768, 26000000, 793, 1, 1, 0}, | |
1436 | {0, 0, 0, 0, 0, 0}, | |
1437 | }; | |
1438 | ||
1439 | static struct clk tegra_pll_s = { | |
1440 | .name = "pll_s", | |
1441 | .flags = PLL_ALT_MISC_REG, | |
1442 | .ops = &tegra_pll_ops, | |
d8611961 | 1443 | .parent = &tegra_clk_32k, |
71fc84cc | 1444 | .max_rate = 26000000, |
f1519611 CC |
1445 | .reg = 0xf0, |
1446 | .u.pll = { | |
1447 | .input_min = 32768, | |
1448 | .input_max = 32768, | |
1449 | .cf_min = 0, /* FIXME */ | |
1450 | .cf_max = 0, /* FIXME */ | |
1451 | .vco_min = 12000000, | |
1452 | .vco_max = 26000000, | |
1453 | .freq_table = tegra_pll_s_freq_table, | |
1454 | .lock_delay = 300, | |
1455 | }, | |
d8611961 CC |
1456 | }; |
1457 | ||
1458 | static struct clk_mux_sel tegra_clk_m_sel[] = { | |
1459 | { .input = &tegra_clk_32k, .value = 0}, | |
1460 | { .input = &tegra_pll_s, .value = 1}, | |
1461 | { 0, 0}, | |
1462 | }; | |
f1519611 | 1463 | |
d8611961 CC |
1464 | static struct clk tegra_clk_m = { |
1465 | .name = "clk_m", | |
1466 | .flags = ENABLE_ON_INIT, | |
1467 | .ops = &tegra_clk_m_ops, | |
1468 | .inputs = tegra_clk_m_sel, | |
1469 | .reg = 0x1fc, | |
d8611961 | 1470 | .reg_shift = 28, |
71fc84cc | 1471 | .max_rate = 26000000, |
d8611961 CC |
1472 | }; |
1473 | ||
f1519611 | 1474 | static struct clk_pll_freq_table tegra_pll_c_freq_table[] = { |
d8611961 CC |
1475 | { 0, 0, 0, 0, 0, 0 }, |
1476 | }; | |
1477 | ||
1478 | static struct clk tegra_pll_c = { | |
1479 | .name = "pll_c", | |
1480 | .flags = PLL_HAS_CPCON, | |
1481 | .ops = &tegra_pll_ops, | |
1482 | .reg = 0x80, | |
d8611961 | 1483 | .parent = &tegra_clk_m, |
71fc84cc | 1484 | .max_rate = 600000000, |
f1519611 CC |
1485 | .u.pll = { |
1486 | .input_min = 2000000, | |
1487 | .input_max = 31000000, | |
1488 | .cf_min = 1000000, | |
1489 | .cf_max = 6000000, | |
1490 | .vco_min = 20000000, | |
1491 | .vco_max = 1400000000, | |
1492 | .freq_table = tegra_pll_c_freq_table, | |
1493 | .lock_delay = 300, | |
1494 | }, | |
d8611961 CC |
1495 | }; |
1496 | ||
1497 | static struct clk tegra_pll_c_out1 = { | |
1498 | .name = "pll_c_out1", | |
1499 | .ops = &tegra_pll_div_ops, | |
1500 | .flags = DIV_U71, | |
1501 | .parent = &tegra_pll_c, | |
1502 | .reg = 0x84, | |
1503 | .reg_shift = 0, | |
71fc84cc | 1504 | .max_rate = 600000000, |
d8611961 CC |
1505 | }; |
1506 | ||
f1519611 | 1507 | static struct clk_pll_freq_table tegra_pll_m_freq_table[] = { |
71fc84cc CC |
1508 | { 12000000, 666000000, 666, 12, 1, 8}, |
1509 | { 13000000, 666000000, 666, 13, 1, 8}, | |
1510 | { 19200000, 666000000, 555, 16, 1, 8}, | |
1511 | { 26000000, 666000000, 666, 26, 1, 8}, | |
1512 | { 12000000, 600000000, 600, 12, 1, 8}, | |
1513 | { 13000000, 600000000, 600, 13, 1, 8}, | |
1514 | { 19200000, 600000000, 375, 12, 1, 6}, | |
1515 | { 26000000, 600000000, 600, 26, 1, 8}, | |
d8611961 CC |
1516 | { 0, 0, 0, 0, 0, 0 }, |
1517 | }; | |
1518 | ||
1519 | static struct clk tegra_pll_m = { | |
1520 | .name = "pll_m", | |
1521 | .flags = PLL_HAS_CPCON, | |
1522 | .ops = &tegra_pll_ops, | |
1523 | .reg = 0x90, | |
d8611961 | 1524 | .parent = &tegra_clk_m, |
71fc84cc | 1525 | .max_rate = 800000000, |
f1519611 CC |
1526 | .u.pll = { |
1527 | .input_min = 2000000, | |
1528 | .input_max = 31000000, | |
1529 | .cf_min = 1000000, | |
1530 | .cf_max = 6000000, | |
1531 | .vco_min = 20000000, | |
1532 | .vco_max = 1200000000, | |
1533 | .freq_table = tegra_pll_m_freq_table, | |
1534 | .lock_delay = 300, | |
1535 | }, | |
d8611961 CC |
1536 | }; |
1537 | ||
1538 | static struct clk tegra_pll_m_out1 = { | |
1539 | .name = "pll_m_out1", | |
1540 | .ops = &tegra_pll_div_ops, | |
1541 | .flags = DIV_U71, | |
1542 | .parent = &tegra_pll_m, | |
1543 | .reg = 0x94, | |
1544 | .reg_shift = 0, | |
71fc84cc | 1545 | .max_rate = 600000000, |
d8611961 CC |
1546 | }; |
1547 | ||
f1519611 | 1548 | static struct clk_pll_freq_table tegra_pll_p_freq_table[] = { |
d8611961 CC |
1549 | { 12000000, 216000000, 432, 12, 2, 8}, |
1550 | { 13000000, 216000000, 432, 13, 2, 8}, | |
1551 | { 19200000, 216000000, 90, 4, 2, 1}, | |
1552 | { 26000000, 216000000, 432, 26, 2, 8}, | |
1553 | { 12000000, 432000000, 432, 12, 1, 8}, | |
1554 | { 13000000, 432000000, 432, 13, 1, 8}, | |
1555 | { 19200000, 432000000, 90, 4, 1, 1}, | |
1556 | { 26000000, 432000000, 432, 26, 1, 8}, | |
1557 | { 0, 0, 0, 0, 0, 0 }, | |
1558 | }; | |
1559 | ||
1560 | static struct clk tegra_pll_p = { | |
1561 | .name = "pll_p", | |
1562 | .flags = ENABLE_ON_INIT | PLL_FIXED | PLL_HAS_CPCON, | |
1563 | .ops = &tegra_pll_ops, | |
1564 | .reg = 0xa0, | |
d8611961 | 1565 | .parent = &tegra_clk_m, |
71fc84cc | 1566 | .max_rate = 432000000, |
f1519611 CC |
1567 | .u.pll = { |
1568 | .input_min = 2000000, | |
1569 | .input_max = 31000000, | |
1570 | .cf_min = 1000000, | |
1571 | .cf_max = 6000000, | |
1572 | .vco_min = 20000000, | |
1573 | .vco_max = 1400000000, | |
1574 | .freq_table = tegra_pll_p_freq_table, | |
1575 | .lock_delay = 300, | |
1576 | }, | |
d8611961 CC |
1577 | }; |
1578 | ||
1579 | static struct clk tegra_pll_p_out1 = { | |
1580 | .name = "pll_p_out1", | |
1581 | .ops = &tegra_pll_div_ops, | |
1582 | .flags = ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED, | |
1583 | .parent = &tegra_pll_p, | |
1584 | .reg = 0xa4, | |
1585 | .reg_shift = 0, | |
71fc84cc | 1586 | .max_rate = 432000000, |
d8611961 CC |
1587 | }; |
1588 | ||
1589 | static struct clk tegra_pll_p_out2 = { | |
1590 | .name = "pll_p_out2", | |
1591 | .ops = &tegra_pll_div_ops, | |
1592 | .flags = ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED, | |
1593 | .parent = &tegra_pll_p, | |
1594 | .reg = 0xa4, | |
1595 | .reg_shift = 16, | |
71fc84cc | 1596 | .max_rate = 432000000, |
d8611961 CC |
1597 | }; |
1598 | ||
1599 | static struct clk tegra_pll_p_out3 = { | |
1600 | .name = "pll_p_out3", | |
1601 | .ops = &tegra_pll_div_ops, | |
1602 | .flags = ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED, | |
1603 | .parent = &tegra_pll_p, | |
1604 | .reg = 0xa8, | |
1605 | .reg_shift = 0, | |
71fc84cc | 1606 | .max_rate = 432000000, |
d8611961 CC |
1607 | }; |
1608 | ||
1609 | static struct clk tegra_pll_p_out4 = { | |
1610 | .name = "pll_p_out4", | |
1611 | .ops = &tegra_pll_div_ops, | |
1612 | .flags = ENABLE_ON_INIT | DIV_U71 | DIV_U71_FIXED, | |
1613 | .parent = &tegra_pll_p, | |
1614 | .reg = 0xa8, | |
1615 | .reg_shift = 16, | |
71fc84cc | 1616 | .max_rate = 432000000, |
d8611961 CC |
1617 | }; |
1618 | ||
f1519611 | 1619 | static struct clk_pll_freq_table tegra_pll_a_freq_table[] = { |
d8611961 CC |
1620 | { 28800000, 56448000, 49, 25, 1, 1}, |
1621 | { 28800000, 73728000, 64, 25, 1, 1}, | |
71fc84cc | 1622 | { 28800000, 24000000, 5, 6, 1, 1}, |
d8611961 CC |
1623 | { 0, 0, 0, 0, 0, 0 }, |
1624 | }; | |
1625 | ||
1626 | static struct clk tegra_pll_a = { | |
1627 | .name = "pll_a", | |
1628 | .flags = PLL_HAS_CPCON, | |
1629 | .ops = &tegra_pll_ops, | |
1630 | .reg = 0xb0, | |
d8611961 | 1631 | .parent = &tegra_pll_p_out1, |
9c7dc562 | 1632 | .max_rate = 73728000, |
f1519611 CC |
1633 | .u.pll = { |
1634 | .input_min = 2000000, | |
1635 | .input_max = 31000000, | |
1636 | .cf_min = 1000000, | |
1637 | .cf_max = 6000000, | |
1638 | .vco_min = 20000000, | |
1639 | .vco_max = 1400000000, | |
1640 | .freq_table = tegra_pll_a_freq_table, | |
1641 | .lock_delay = 300, | |
1642 | }, | |
d8611961 CC |
1643 | }; |
1644 | ||
1645 | static struct clk tegra_pll_a_out0 = { | |
1646 | .name = "pll_a_out0", | |
1647 | .ops = &tegra_pll_div_ops, | |
1648 | .flags = DIV_U71, | |
1649 | .parent = &tegra_pll_a, | |
1650 | .reg = 0xb4, | |
1651 | .reg_shift = 0, | |
9c7dc562 | 1652 | .max_rate = 73728000, |
d8611961 CC |
1653 | }; |
1654 | ||
f1519611 | 1655 | static struct clk_pll_freq_table tegra_pll_d_freq_table[] = { |
cea62c87 CC |
1656 | { 12000000, 216000000, 216, 12, 1, 4}, |
1657 | { 13000000, 216000000, 216, 13, 1, 4}, | |
1658 | { 19200000, 216000000, 135, 12, 1, 3}, | |
1659 | { 26000000, 216000000, 216, 26, 1, 4}, | |
1660 | ||
1661 | { 12000000, 594000000, 594, 12, 1, 8}, | |
1662 | { 13000000, 594000000, 594, 13, 1, 8}, | |
1663 | { 19200000, 594000000, 495, 16, 1, 8}, | |
1664 | { 26000000, 594000000, 594, 26, 1, 8}, | |
1665 | ||
d8611961 CC |
1666 | { 12000000, 1000000000, 1000, 12, 1, 12}, |
1667 | { 13000000, 1000000000, 1000, 13, 1, 12}, | |
1668 | { 19200000, 1000000000, 625, 12, 1, 8}, | |
1669 | { 26000000, 1000000000, 1000, 26, 1, 12}, | |
cea62c87 | 1670 | |
d8611961 CC |
1671 | { 0, 0, 0, 0, 0, 0 }, |
1672 | }; | |
1673 | ||
1674 | static struct clk tegra_pll_d = { | |
1675 | .name = "pll_d", | |
1676 | .flags = PLL_HAS_CPCON | PLLD, | |
1677 | .ops = &tegra_pll_ops, | |
1678 | .reg = 0xd0, | |
d8611961 | 1679 | .parent = &tegra_clk_m, |
71fc84cc | 1680 | .max_rate = 1000000000, |
f1519611 CC |
1681 | .u.pll = { |
1682 | .input_min = 2000000, | |
1683 | .input_max = 40000000, | |
1684 | .cf_min = 1000000, | |
1685 | .cf_max = 6000000, | |
1686 | .vco_min = 40000000, | |
1687 | .vco_max = 1000000000, | |
1688 | .freq_table = tegra_pll_d_freq_table, | |
1689 | .lock_delay = 1000, | |
1690 | }, | |
d8611961 CC |
1691 | }; |
1692 | ||
1693 | static struct clk tegra_pll_d_out0 = { | |
1694 | .name = "pll_d_out0", | |
1695 | .ops = &tegra_pll_div_ops, | |
1696 | .flags = DIV_2 | PLLD, | |
1697 | .parent = &tegra_pll_d, | |
71fc84cc | 1698 | .max_rate = 500000000, |
d8611961 CC |
1699 | }; |
1700 | ||
f1519611 | 1701 | static struct clk_pll_freq_table tegra_pll_u_freq_table[] = { |
71fc84cc CC |
1702 | { 12000000, 480000000, 960, 12, 2, 0}, |
1703 | { 13000000, 480000000, 960, 13, 2, 0}, | |
1704 | { 19200000, 480000000, 200, 4, 2, 0}, | |
1705 | { 26000000, 480000000, 960, 26, 2, 0}, | |
d8611961 CC |
1706 | { 0, 0, 0, 0, 0, 0 }, |
1707 | }; | |
1708 | ||
1709 | static struct clk tegra_pll_u = { | |
1710 | .name = "pll_u", | |
71fc84cc | 1711 | .flags = PLLU, |
d8611961 CC |
1712 | .ops = &tegra_pll_ops, |
1713 | .reg = 0xc0, | |
d8611961 | 1714 | .parent = &tegra_clk_m, |
71fc84cc | 1715 | .max_rate = 480000000, |
f1519611 CC |
1716 | .u.pll = { |
1717 | .input_min = 2000000, | |
1718 | .input_max = 40000000, | |
1719 | .cf_min = 1000000, | |
1720 | .cf_max = 6000000, | |
1721 | .vco_min = 480000000, | |
1722 | .vco_max = 960000000, | |
1723 | .freq_table = tegra_pll_u_freq_table, | |
1724 | .lock_delay = 1000, | |
1725 | }, | |
1726 | }; | |
1727 | ||
1728 | static struct clk_pll_freq_table tegra_pll_x_freq_table[] = { | |
71fc84cc | 1729 | /* 1 GHz */ |
d8611961 CC |
1730 | { 12000000, 1000000000, 1000, 12, 1, 12}, |
1731 | { 13000000, 1000000000, 1000, 13, 1, 12}, | |
1732 | { 19200000, 1000000000, 625, 12, 1, 8}, | |
1733 | { 26000000, 1000000000, 1000, 26, 1, 12}, | |
71fc84cc CC |
1734 | |
1735 | /* 912 MHz */ | |
1736 | { 12000000, 912000000, 912, 12, 1, 12}, | |
1737 | { 13000000, 912000000, 912, 13, 1, 12}, | |
1738 | { 19200000, 912000000, 760, 16, 1, 8}, | |
1739 | { 26000000, 912000000, 912, 26, 1, 12}, | |
1740 | ||
1741 | /* 816 MHz */ | |
1742 | { 12000000, 816000000, 816, 12, 1, 12}, | |
1743 | { 13000000, 816000000, 816, 13, 1, 12}, | |
1744 | { 19200000, 816000000, 680, 16, 1, 8}, | |
1745 | { 26000000, 816000000, 816, 26, 1, 12}, | |
1746 | ||
1747 | /* 760 MHz */ | |
1748 | { 12000000, 760000000, 760, 12, 1, 12}, | |
1749 | { 13000000, 760000000, 760, 13, 1, 12}, | |
1750 | { 19200000, 760000000, 950, 24, 1, 8}, | |
1751 | { 26000000, 760000000, 760, 26, 1, 12}, | |
1752 | ||
1753 | /* 608 MHz */ | |
9c7dc562 CC |
1754 | { 12000000, 608000000, 608, 12, 1, 12}, |
1755 | { 13000000, 608000000, 608, 13, 1, 12}, | |
71fc84cc | 1756 | { 19200000, 608000000, 380, 12, 1, 8}, |
9c7dc562 | 1757 | { 26000000, 608000000, 608, 26, 1, 12}, |
71fc84cc CC |
1758 | |
1759 | /* 456 MHz */ | |
1760 | { 12000000, 456000000, 456, 12, 1, 12}, | |
1761 | { 13000000, 456000000, 456, 13, 1, 12}, | |
1762 | { 19200000, 456000000, 380, 16, 1, 8}, | |
1763 | { 26000000, 456000000, 456, 26, 1, 12}, | |
1764 | ||
1765 | /* 312 MHz */ | |
1766 | { 12000000, 312000000, 312, 12, 1, 12}, | |
1767 | { 13000000, 312000000, 312, 13, 1, 12}, | |
1768 | { 19200000, 312000000, 260, 16, 1, 8}, | |
1769 | { 26000000, 312000000, 312, 26, 1, 12}, | |
1770 | ||
d8611961 CC |
1771 | { 0, 0, 0, 0, 0, 0 }, |
1772 | }; | |
1773 | ||
1774 | static struct clk tegra_pll_x = { | |
1775 | .name = "pll_x", | |
1776 | .flags = PLL_HAS_CPCON | PLL_ALT_MISC_REG, | |
71fc84cc | 1777 | .ops = &tegra_pllx_ops, |
d8611961 | 1778 | .reg = 0xe0, |
d8611961 | 1779 | .parent = &tegra_clk_m, |
71fc84cc | 1780 | .max_rate = 1000000000, |
f1519611 CC |
1781 | .u.pll = { |
1782 | .input_min = 2000000, | |
1783 | .input_max = 31000000, | |
1784 | .cf_min = 1000000, | |
1785 | .cf_max = 6000000, | |
1786 | .vco_min = 20000000, | |
1787 | .vco_max = 1200000000, | |
1788 | .freq_table = tegra_pll_x_freq_table, | |
1789 | .lock_delay = 300, | |
1790 | }, | |
1791 | }; | |
1792 | ||
1793 | static struct clk_pll_freq_table tegra_pll_e_freq_table[] = { | |
8d685bc5 MR |
1794 | { 12000000, 100000000, 200, 24, 1, 0 }, |
1795 | { 0, 0, 0, 0, 0, 0 }, | |
1796 | }; | |
1797 | ||
1798 | static struct clk tegra_pll_e = { | |
1799 | .name = "pll_e", | |
1800 | .flags = PLL_ALT_MISC_REG, | |
1801 | .ops = &tegra_plle_ops, | |
8d685bc5 MR |
1802 | .parent = &tegra_clk_m, |
1803 | .reg = 0xe8, | |
f1519611 CC |
1804 | .max_rate = 100000000, |
1805 | .u.pll = { | |
1806 | .input_min = 12000000, | |
1807 | .input_max = 12000000, | |
1808 | .freq_table = tegra_pll_e_freq_table, | |
1809 | }, | |
8d685bc5 MR |
1810 | }; |
1811 | ||
d8611961 CC |
1812 | static struct clk tegra_clk_d = { |
1813 | .name = "clk_d", | |
1814 | .flags = PERIPH_NO_RESET, | |
1815 | .ops = &tegra_clk_double_ops, | |
d8611961 CC |
1816 | .reg = 0x34, |
1817 | .reg_shift = 12, | |
1818 | .parent = &tegra_clk_m, | |
71fc84cc | 1819 | .max_rate = 52000000, |
f1519611 CC |
1820 | .u.periph = { |
1821 | .clk_num = 90, | |
1822 | }, | |
71fc84cc CC |
1823 | }; |
1824 | ||
cea62c87 | 1825 | /* dap_mclk1, belongs to the cdev1 pingroup. */ |
ddb7d5d8 SW |
1826 | static struct clk tegra_clk_cdev1 = { |
1827 | .name = "cdev1", | |
cea62c87 | 1828 | .ops = &tegra_cdev_clk_ops, |
cea62c87 CC |
1829 | .rate = 26000000, |
1830 | .max_rate = 26000000, | |
f1519611 CC |
1831 | .u.periph = { |
1832 | .clk_num = 94, | |
1833 | }, | |
cea62c87 CC |
1834 | }; |
1835 | ||
1836 | /* dap_mclk2, belongs to the cdev2 pingroup. */ | |
ddb7d5d8 SW |
1837 | static struct clk tegra_clk_cdev2 = { |
1838 | .name = "cdev2", | |
cea62c87 | 1839 | .ops = &tegra_cdev_clk_ops, |
cea62c87 CC |
1840 | .rate = 26000000, |
1841 | .max_rate = 26000000, | |
f1519611 CC |
1842 | .u.periph = { |
1843 | .clk_num = 93, | |
1844 | }, | |
cea62c87 CC |
1845 | }; |
1846 | ||
71fc84cc CC |
1847 | /* initialized before peripheral clocks */ |
1848 | static struct clk_mux_sel mux_audio_sync_clk[8+1]; | |
1849 | static const struct audio_sources { | |
1850 | const char *name; | |
1851 | int value; | |
1852 | } mux_audio_sync_clk_sources[] = { | |
1853 | { .name = "spdif_in", .value = 0 }, | |
1854 | { .name = "i2s1", .value = 1 }, | |
1855 | { .name = "i2s2", .value = 2 }, | |
1856 | { .name = "pll_a_out0", .value = 4 }, | |
1857 | #if 0 /* FIXME: not implemented */ | |
1858 | { .name = "ac97", .value = 3 }, | |
1859 | { .name = "ext_audio_clk2", .value = 5 }, | |
1860 | { .name = "ext_audio_clk1", .value = 6 }, | |
1861 | { .name = "ext_vimclk", .value = 7 }, | |
1862 | #endif | |
1863 | { 0, 0 } | |
1864 | }; | |
1865 | ||
1866 | static struct clk tegra_clk_audio = { | |
1867 | .name = "audio", | |
1868 | .inputs = mux_audio_sync_clk, | |
1869 | .reg = 0x38, | |
9c7dc562 | 1870 | .max_rate = 73728000, |
71fc84cc | 1871 | .ops = &tegra_audio_sync_clk_ops |
d8611961 CC |
1872 | }; |
1873 | ||
d8611961 | 1874 | static struct clk tegra_clk_audio_2x = { |
71fc84cc | 1875 | .name = "audio_2x", |
d8611961 | 1876 | .flags = PERIPH_NO_RESET, |
71fc84cc | 1877 | .max_rate = 48000000, |
d8611961 | 1878 | .ops = &tegra_clk_double_ops, |
d8611961 CC |
1879 | .reg = 0x34, |
1880 | .reg_shift = 8, | |
71fc84cc | 1881 | .parent = &tegra_clk_audio, |
f1519611 CC |
1882 | .u.periph = { |
1883 | .clk_num = 89, | |
1884 | }, | |
71fc84cc CC |
1885 | }; |
1886 | ||
1887 | struct clk_lookup tegra_audio_clk_lookups[] = { | |
1888 | { .con_id = "audio", .clk = &tegra_clk_audio }, | |
1889 | { .con_id = "audio_2x", .clk = &tegra_clk_audio_2x } | |
1890 | }; | |
1891 | ||
1892 | /* This is called after peripheral clocks are initialized, as the | |
1893 | * audio_sync clock depends on some of the peripheral clocks. | |
1894 | */ | |
1895 | ||
1896 | static void init_audio_sync_clock_mux(void) | |
1897 | { | |
1898 | int i; | |
1899 | struct clk_mux_sel *sel = mux_audio_sync_clk; | |
1900 | const struct audio_sources *src = mux_audio_sync_clk_sources; | |
1901 | struct clk_lookup *lookup; | |
1902 | ||
1903 | for (i = 0; src->name; i++, sel++, src++) { | |
1904 | sel->input = tegra_get_clock_by_name(src->name); | |
1905 | if (!sel->input) | |
1906 | pr_err("%s: could not find clk %s\n", __func__, | |
1907 | src->name); | |
1908 | sel->value = src->value; | |
1909 | } | |
1910 | ||
1911 | lookup = tegra_audio_clk_lookups; | |
1912 | for (i = 0; i < ARRAY_SIZE(tegra_audio_clk_lookups); i++, lookup++) { | |
1913 | clk_init(lookup->clk); | |
1914 | clkdev_add(lookup); | |
1915 | } | |
d8611961 | 1916 | } |
d8611961 CC |
1917 | |
1918 | static struct clk_mux_sel mux_cclk[] = { | |
1919 | { .input = &tegra_clk_m, .value = 0}, | |
1920 | { .input = &tegra_pll_c, .value = 1}, | |
1921 | { .input = &tegra_clk_32k, .value = 2}, | |
1922 | { .input = &tegra_pll_m, .value = 3}, | |
1923 | { .input = &tegra_pll_p, .value = 4}, | |
1924 | { .input = &tegra_pll_p_out4, .value = 5}, | |
1925 | { .input = &tegra_pll_p_out3, .value = 6}, | |
1926 | { .input = &tegra_clk_d, .value = 7}, | |
1927 | { .input = &tegra_pll_x, .value = 8}, | |
1928 | { 0, 0}, | |
1929 | }; | |
1930 | ||
1931 | static struct clk_mux_sel mux_sclk[] = { | |
1932 | { .input = &tegra_clk_m, .value = 0}, | |
1933 | { .input = &tegra_pll_c_out1, .value = 1}, | |
1934 | { .input = &tegra_pll_p_out4, .value = 2}, | |
1935 | { .input = &tegra_pll_p_out3, .value = 3}, | |
1936 | { .input = &tegra_pll_p_out2, .value = 4}, | |
1937 | { .input = &tegra_clk_d, .value = 5}, | |
1938 | { .input = &tegra_clk_32k, .value = 6}, | |
1939 | { .input = &tegra_pll_m_out1, .value = 7}, | |
1940 | { 0, 0}, | |
1941 | }; | |
1942 | ||
71fc84cc CC |
1943 | static struct clk tegra_clk_cclk = { |
1944 | .name = "cclk", | |
d8611961 CC |
1945 | .inputs = mux_cclk, |
1946 | .reg = 0x20, | |
1947 | .ops = &tegra_super_ops, | |
71fc84cc | 1948 | .max_rate = 1000000000, |
d8611961 CC |
1949 | }; |
1950 | ||
71fc84cc CC |
1951 | static struct clk tegra_clk_sclk = { |
1952 | .name = "sclk", | |
d8611961 CC |
1953 | .inputs = mux_sclk, |
1954 | .reg = 0x28, | |
1955 | .ops = &tegra_super_ops, | |
9c7dc562 CC |
1956 | .max_rate = 240000000, |
1957 | .min_rate = 120000000, | |
71fc84cc CC |
1958 | }; |
1959 | ||
1960 | static struct clk tegra_clk_virtual_cpu = { | |
1961 | .name = "cpu", | |
1962 | .parent = &tegra_clk_cclk, | |
71fc84cc CC |
1963 | .ops = &tegra_cpu_ops, |
1964 | .max_rate = 1000000000, | |
f1519611 CC |
1965 | .u.cpu = { |
1966 | .main = &tegra_pll_x, | |
1967 | .backup = &tegra_pll_p, | |
1968 | }, | |
d8611961 CC |
1969 | }; |
1970 | ||
9c7dc562 CC |
1971 | static struct clk tegra_clk_cop = { |
1972 | .name = "cop", | |
1973 | .parent = &tegra_clk_sclk, | |
1974 | .ops = &tegra_cop_ops, | |
1975 | .max_rate = 240000000, | |
1976 | }; | |
1977 | ||
d8611961 CC |
1978 | static struct clk tegra_clk_hclk = { |
1979 | .name = "hclk", | |
1980 | .flags = DIV_BUS, | |
71fc84cc | 1981 | .parent = &tegra_clk_sclk, |
d8611961 CC |
1982 | .reg = 0x30, |
1983 | .reg_shift = 4, | |
1984 | .ops = &tegra_bus_ops, | |
71fc84cc | 1985 | .max_rate = 240000000, |
d8611961 CC |
1986 | }; |
1987 | ||
1988 | static struct clk tegra_clk_pclk = { | |
1989 | .name = "pclk", | |
1990 | .flags = DIV_BUS, | |
1991 | .parent = &tegra_clk_hclk, | |
1992 | .reg = 0x30, | |
1993 | .reg_shift = 0, | |
1994 | .ops = &tegra_bus_ops, | |
9c7dc562 | 1995 | .max_rate = 120000000, |
d8611961 CC |
1996 | }; |
1997 | ||
cea62c87 CC |
1998 | static struct clk tegra_clk_blink = { |
1999 | .name = "blink", | |
2000 | .parent = &tegra_clk_32k, | |
2001 | .reg = 0x40, | |
2002 | .ops = &tegra_blink_clk_ops, | |
2003 | .max_rate = 32768, | |
2004 | }; | |
2005 | ||
d8611961 CC |
2006 | static struct clk_mux_sel mux_pllm_pllc_pllp_plla[] = { |
2007 | { .input = &tegra_pll_m, .value = 0}, | |
2008 | { .input = &tegra_pll_c, .value = 1}, | |
2009 | { .input = &tegra_pll_p, .value = 2}, | |
2010 | { .input = &tegra_pll_a_out0, .value = 3}, | |
2011 | { 0, 0}, | |
2012 | }; | |
2013 | ||
2014 | static struct clk_mux_sel mux_pllm_pllc_pllp_clkm[] = { | |
2015 | { .input = &tegra_pll_m, .value = 0}, | |
2016 | { .input = &tegra_pll_c, .value = 1}, | |
2017 | { .input = &tegra_pll_p, .value = 2}, | |
2018 | { .input = &tegra_clk_m, .value = 3}, | |
2019 | { 0, 0}, | |
2020 | }; | |
2021 | ||
2022 | static struct clk_mux_sel mux_pllp_pllc_pllm_clkm[] = { | |
2023 | { .input = &tegra_pll_p, .value = 0}, | |
2024 | { .input = &tegra_pll_c, .value = 1}, | |
2025 | { .input = &tegra_pll_m, .value = 2}, | |
2026 | { .input = &tegra_clk_m, .value = 3}, | |
2027 | { 0, 0}, | |
2028 | }; | |
2029 | ||
71fc84cc CC |
2030 | static struct clk_mux_sel mux_pllaout0_audio2x_pllp_clkm[] = { |
2031 | {.input = &tegra_pll_a_out0, .value = 0}, | |
2032 | {.input = &tegra_clk_audio_2x, .value = 1}, | |
d8611961 CC |
2033 | {.input = &tegra_pll_p, .value = 2}, |
2034 | {.input = &tegra_clk_m, .value = 3}, | |
2035 | { 0, 0}, | |
2036 | }; | |
2037 | ||
2038 | static struct clk_mux_sel mux_pllp_plld_pllc_clkm[] = { | |
2039 | {.input = &tegra_pll_p, .value = 0}, | |
2040 | {.input = &tegra_pll_d_out0, .value = 1}, | |
2041 | {.input = &tegra_pll_c, .value = 2}, | |
2042 | {.input = &tegra_clk_m, .value = 3}, | |
2043 | { 0, 0}, | |
2044 | }; | |
2045 | ||
2046 | static struct clk_mux_sel mux_pllp_pllc_audio_clkm_clk32[] = { | |
2047 | {.input = &tegra_pll_p, .value = 0}, | |
2048 | {.input = &tegra_pll_c, .value = 1}, | |
71fc84cc | 2049 | {.input = &tegra_clk_audio, .value = 2}, |
d8611961 CC |
2050 | {.input = &tegra_clk_m, .value = 3}, |
2051 | {.input = &tegra_clk_32k, .value = 4}, | |
2052 | { 0, 0}, | |
2053 | }; | |
2054 | ||
2055 | static struct clk_mux_sel mux_pllp_pllc_pllm[] = { | |
2056 | {.input = &tegra_pll_p, .value = 0}, | |
2057 | {.input = &tegra_pll_c, .value = 1}, | |
2058 | {.input = &tegra_pll_m, .value = 2}, | |
2059 | { 0, 0}, | |
2060 | }; | |
2061 | ||
2062 | static struct clk_mux_sel mux_clk_m[] = { | |
2063 | { .input = &tegra_clk_m, .value = 0}, | |
2064 | { 0, 0}, | |
2065 | }; | |
2066 | ||
2067 | static struct clk_mux_sel mux_pllp_out3[] = { | |
2068 | { .input = &tegra_pll_p_out3, .value = 0}, | |
2069 | { 0, 0}, | |
2070 | }; | |
2071 | ||
2072 | static struct clk_mux_sel mux_plld[] = { | |
2073 | { .input = &tegra_pll_d, .value = 0}, | |
2074 | { 0, 0}, | |
2075 | }; | |
2076 | ||
2077 | static struct clk_mux_sel mux_clk_32k[] = { | |
2078 | { .input = &tegra_clk_32k, .value = 0}, | |
2079 | { 0, 0}, | |
2080 | }; | |
2081 | ||
1ca00347 SW |
2082 | static struct clk_mux_sel mux_pclk[] = { |
2083 | { .input = &tegra_clk_pclk, .value = 0}, | |
2084 | { 0, 0}, | |
2085 | }; | |
2086 | ||
6d296828 CC |
2087 | static struct clk tegra_clk_emc = { |
2088 | .name = "emc", | |
2089 | .ops = &tegra_emc_clk_ops, | |
2090 | .reg = 0x19c, | |
2091 | .max_rate = 800000000, | |
2092 | .inputs = mux_pllm_pllc_pllp_clkm, | |
2093 | .flags = MUX | DIV_U71 | PERIPH_EMC_ENB, | |
2094 | .u.periph = { | |
2095 | .clk_num = 57, | |
2096 | }, | |
2097 | }; | |
2098 | ||
71fc84cc | 2099 | #define PERIPH_CLK(_name, _dev, _con, _clk_num, _reg, _max, _inputs, _flags) \ |
d8611961 CC |
2100 | { \ |
2101 | .name = _name, \ | |
2102 | .lookup = { \ | |
2103 | .dev_id = _dev, \ | |
2104 | .con_id = _con, \ | |
2105 | }, \ | |
2106 | .ops = &tegra_periph_clk_ops, \ | |
d8611961 CC |
2107 | .reg = _reg, \ |
2108 | .inputs = _inputs, \ | |
2109 | .flags = _flags, \ | |
71fc84cc | 2110 | .max_rate = _max, \ |
f1519611 CC |
2111 | .u.periph = { \ |
2112 | .clk_num = _clk_num, \ | |
2113 | }, \ | |
d8611961 CC |
2114 | } |
2115 | ||
310992ca CC |
2116 | #define SHARED_CLK(_name, _dev, _con, _parent) \ |
2117 | { \ | |
2118 | .name = _name, \ | |
2119 | .lookup = { \ | |
2120 | .dev_id = _dev, \ | |
2121 | .con_id = _con, \ | |
2122 | }, \ | |
2123 | .ops = &tegra_clk_shared_bus_ops, \ | |
2124 | .parent = _parent, \ | |
2125 | } | |
2126 | ||
3ec349fb | 2127 | struct clk tegra_list_clks[] = { |
1ca00347 | 2128 | PERIPH_CLK("apbdma", "tegra-dma", NULL, 34, 0, 108000000, mux_pclk, 0), |
71fc84cc CC |
2129 | PERIPH_CLK("rtc", "rtc-tegra", NULL, 4, 0, 32768, mux_clk_32k, PERIPH_NO_RESET), |
2130 | PERIPH_CLK("timer", "timer", NULL, 5, 0, 26000000, mux_clk_m, 0), | |
3c106bf5 SW |
2131 | PERIPH_CLK("i2s1", "tegra-i2s.0", NULL, 11, 0x100, 26000000, mux_pllaout0_audio2x_pllp_clkm, MUX | DIV_U71), |
2132 | PERIPH_CLK("i2s2", "tegra-i2s.1", NULL, 18, 0x104, 26000000, mux_pllaout0_audio2x_pllp_clkm, MUX | DIV_U71), | |
71fc84cc CC |
2133 | PERIPH_CLK("spdif_out", "spdif_out", NULL, 10, 0x108, 100000000, mux_pllaout0_audio2x_pllp_clkm, MUX | DIV_U71), |
2134 | PERIPH_CLK("spdif_in", "spdif_in", NULL, 10, 0x10c, 100000000, mux_pllp_pllc_pllm, MUX | DIV_U71), | |
2135 | PERIPH_CLK("pwm", "pwm", NULL, 17, 0x110, 432000000, mux_pllp_pllc_audio_clkm_clk32, MUX | DIV_U71), | |
2136 | PERIPH_CLK("spi", "spi", NULL, 43, 0x114, 40000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), | |
2137 | PERIPH_CLK("xio", "xio", NULL, 45, 0x120, 150000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), | |
2138 | PERIPH_CLK("twc", "twc", NULL, 16, 0x12c, 150000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), | |
2139 | PERIPH_CLK("sbc1", "spi_tegra.0", NULL, 41, 0x134, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), | |
2140 | PERIPH_CLK("sbc2", "spi_tegra.1", NULL, 44, 0x118, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), | |
2141 | PERIPH_CLK("sbc3", "spi_tegra.2", NULL, 46, 0x11c, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), | |
2142 | PERIPH_CLK("sbc4", "spi_tegra.3", NULL, 68, 0x1b4, 160000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), | |
2143 | PERIPH_CLK("ide", "ide", NULL, 25, 0x144, 100000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* requires min voltage */ | |
2144 | PERIPH_CLK("ndflash", "tegra_nand", NULL, 13, 0x160, 164000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage */ | |
71fc84cc CC |
2145 | PERIPH_CLK("vfir", "vfir", NULL, 7, 0x168, 72000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), |
2146 | PERIPH_CLK("sdmmc1", "sdhci-tegra.0", NULL, 14, 0x150, 52000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage */ | |
2147 | PERIPH_CLK("sdmmc2", "sdhci-tegra.1", NULL, 9, 0x154, 52000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage */ | |
2148 | PERIPH_CLK("sdmmc3", "sdhci-tegra.2", NULL, 69, 0x1bc, 52000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage */ | |
cea62c87 | 2149 | PERIPH_CLK("sdmmc4", "sdhci-tegra.3", NULL, 15, 0x164, 52000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage */ |
9c7dc562 CC |
2150 | PERIPH_CLK("vcp", "tegra-avp", "vcp", 29, 0, 250000000, mux_clk_m, 0), |
2151 | PERIPH_CLK("bsea", "tegra-avp", "bsea", 62, 0, 250000000, mux_clk_m, 0), | |
2152 | PERIPH_CLK("bsev", "tegra-aes", "bsev", 63, 0, 250000000, mux_clk_m, 0), | |
2153 | PERIPH_CLK("vde", "tegra-avp", "vde", 61, 0x1c8, 250000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage and process_id */ | |
71fc84cc | 2154 | PERIPH_CLK("csite", "csite", NULL, 73, 0x1d4, 144000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* max rate ??? */ |
d8611961 | 2155 | /* FIXME: what is la? */ |
71fc84cc CC |
2156 | PERIPH_CLK("la", "la", NULL, 76, 0x1f8, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), |
2157 | PERIPH_CLK("owr", "tegra_w1", NULL, 71, 0x1cc, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), | |
2158 | PERIPH_CLK("nor", "nor", NULL, 42, 0x1d0, 92000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* requires min voltage */ | |
2159 | PERIPH_CLK("mipi", "mipi", NULL, 50, 0x174, 60000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U71), /* scales with voltage */ | |
2160 | PERIPH_CLK("i2c1", "tegra-i2c.0", NULL, 12, 0x124, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U16), | |
2161 | PERIPH_CLK("i2c2", "tegra-i2c.1", NULL, 54, 0x198, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U16), | |
2162 | PERIPH_CLK("i2c3", "tegra-i2c.2", NULL, 67, 0x1b8, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U16), | |
2163 | PERIPH_CLK("dvc", "tegra-i2c.3", NULL, 47, 0x128, 26000000, mux_pllp_pllc_pllm_clkm, MUX | DIV_U16), | |
2164 | PERIPH_CLK("i2c1_i2c", "tegra-i2c.0", "i2c", 0, 0, 72000000, mux_pllp_out3, 0), | |
2165 | PERIPH_CLK("i2c2_i2c", "tegra-i2c.1", "i2c", 0, 0, 72000000, mux_pllp_out3, 0), | |
2166 | PERIPH_CLK("i2c3_i2c", "tegra-i2c.2", "i2c", 0, 0, 72000000, mux_pllp_out3, 0), | |
2167 | PERIPH_CLK("dvc_i2c", "tegra-i2c.3", "i2c", 0, 0, 72000000, mux_pllp_out3, 0), | |
cea62c87 CC |
2168 | PERIPH_CLK("uarta", "uart.0", NULL, 6, 0x178, 600000000, mux_pllp_pllc_pllm_clkm, MUX), |
2169 | PERIPH_CLK("uartb", "uart.1", NULL, 7, 0x17c, 600000000, mux_pllp_pllc_pllm_clkm, MUX), | |
2170 | PERIPH_CLK("uartc", "uart.2", NULL, 55, 0x1a0, 600000000, mux_pllp_pllc_pllm_clkm, MUX), | |
2171 | PERIPH_CLK("uartd", "uart.3", NULL, 65, 0x1c0, 600000000, mux_pllp_pllc_pllm_clkm, MUX), | |
2172 | PERIPH_CLK("uarte", "uart.4", NULL, 66, 0x1c4, 600000000, mux_pllp_pllc_pllm_clkm, MUX), | |
71fc84cc CC |
2173 | PERIPH_CLK("3d", "3d", NULL, 24, 0x158, 300000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | PERIPH_MANUAL_RESET), /* scales with voltage and process_id */ |
2174 | PERIPH_CLK("2d", "2d", NULL, 21, 0x15c, 300000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71), /* scales with voltage and process_id */ | |
cea62c87 CC |
2175 | PERIPH_CLK("vi", "tegra_camera", "vi", 20, 0x148, 150000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71), /* scales with voltage and process_id */ |
2176 | PERIPH_CLK("vi_sensor", "tegra_camera", "vi_sensor", 20, 0x1a8, 150000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71 | PERIPH_NO_RESET), /* scales with voltage and process_id */ | |
71fc84cc CC |
2177 | PERIPH_CLK("epp", "epp", NULL, 19, 0x16c, 300000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71), /* scales with voltage and process_id */ |
2178 | PERIPH_CLK("mpe", "mpe", NULL, 60, 0x170, 250000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71), /* scales with voltage and process_id */ | |
2179 | PERIPH_CLK("host1x", "host1x", NULL, 28, 0x180, 166000000, mux_pllm_pllc_pllp_plla, MUX | DIV_U71), /* scales with voltage and process_id */ | |
71fc84cc CC |
2180 | PERIPH_CLK("cve", "cve", NULL, 49, 0x140, 250000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71), /* requires min voltage */ |
2181 | PERIPH_CLK("tvo", "tvo", NULL, 49, 0x188, 250000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71), /* requires min voltage */ | |
cea62c87 | 2182 | PERIPH_CLK("hdmi", "hdmi", NULL, 51, 0x18c, 600000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71), /* requires min voltage */ |
71fc84cc | 2183 | PERIPH_CLK("tvdac", "tvdac", NULL, 53, 0x194, 250000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71), /* requires min voltage */ |
cea62c87 CC |
2184 | PERIPH_CLK("disp1", "tegradc.0", NULL, 27, 0x138, 600000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71), /* scales with voltage and process_id */ |
2185 | PERIPH_CLK("disp2", "tegradc.1", NULL, 26, 0x13c, 600000000, mux_pllp_plld_pllc_clkm, MUX | DIV_U71), /* scales with voltage and process_id */ | |
71fc84cc CC |
2186 | PERIPH_CLK("usbd", "fsl-tegra-udc", NULL, 22, 0, 480000000, mux_clk_m, 0), /* requires min voltage */ |
2187 | PERIPH_CLK("usb2", "tegra-ehci.1", NULL, 58, 0, 480000000, mux_clk_m, 0), /* requires min voltage */ | |
2188 | PERIPH_CLK("usb3", "tegra-ehci.2", NULL, 59, 0, 480000000, mux_clk_m, 0), /* requires min voltage */ | |
71fc84cc | 2189 | PERIPH_CLK("dsi", "dsi", NULL, 48, 0, 500000000, mux_plld, 0), /* scales with voltage */ |
cea62c87 CC |
2190 | PERIPH_CLK("csi", "tegra_camera", "csi", 52, 0, 72000000, mux_pllp_out3, 0), |
2191 | PERIPH_CLK("isp", "tegra_camera", "isp", 23, 0, 150000000, mux_clk_m, 0), /* same frequency as VI */ | |
2192 | PERIPH_CLK("csus", "tegra_camera", "csus", 92, 0, 150000000, mux_clk_m, PERIPH_NO_RESET), | |
8d685bc5 MR |
2193 | PERIPH_CLK("pex", NULL, "pex", 70, 0, 26000000, mux_clk_m, PERIPH_MANUAL_RESET), |
2194 | PERIPH_CLK("afi", NULL, "afi", 72, 0, 26000000, mux_clk_m, PERIPH_MANUAL_RESET), | |
2195 | PERIPH_CLK("pcie_xclk", NULL, "pcie_xclk", 74, 0, 26000000, mux_clk_m, PERIPH_MANUAL_RESET), | |
9c7dc562 CC |
2196 | |
2197 | SHARED_CLK("avp.sclk", "tegra-avp", "sclk", &tegra_clk_sclk), | |
2198 | SHARED_CLK("avp.emc", "tegra-avp", "emc", &tegra_clk_emc), | |
2199 | SHARED_CLK("cpu.emc", "cpu", "emc", &tegra_clk_emc), | |
2200 | SHARED_CLK("disp1.emc", "tegradc.0", "emc", &tegra_clk_emc), | |
2201 | SHARED_CLK("disp2.emc", "tegradc.1", "emc", &tegra_clk_emc), | |
2202 | SHARED_CLK("hdmi.emc", "hdmi", "emc", &tegra_clk_emc), | |
2203 | SHARED_CLK("host.emc", "tegra_grhost", "emc", &tegra_clk_emc), | |
2204 | SHARED_CLK("usbd.emc", "fsl-tegra-udc", "emc", &tegra_clk_emc), | |
2205 | SHARED_CLK("usb1.emc", "tegra-ehci.0", "emc", &tegra_clk_emc), | |
2206 | SHARED_CLK("usb2.emc", "tegra-ehci.1", "emc", &tegra_clk_emc), | |
2207 | SHARED_CLK("usb3.emc", "tegra-ehci.2", "emc", &tegra_clk_emc), | |
d8611961 CC |
2208 | }; |
2209 | ||
2210 | #define CLK_DUPLICATE(_name, _dev, _con) \ | |
2211 | { \ | |
2212 | .name = _name, \ | |
2213 | .lookup = { \ | |
2214 | .dev_id = _dev, \ | |
2215 | .con_id = _con, \ | |
2216 | }, \ | |
2217 | } | |
2218 | ||
2219 | /* Some clocks may be used by different drivers depending on the board | |
2220 | * configuration. List those here to register them twice in the clock lookup | |
2221 | * table under two names. | |
2222 | */ | |
2223 | struct clk_duplicate tegra_clk_duplicates[] = { | |
2224 | CLK_DUPLICATE("uarta", "tegra_uart.0", NULL), | |
2225 | CLK_DUPLICATE("uartb", "tegra_uart.1", NULL), | |
2226 | CLK_DUPLICATE("uartc", "tegra_uart.2", NULL), | |
2227 | CLK_DUPLICATE("uartd", "tegra_uart.3", NULL), | |
2228 | CLK_DUPLICATE("uarte", "tegra_uart.4", NULL), | |
cea62c87 | 2229 | CLK_DUPLICATE("usbd", "utmip-pad", NULL), |
71fc84cc | 2230 | CLK_DUPLICATE("usbd", "tegra-ehci.0", NULL), |
cea62c87 CC |
2231 | CLK_DUPLICATE("usbd", "tegra-otg", NULL), |
2232 | CLK_DUPLICATE("hdmi", "tegradc.0", "hdmi"), | |
2233 | CLK_DUPLICATE("hdmi", "tegradc.1", "hdmi"), | |
2234 | CLK_DUPLICATE("pwm", "tegra_pwm.0", NULL), | |
2235 | CLK_DUPLICATE("pwm", "tegra_pwm.1", NULL), | |
2236 | CLK_DUPLICATE("pwm", "tegra_pwm.2", NULL), | |
2237 | CLK_DUPLICATE("pwm", "tegra_pwm.3", NULL), | |
9c7dc562 CC |
2238 | CLK_DUPLICATE("host1x", "tegra_grhost", "host1x"), |
2239 | CLK_DUPLICATE("2d", "tegra_grhost", "gr2d"), | |
2240 | CLK_DUPLICATE("3d", "tegra_grhost", "gr3d"), | |
2241 | CLK_DUPLICATE("epp", "tegra_grhost", "epp"), | |
2242 | CLK_DUPLICATE("mpe", "tegra_grhost", "mpe"), | |
2243 | CLK_DUPLICATE("cop", "tegra-avp", "cop"), | |
2244 | CLK_DUPLICATE("vde", "tegra-aes", "vde"), | |
d8611961 CC |
2245 | }; |
2246 | ||
2247 | #define CLK(dev, con, ck) \ | |
2248 | { \ | |
2249 | .dev_id = dev, \ | |
2250 | .con_id = con, \ | |
2251 | .clk = ck, \ | |
2252 | } | |
2253 | ||
3ec349fb CC |
2254 | struct clk *tegra_ptr_clks[] = { |
2255 | &tegra_clk_32k, | |
2256 | &tegra_pll_s, | |
2257 | &tegra_clk_m, | |
2258 | &tegra_pll_m, | |
2259 | &tegra_pll_m_out1, | |
2260 | &tegra_pll_c, | |
2261 | &tegra_pll_c_out1, | |
2262 | &tegra_pll_p, | |
2263 | &tegra_pll_p_out1, | |
2264 | &tegra_pll_p_out2, | |
2265 | &tegra_pll_p_out3, | |
2266 | &tegra_pll_p_out4, | |
2267 | &tegra_pll_a, | |
2268 | &tegra_pll_a_out0, | |
2269 | &tegra_pll_d, | |
2270 | &tegra_pll_d_out0, | |
2271 | &tegra_pll_u, | |
2272 | &tegra_pll_x, | |
2273 | &tegra_pll_e, | |
2274 | &tegra_clk_cclk, | |
2275 | &tegra_clk_sclk, | |
2276 | &tegra_clk_hclk, | |
2277 | &tegra_clk_pclk, | |
2278 | &tegra_clk_d, | |
ddb7d5d8 SW |
2279 | &tegra_clk_cdev1, |
2280 | &tegra_clk_cdev2, | |
3ec349fb CC |
2281 | &tegra_clk_virtual_cpu, |
2282 | &tegra_clk_blink, | |
9c7dc562 | 2283 | &tegra_clk_cop, |
6d296828 | 2284 | &tegra_clk_emc, |
3ec349fb CC |
2285 | }; |
2286 | ||
2287 | static void tegra2_init_one_clock(struct clk *c) | |
2288 | { | |
2289 | clk_init(c); | |
310992ca | 2290 | INIT_LIST_HEAD(&c->shared_bus_list); |
3ec349fb CC |
2291 | if (!c->lookup.dev_id && !c->lookup.con_id) |
2292 | c->lookup.con_id = c->name; | |
2293 | c->lookup.clk = c; | |
2294 | clkdev_add(&c->lookup); | |
2295 | } | |
d8611961 CC |
2296 | |
2297 | void __init tegra2_init_clocks(void) | |
2298 | { | |
2299 | int i; | |
d8611961 | 2300 | struct clk *c; |
d8611961 | 2301 | |
3ec349fb CC |
2302 | for (i = 0; i < ARRAY_SIZE(tegra_ptr_clks); i++) |
2303 | tegra2_init_one_clock(tegra_ptr_clks[i]); | |
d8611961 | 2304 | |
3ec349fb CC |
2305 | for (i = 0; i < ARRAY_SIZE(tegra_list_clks); i++) |
2306 | tegra2_init_one_clock(&tegra_list_clks[i]); | |
d8611961 CC |
2307 | |
2308 | for (i = 0; i < ARRAY_SIZE(tegra_clk_duplicates); i++) { | |
3ec349fb CC |
2309 | c = tegra_get_clock_by_name(tegra_clk_duplicates[i].name); |
2310 | if (!c) { | |
d8611961 | 2311 | pr_err("%s: Unknown duplicate clock %s\n", __func__, |
3ec349fb CC |
2312 | tegra_clk_duplicates[i].name); |
2313 | continue; | |
d8611961 | 2314 | } |
3ec349fb CC |
2315 | |
2316 | tegra_clk_duplicates[i].lookup.clk = c; | |
2317 | clkdev_add(&tegra_clk_duplicates[i].lookup); | |
d8611961 | 2318 | } |
71fc84cc CC |
2319 | |
2320 | init_audio_sync_clock_mux(); | |
2321 | } | |
2322 | ||
2323 | #ifdef CONFIG_PM | |
2324 | static u32 clk_rst_suspend[RST_DEVICES_NUM + CLK_OUT_ENB_NUM + | |
c2f44a9d | 2325 | PERIPH_CLK_SOURCE_NUM + 22]; |
71fc84cc CC |
2326 | |
2327 | void tegra_clk_suspend(void) | |
2328 | { | |
2329 | unsigned long off, i; | |
2330 | u32 *ctx = clk_rst_suspend; | |
2331 | ||
2332 | *ctx++ = clk_readl(OSC_CTRL) & OSC_CTRL_MASK; | |
cea62c87 CC |
2333 | *ctx++ = clk_readl(tegra_pll_c.reg + PLL_BASE); |
2334 | *ctx++ = clk_readl(tegra_pll_c.reg + PLL_MISC(&tegra_pll_c)); | |
2335 | *ctx++ = clk_readl(tegra_pll_a.reg + PLL_BASE); | |
2336 | *ctx++ = clk_readl(tegra_pll_a.reg + PLL_MISC(&tegra_pll_a)); | |
c2f44a9d CC |
2337 | *ctx++ = clk_readl(tegra_pll_s.reg + PLL_BASE); |
2338 | *ctx++ = clk_readl(tegra_pll_s.reg + PLL_MISC(&tegra_pll_s)); | |
2339 | *ctx++ = clk_readl(tegra_pll_d.reg + PLL_BASE); | |
2340 | *ctx++ = clk_readl(tegra_pll_d.reg + PLL_MISC(&tegra_pll_d)); | |
2341 | *ctx++ = clk_readl(tegra_pll_u.reg + PLL_BASE); | |
2342 | *ctx++ = clk_readl(tegra_pll_u.reg + PLL_MISC(&tegra_pll_u)); | |
cea62c87 CC |
2343 | |
2344 | *ctx++ = clk_readl(tegra_pll_m_out1.reg); | |
cea62c87 CC |
2345 | *ctx++ = clk_readl(tegra_pll_a_out0.reg); |
2346 | *ctx++ = clk_readl(tegra_pll_c_out1.reg); | |
2347 | ||
2348 | *ctx++ = clk_readl(tegra_clk_cclk.reg); | |
2349 | *ctx++ = clk_readl(tegra_clk_cclk.reg + SUPER_CLK_DIVIDER); | |
2350 | ||
2351 | *ctx++ = clk_readl(tegra_clk_sclk.reg); | |
2352 | *ctx++ = clk_readl(tegra_clk_sclk.reg + SUPER_CLK_DIVIDER); | |
2353 | *ctx++ = clk_readl(tegra_clk_pclk.reg); | |
71fc84cc | 2354 | |
c2f44a9d CC |
2355 | *ctx++ = clk_readl(tegra_clk_audio.reg); |
2356 | ||
71fc84cc CC |
2357 | for (off = PERIPH_CLK_SOURCE_I2S1; off <= PERIPH_CLK_SOURCE_OSC; |
2358 | off += 4) { | |
2359 | if (off == PERIPH_CLK_SOURCE_EMC) | |
2360 | continue; | |
2361 | *ctx++ = clk_readl(off); | |
2362 | } | |
2363 | ||
2364 | off = RST_DEVICES; | |
2365 | for (i = 0; i < RST_DEVICES_NUM; i++, off += 4) | |
2366 | *ctx++ = clk_readl(off); | |
2367 | ||
2368 | off = CLK_OUT_ENB; | |
2369 | for (i = 0; i < CLK_OUT_ENB_NUM; i++, off += 4) | |
2370 | *ctx++ = clk_readl(off); | |
2371 | ||
2372 | *ctx++ = clk_readl(MISC_CLK_ENB); | |
2373 | *ctx++ = clk_readl(CLK_MASK_ARM); | |
c2f44a9d CC |
2374 | |
2375 | BUG_ON(ctx - clk_rst_suspend != ARRAY_SIZE(clk_rst_suspend)); | |
71fc84cc CC |
2376 | } |
2377 | ||
2378 | void tegra_clk_resume(void) | |
2379 | { | |
2380 | unsigned long off, i; | |
2381 | const u32 *ctx = clk_rst_suspend; | |
2382 | u32 val; | |
2383 | ||
2384 | val = clk_readl(OSC_CTRL) & ~OSC_CTRL_MASK; | |
2385 | val |= *ctx++; | |
2386 | clk_writel(val, OSC_CTRL); | |
2387 | ||
cea62c87 CC |
2388 | clk_writel(*ctx++, tegra_pll_c.reg + PLL_BASE); |
2389 | clk_writel(*ctx++, tegra_pll_c.reg + PLL_MISC(&tegra_pll_c)); | |
2390 | clk_writel(*ctx++, tegra_pll_a.reg + PLL_BASE); | |
2391 | clk_writel(*ctx++, tegra_pll_a.reg + PLL_MISC(&tegra_pll_a)); | |
c2f44a9d CC |
2392 | clk_writel(*ctx++, tegra_pll_s.reg + PLL_BASE); |
2393 | clk_writel(*ctx++, tegra_pll_s.reg + PLL_MISC(&tegra_pll_s)); | |
2394 | clk_writel(*ctx++, tegra_pll_d.reg + PLL_BASE); | |
2395 | clk_writel(*ctx++, tegra_pll_d.reg + PLL_MISC(&tegra_pll_d)); | |
2396 | clk_writel(*ctx++, tegra_pll_u.reg + PLL_BASE); | |
2397 | clk_writel(*ctx++, tegra_pll_u.reg + PLL_MISC(&tegra_pll_u)); | |
2398 | udelay(1000); | |
cea62c87 CC |
2399 | |
2400 | clk_writel(*ctx++, tegra_pll_m_out1.reg); | |
cea62c87 CC |
2401 | clk_writel(*ctx++, tegra_pll_a_out0.reg); |
2402 | clk_writel(*ctx++, tegra_pll_c_out1.reg); | |
2403 | ||
2404 | clk_writel(*ctx++, tegra_clk_cclk.reg); | |
2405 | clk_writel(*ctx++, tegra_clk_cclk.reg + SUPER_CLK_DIVIDER); | |
2406 | ||
2407 | clk_writel(*ctx++, tegra_clk_sclk.reg); | |
2408 | clk_writel(*ctx++, tegra_clk_sclk.reg + SUPER_CLK_DIVIDER); | |
2409 | clk_writel(*ctx++, tegra_clk_pclk.reg); | |
2410 | ||
c2f44a9d CC |
2411 | clk_writel(*ctx++, tegra_clk_audio.reg); |
2412 | ||
71fc84cc CC |
2413 | /* enable all clocks before configuring clock sources */ |
2414 | clk_writel(0xbffffff9ul, CLK_OUT_ENB); | |
2415 | clk_writel(0xfefffff7ul, CLK_OUT_ENB + 4); | |
2416 | clk_writel(0x77f01bfful, CLK_OUT_ENB + 8); | |
2417 | wmb(); | |
2418 | ||
2419 | for (off = PERIPH_CLK_SOURCE_I2S1; off <= PERIPH_CLK_SOURCE_OSC; | |
2420 | off += 4) { | |
2421 | if (off == PERIPH_CLK_SOURCE_EMC) | |
2422 | continue; | |
2423 | clk_writel(*ctx++, off); | |
2424 | } | |
2425 | wmb(); | |
2426 | ||
2427 | off = RST_DEVICES; | |
2428 | for (i = 0; i < RST_DEVICES_NUM; i++, off += 4) | |
2429 | clk_writel(*ctx++, off); | |
2430 | wmb(); | |
2431 | ||
2432 | off = CLK_OUT_ENB; | |
2433 | for (i = 0; i < CLK_OUT_ENB_NUM; i++, off += 4) | |
2434 | clk_writel(*ctx++, off); | |
2435 | wmb(); | |
2436 | ||
2437 | clk_writel(*ctx++, MISC_CLK_ENB); | |
2438 | clk_writel(*ctx++, CLK_MASK_ARM); | |
d8611961 | 2439 | } |
71fc84cc | 2440 | #endif |