[deliverable/linux.git] / arch / arm / mach-tegra / timer.c

/*
 * arch/arch/mach-tegra/timer.c
 *
 * Copyright (C) 2010 Google, Inc.
 *
 * Author:
 *	Colin Cross <ccross@google.com>
 *
 * This software is licensed under the terms of the GNU General Public
 * License version 2, as published by the Free Software Foundation, and
 * may be copied, distributed, and modified under those terms.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 */

#include <linux/init.h>
#include <linux/time.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/clockchips.h>
#include <linux/clocksource.h>
#include <linux/clk.h>
#include <linux/io.h>
#include <linux/cnt32_to_63.h>

#include <asm/mach/time.h>
#include <asm/localtimer.h>

#include <mach/iomap.h>
#include <mach/irqs.h>

#include "board.h"
#include "clock.h"

#define TIMERUS_CNTR_1US 0x10
#define TIMERUS_USEC_CFG 0x14
#define TIMERUS_CNTR_FREEZE 0x4c

#define TIMER1_BASE 0x0
#define TIMER2_BASE 0x8
#define TIMER3_BASE 0x50
#define TIMER4_BASE 0x58

#define TIMER_PTV 0x0
#define TIMER_PCR 0x4

struct tegra_timer;

static void __iomem *timer_reg_base = IO_ADDRESS(TEGRA_TMR1_BASE);

#define timer_writel(value, reg) \
	__raw_writel(value, (u32)timer_reg_base + (reg))
#define timer_readl(reg) \
	__raw_readl((u32)timer_reg_base + (reg))

static int tegra_timer_set_next_event(unsigned long cycles,
					 struct clock_event_device *evt)
{
	u32 reg;

	reg = 0x80000000 | ((cycles > 1) ? (cycles-1) : 0);
	timer_writel(reg, TIMER3_BASE + TIMER_PTV);

	return 0;
}

static void tegra_timer_set_mode(enum clock_event_mode mode,
				    struct clock_event_device *evt)
{
	u32 reg;

	timer_writel(0, TIMER3_BASE + TIMER_PTV);

	switch (mode) {
	case CLOCK_EVT_MODE_PERIODIC:
		reg = 0xC0000000 | ((1000000/HZ)-1);
		timer_writel(reg, TIMER3_BASE + TIMER_PTV);
		break;
	case CLOCK_EVT_MODE_ONESHOT:
		break;
	case CLOCK_EVT_MODE_UNUSED:
	case CLOCK_EVT_MODE_SHUTDOWN:
	case CLOCK_EVT_MODE_RESUME:
		break;
	}
}

static cycle_t tegra_clocksource_read(struct clocksource *cs)
{
	return cnt32_to_63(timer_readl(TIMERUS_CNTR_1US));
}

static struct clock_event_device tegra_clockevent = {
	.name		= "timer0",
	.rating		= 300,
	.features	= CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC,
	.set_next_event	= tegra_timer_set_next_event,
	.set_mode	= tegra_timer_set_mode,
};

static struct clocksource tegra_clocksource = {
	.name	= "timer_us",
	.rating	= 300,
	.read	= tegra_clocksource_read,
	.mask	= 0x7FFFFFFFFFFFFFFFULL,
	.flags	= CLOCK_SOURCE_IS_CONTINUOUS,
};

unsigned long long sched_clock(void)
{
	return clocksource_cyc2ns(tegra_clocksource.read(&tegra_clocksource),
		tegra_clocksource.mult, tegra_clocksource.shift);
}

static irqreturn_t tegra_timer_interrupt(int irq, void *dev_id)
{
	struct clock_event_device *evt = (struct clock_event_device *)dev_id;
	timer_writel(1<<30, TIMER3_BASE + TIMER_PCR);
	evt->event_handler(evt);
	return IRQ_HANDLED;
}

static struct irqaction tegra_timer_irq = {
	.name		= "timer0",
	.flags		= IRQF_DISABLED | IRQF_TIMER | IRQF_TRIGGER_HIGH,
	.handler	= tegra_timer_interrupt,
	.dev_id		= &tegra_clockevent,
	.irq		= INT_TMR3,
};

static void __init tegra_init_timer(void)
{
	unsigned long rate = clk_measure_input_freq();
	int ret;

#ifdef CONFIG_HAVE_ARM_TWD
	twd_base = IO_ADDRESS(TEGRA_ARM_PERIF_BASE + 0x600);
#endif

	switch (rate) {
	case 12000000:
		timer_writel(0x000b, TIMERUS_USEC_CFG);
		break;
	case 13000000:
		timer_writel(0x000c, TIMERUS_USEC_CFG);
		break;
	case 19200000:
		timer_writel(0x045f, TIMERUS_USEC_CFG);
		break;
	case 26000000:
		timer_writel(0x0019, TIMERUS_USEC_CFG);
		break;
	default:
		WARN(1, "Unknown clock rate");
	}

	if (clocksource_register_hz(&tegra_clocksource, 1000000)) {
		printk(KERN_ERR "Failed to register clocksource\n");
		BUG();
	}

	ret = setup_irq(tegra_timer_irq.irq, &tegra_timer_irq);
	if (ret) {
		printk(KERN_ERR "Failed to register timer IRQ: %d\n", ret);
		BUG();
	}

	clockevents_calc_mult_shift(&tegra_clockevent, 1000000, 5);
	tegra_clockevent.max_delta_ns =
		clockevent_delta2ns(0x1fffffff, &tegra_clockevent);
	tegra_clockevent.min_delta_ns =
		clockevent_delta2ns(0x1, &tegra_clockevent);
	tegra_clockevent.cpumask = cpu_all_mask;
	tegra_clockevent.irq = tegra_timer_irq.irq;
	clockevents_register_device(&tegra_clockevent);

	return;
}

struct sys_timer tegra_timer = {
	.init = tegra_init_timer,
};
Commit	Line	Data
2d5cd9a3 CC	1	/*
	2	* arch/arch/mach-tegra/timer.c
	3	*
	4	* Copyright (C) 2010 Google, Inc.
	5	*
	6	* Author:
	7	* Colin Cross <ccross@google.com>
	8	*
	9	* This software is licensed under the terms of the GNU General Public
	10	* License version 2, as published by the Free Software Foundation, and
	11	* may be copied, distributed, and modified under those terms.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	*/
	19
	20	#include <linux/init.h>
	21	#include <linux/time.h>
	22	#include <linux/interrupt.h>
	23	#include <linux/irq.h>
	24	#include <linux/clockchips.h>
	25	#include <linux/clocksource.h>
	26	#include <linux/clk.h>
	27	#include <linux/io.h>
	28	#include <linux/cnt32_to_63.h>
	29
2d5cd9a3 CC	30	#include <asm/mach/time.h>
	31	#include <asm/localtimer.h>
	32
	33	#include <mach/iomap.h>
	34	#include <mach/irqs.h>
	35
	36	#include "board.h"
	37	#include "clock.h"
	38
	39	#define TIMERUS_CNTR_1US 0x10
	40	#define TIMERUS_USEC_CFG 0x14
	41	#define TIMERUS_CNTR_FREEZE 0x4c
	42
	43	#define TIMER1_BASE 0x0
	44	#define TIMER2_BASE 0x8
	45	#define TIMER3_BASE 0x50
	46	#define TIMER4_BASE 0x58
	47
	48	#define TIMER_PTV 0x0
	49	#define TIMER_PCR 0x4
	50
	51	struct tegra_timer;
	52
	53	static void __iomem *timer_reg_base = IO_ADDRESS(TEGRA_TMR1_BASE);
	54
	55	#define timer_writel(value, reg) \
	56	__raw_writel(value, (u32)timer_reg_base + (reg))
	57	#define timer_readl(reg) \
	58	__raw_readl((u32)timer_reg_base + (reg))
	59
	60	static int tegra_timer_set_next_event(unsigned long cycles,
	61	struct clock_event_device *evt)
	62	{
	63	u32 reg;
	64
	65	reg = 0x80000000 \| ((cycles > 1) ? (cycles-1) : 0);
	66	timer_writel(reg, TIMER3_BASE + TIMER_PTV);
	67
	68	return 0;
	69	}
	70
	71	static void tegra_timer_set_mode(enum clock_event_mode mode,
	72	struct clock_event_device *evt)
	73	{
	74	u32 reg;
	75
	76	timer_writel(0, TIMER3_BASE + TIMER_PTV);
	77
	78	switch (mode) {
	79	case CLOCK_EVT_MODE_PERIODIC:
	80	reg = 0xC0000000 \| ((1000000/HZ)-1);
	81	timer_writel(reg, TIMER3_BASE + TIMER_PTV);
	82	break;
	83	case CLOCK_EVT_MODE_ONESHOT:
	84	break;
	85	case CLOCK_EVT_MODE_UNUSED:
	86	case CLOCK_EVT_MODE_SHUTDOWN:
	87	case CLOCK_EVT_MODE_RESUME:
	88	break;
	89	}
	90	}
	91
	92	static cycle_t tegra_clocksource_read(struct clocksource *cs)
	93	{
94	return cnt32_to_63(timer_readl(TIMERUS_CNTR_1US));
95	}
96
97	static struct clock_event_device tegra_clockevent = {
98	.name = "timer0",
99	.rating = 300,
100	.features = CLOCK_EVT_FEAT_ONESHOT \| CLOCK_EVT_FEAT_PERIODIC,
101	.set_next_event = tegra_timer_set_next_event,
102	.set_mode = tegra_timer_set_mode,
103	};
104
105	static struct clocksource tegra_clocksource = {
106	.name = "timer_us",
107	.rating = 300,
108	.read = tegra_clocksource_read,
109	.mask = 0x7FFFFFFFFFFFFFFFULL,
110	.flags = CLOCK_SOURCE_IS_CONTINUOUS,
111	};
112
113	unsigned long long sched_clock(void)
114	{
115	return clocksource_cyc2ns(tegra_clocksource.read(&tegra_clocksource),
116	tegra_clocksource.mult, tegra_clocksource.shift);
117	}
118
119	static irqreturn_t tegra_timer_interrupt(int irq, void *dev_id)
120	{
121	struct clock_event_device evt = (struct clock_event_device )dev_id;
122	timer_writel(1<<30, TIMER3_BASE + TIMER_PCR);
123	evt->event_handler(evt);
124	return IRQ_HANDLED;
125	}
126
127	static struct irqaction tegra_timer_irq = {
128	.name = "timer0",
129	.flags = IRQF_DISABLED \| IRQF_TIMER \| IRQF_TRIGGER_HIGH,
130	.handler = tegra_timer_interrupt,
131	.dev_id = &tegra_clockevent,
132	.irq = INT_TMR3,
133	};
134
135	static void __init tegra_init_timer(void)
136	{
137	unsigned long rate = clk_measure_input_freq();
138	int ret;
139
140	#ifdef CONFIG_HAVE_ARM_TWD
141	twd_base = IO_ADDRESS(TEGRA_ARM_PERIF_BASE + 0x600);
142	#endif
143
144	switch (rate) {
145	case 12000000:
146	timer_writel(0x000b, TIMERUS_USEC_CFG);
147	break;
148	case 13000000:
149	timer_writel(0x000c, TIMERUS_USEC_CFG);
150	break;
151	case 19200000:
152	timer_writel(0x045f, TIMERUS_USEC_CFG);
153	break;
154	case 26000000:
155	timer_writel(0x0019, TIMERUS_USEC_CFG);
156	break;
157	default:
158	WARN(1, "Unknown clock rate");
159	}
160
161	if (clocksource_register_hz(&tegra_clocksource, 1000000)) {
162	printk(KERN_ERR "Failed to register clocksource\n");
163	BUG();
164	}
165
166	ret = setup_irq(tegra_timer_irq.irq, &tegra_timer_irq);
167	if (ret) {
168	printk(KERN_ERR "Failed to register timer IRQ: %d\n", ret);
169	BUG();
170	}
171
172	clockevents_calc_mult_shift(&tegra_clockevent, 1000000, 5);
173	tegra_clockevent.max_delta_ns =
174	clockevent_delta2ns(0x1fffffff, &tegra_clockevent);
175	tegra_clockevent.min_delta_ns =
176	clockevent_delta2ns(0x1, &tegra_clockevent);
177	tegra_clockevent.cpumask = cpu_all_mask;
178	tegra_clockevent.irq = tegra_timer_irq.irq;
179	clockevents_register_device(&tegra_clockevent);
180
181	return;
182	}
183
184	struct sys_timer tegra_timer = {
185	.init = tegra_init_timer,
186	};