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1 | /* |
2 | * arch/arch/mach-tegra/timer.c | |
3 | * | |
4 | * Copyright (C) 2010 Google, Inc. | |
5 | * | |
6 | * Author: | |
7 | * Colin Cross <ccross@google.com> | |
8 | * | |
9 | * This software is licensed under the terms of the GNU General Public | |
10 | * License version 2, as published by the Free Software Foundation, and | |
11 | * may be copied, distributed, and modified under those terms. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | */ | |
19 | ||
20 | #include <linux/init.h> | |
62248ae8 | 21 | #include <linux/err.h> |
5e06b649 | 22 | #include <linux/sched.h> |
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23 | #include <linux/time.h> |
24 | #include <linux/interrupt.h> | |
25 | #include <linux/irq.h> | |
26 | #include <linux/clockchips.h> | |
27 | #include <linux/clocksource.h> | |
28 | #include <linux/clk.h> | |
29 | #include <linux/io.h> | |
2d5cd9a3 | 30 | |
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31 | #include <asm/mach/time.h> |
32 | #include <asm/localtimer.h> | |
e3f4c0ab | 33 | #include <asm/sched_clock.h> |
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34 | |
35 | #include <mach/iomap.h> | |
36 | #include <mach/irqs.h> | |
2ea67fd1 | 37 | #include <mach/suspend.h> |
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38 | |
39 | #include "board.h" | |
40 | #include "clock.h" | |
41 | ||
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42 | #define RTC_SECONDS 0x08 |
43 | #define RTC_SHADOW_SECONDS 0x0c | |
44 | #define RTC_MILLISECONDS 0x10 | |
45 | ||
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46 | #define TIMERUS_CNTR_1US 0x10 |
47 | #define TIMERUS_USEC_CFG 0x14 | |
48 | #define TIMERUS_CNTR_FREEZE 0x4c | |
49 | ||
50 | #define TIMER1_BASE 0x0 | |
51 | #define TIMER2_BASE 0x8 | |
52 | #define TIMER3_BASE 0x50 | |
53 | #define TIMER4_BASE 0x58 | |
54 | ||
55 | #define TIMER_PTV 0x0 | |
56 | #define TIMER_PCR 0x4 | |
57 | ||
2d5cd9a3 | 58 | static void __iomem *timer_reg_base = IO_ADDRESS(TEGRA_TMR1_BASE); |
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59 | static void __iomem *rtc_base = IO_ADDRESS(TEGRA_RTC_BASE); |
60 | ||
61 | static struct timespec persistent_ts; | |
62 | static u64 persistent_ms, last_persistent_ms; | |
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63 | |
64 | #define timer_writel(value, reg) \ | |
75d71166 | 65 | __raw_writel(value, timer_reg_base + (reg)) |
2d5cd9a3 | 66 | #define timer_readl(reg) \ |
75d71166 | 67 | __raw_readl(timer_reg_base + (reg)) |
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68 | |
69 | static int tegra_timer_set_next_event(unsigned long cycles, | |
70 | struct clock_event_device *evt) | |
71 | { | |
72 | u32 reg; | |
73 | ||
74 | reg = 0x80000000 | ((cycles > 1) ? (cycles-1) : 0); | |
75 | timer_writel(reg, TIMER3_BASE + TIMER_PTV); | |
76 | ||
77 | return 0; | |
78 | } | |
79 | ||
80 | static void tegra_timer_set_mode(enum clock_event_mode mode, | |
81 | struct clock_event_device *evt) | |
82 | { | |
83 | u32 reg; | |
84 | ||
85 | timer_writel(0, TIMER3_BASE + TIMER_PTV); | |
86 | ||
87 | switch (mode) { | |
88 | case CLOCK_EVT_MODE_PERIODIC: | |
89 | reg = 0xC0000000 | ((1000000/HZ)-1); | |
90 | timer_writel(reg, TIMER3_BASE + TIMER_PTV); | |
91 | break; | |
92 | case CLOCK_EVT_MODE_ONESHOT: | |
93 | break; | |
94 | case CLOCK_EVT_MODE_UNUSED: | |
95 | case CLOCK_EVT_MODE_SHUTDOWN: | |
96 | case CLOCK_EVT_MODE_RESUME: | |
97 | break; | |
98 | } | |
99 | } | |
100 | ||
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101 | static struct clock_event_device tegra_clockevent = { |
102 | .name = "timer0", | |
103 | .rating = 300, | |
104 | .features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC, | |
105 | .set_next_event = tegra_timer_set_next_event, | |
106 | .set_mode = tegra_timer_set_mode, | |
107 | }; | |
108 | ||
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109 | static DEFINE_CLOCK_DATA(cd); |
110 | ||
111 | /* | |
112 | * Constants generated by clocks_calc_mult_shift(m, s, 1MHz, NSEC_PER_SEC, 60). | |
113 | * This gives a resolution of about 1us and a wrap period of about 1h11min. | |
114 | */ | |
115 | #define SC_MULT 4194304000u | |
116 | #define SC_SHIFT 22 | |
117 | ||
5e06b649 | 118 | unsigned long long notrace sched_clock(void) |
2d5cd9a3 | 119 | { |
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120 | u32 cyc = timer_readl(TIMERUS_CNTR_1US); |
121 | return cyc_to_fixed_sched_clock(&cd, cyc, (u32)~0, SC_MULT, SC_SHIFT); | |
122 | } | |
123 | ||
124 | static void notrace tegra_update_sched_clock(void) | |
125 | { | |
126 | u32 cyc = timer_readl(TIMERUS_CNTR_1US); | |
127 | update_sched_clock(&cd, cyc, (u32)~0); | |
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128 | } |
129 | ||
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130 | /* |
131 | * tegra_rtc_read - Reads the Tegra RTC registers | |
132 | * Care must be taken that this funciton is not called while the | |
133 | * tegra_rtc driver could be executing to avoid race conditions | |
134 | * on the RTC shadow register | |
135 | */ | |
136 | u64 tegra_rtc_read_ms(void) | |
137 | { | |
138 | u32 ms = readl(rtc_base + RTC_MILLISECONDS); | |
139 | u32 s = readl(rtc_base + RTC_SHADOW_SECONDS); | |
140 | return (u64)s * MSEC_PER_SEC + ms; | |
141 | } | |
142 | ||
143 | /* | |
144 | * read_persistent_clock - Return time from a persistent clock. | |
145 | * | |
146 | * Reads the time from a source which isn't disabled during PM, the | |
147 | * 32k sync timer. Convert the cycles elapsed since last read into | |
148 | * nsecs and adds to a monotonically increasing timespec. | |
149 | * Care must be taken that this funciton is not called while the | |
150 | * tegra_rtc driver could be executing to avoid race conditions | |
151 | * on the RTC shadow register | |
152 | */ | |
153 | void read_persistent_clock(struct timespec *ts) | |
154 | { | |
155 | u64 delta; | |
156 | struct timespec *tsp = &persistent_ts; | |
157 | ||
158 | last_persistent_ms = persistent_ms; | |
159 | persistent_ms = tegra_rtc_read_ms(); | |
160 | delta = persistent_ms - last_persistent_ms; | |
161 | ||
162 | timespec_add_ns(tsp, delta * NSEC_PER_MSEC); | |
163 | *ts = *tsp; | |
164 | } | |
165 | ||
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166 | static irqreturn_t tegra_timer_interrupt(int irq, void *dev_id) |
167 | { | |
168 | struct clock_event_device *evt = (struct clock_event_device *)dev_id; | |
169 | timer_writel(1<<30, TIMER3_BASE + TIMER_PCR); | |
170 | evt->event_handler(evt); | |
171 | return IRQ_HANDLED; | |
172 | } | |
173 | ||
174 | static struct irqaction tegra_timer_irq = { | |
175 | .name = "timer0", | |
176 | .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_TRIGGER_HIGH, | |
177 | .handler = tegra_timer_interrupt, | |
178 | .dev_id = &tegra_clockevent, | |
179 | .irq = INT_TMR3, | |
180 | }; | |
181 | ||
182 | static void __init tegra_init_timer(void) | |
183 | { | |
62248ae8 | 184 | struct clk *clk; |
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185 | unsigned long rate = clk_measure_input_freq(); |
186 | int ret; | |
187 | ||
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188 | clk = clk_get_sys("timer", NULL); |
189 | BUG_ON(IS_ERR(clk)); | |
190 | clk_enable(clk); | |
191 | ||
192 | /* | |
193 | * rtc registers are used by read_persistent_clock, keep the rtc clock | |
194 | * enabled | |
195 | */ | |
196 | clk = clk_get_sys("rtc-tegra", NULL); | |
197 | BUG_ON(IS_ERR(clk)); | |
198 | clk_enable(clk); | |
199 | ||
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200 | #ifdef CONFIG_HAVE_ARM_TWD |
201 | twd_base = IO_ADDRESS(TEGRA_ARM_PERIF_BASE + 0x600); | |
202 | #endif | |
203 | ||
204 | switch (rate) { | |
205 | case 12000000: | |
206 | timer_writel(0x000b, TIMERUS_USEC_CFG); | |
207 | break; | |
208 | case 13000000: | |
209 | timer_writel(0x000c, TIMERUS_USEC_CFG); | |
210 | break; | |
211 | case 19200000: | |
212 | timer_writel(0x045f, TIMERUS_USEC_CFG); | |
213 | break; | |
214 | case 26000000: | |
215 | timer_writel(0x0019, TIMERUS_USEC_CFG); | |
216 | break; | |
217 | default: | |
218 | WARN(1, "Unknown clock rate"); | |
219 | } | |
220 | ||
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221 | init_fixed_sched_clock(&cd, tegra_update_sched_clock, 32, |
222 | 1000000, SC_MULT, SC_SHIFT); | |
223 | ||
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224 | if (clocksource_mmio_init(timer_reg_base + TIMERUS_CNTR_1US, |
225 | "timer_us", 1000000, 300, 32, clocksource_mmio_readl_up)) { | |
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226 | printk(KERN_ERR "Failed to register clocksource\n"); |
227 | BUG(); | |
228 | } | |
229 | ||
230 | ret = setup_irq(tegra_timer_irq.irq, &tegra_timer_irq); | |
231 | if (ret) { | |
232 | printk(KERN_ERR "Failed to register timer IRQ: %d\n", ret); | |
233 | BUG(); | |
234 | } | |
235 | ||
236 | clockevents_calc_mult_shift(&tegra_clockevent, 1000000, 5); | |
237 | tegra_clockevent.max_delta_ns = | |
238 | clockevent_delta2ns(0x1fffffff, &tegra_clockevent); | |
239 | tegra_clockevent.min_delta_ns = | |
240 | clockevent_delta2ns(0x1, &tegra_clockevent); | |
241 | tegra_clockevent.cpumask = cpu_all_mask; | |
242 | tegra_clockevent.irq = tegra_timer_irq.irq; | |
243 | clockevents_register_device(&tegra_clockevent); | |
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244 | } |
245 | ||
246 | struct sys_timer tegra_timer = { | |
247 | .init = tegra_init_timer, | |
248 | }; | |
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249 | |
250 | #ifdef CONFIG_PM | |
251 | static u32 usec_config; | |
252 | ||
253 | void tegra_timer_suspend(void) | |
254 | { | |
255 | usec_config = timer_readl(TIMERUS_USEC_CFG); | |
256 | } | |
257 | ||
258 | void tegra_timer_resume(void) | |
259 | { | |
260 | timer_writel(usec_config, TIMERUS_USEC_CFG); | |
261 | } | |
262 | #endif |