[deliverable/linux.git] / arch / arm / mach-ux500 / board-mop500-sdi.c

/*
 * Copyright (C) ST-Ericsson SA 2010
 *
 * Author: Hanumath Prasad <hanumath.prasad@stericsson.com>
 * License terms: GNU General Public License (GPL) version 2
 */

#include <linux/kernel.h>
#include <linux/gpio.h>
#include <linux/amba/bus.h>
#include <linux/amba/mmci.h>
#include <linux/mmc/host.h>
#include <linux/platform_device.h>
#include <linux/platform_data/dma-ste-dma40.h>

#include <asm/mach-types.h>
#include "devices.h"

#include "db8500-regs.h"
#include "devices-db8500.h"
#include "board-mop500.h"
#include "ste-dma40-db8500.h"

/*
 * v2 has a new version of this block that need to be forced, the number found
 * in hardware is incorrect
 */
#define U8500_SDI_V2_PERIPHID 0x10480180

/*
 * SDI 0 (MicroSD slot)
 */

#ifdef CONFIG_STE_DMA40
struct stedma40_chan_cfg mop500_sdi0_dma_cfg_rx = {
	.mode = STEDMA40_MODE_LOGICAL,
	.dir = DMA_DEV_TO_MEM,
	.dev_type = DB8500_DMA_DEV29_SD_MM0,
};

static struct stedma40_chan_cfg mop500_sdi0_dma_cfg_tx = {
	.mode = STEDMA40_MODE_LOGICAL,
	.dir = DMA_MEM_TO_DEV,
	.dev_type = DB8500_DMA_DEV29_SD_MM0,
};
#endif

struct mmci_platform_data mop500_sdi0_data = {
	.f_max		= 100000000,
	.capabilities	= MMC_CAP_4_BIT_DATA |
				MMC_CAP_SD_HIGHSPEED |
				MMC_CAP_MMC_HIGHSPEED |
				MMC_CAP_ERASE |
				MMC_CAP_UHS_SDR12 |
				MMC_CAP_UHS_SDR25,
	.gpio_wp	= -1,
	.sigdir		= MCI_ST_FBCLKEN |
				MCI_ST_CMDDIREN |
				MCI_ST_DATA0DIREN |
				MCI_ST_DATA2DIREN,
#ifdef CONFIG_STE_DMA40
	.dma_filter	= stedma40_filter,
	.dma_rx_param	= &mop500_sdi0_dma_cfg_rx,
	.dma_tx_param	= &mop500_sdi0_dma_cfg_tx,
#endif
};

/*
 * SDI1 (SDIO WLAN)
 */
#ifdef CONFIG_STE_DMA40
static struct stedma40_chan_cfg sdi1_dma_cfg_rx = {
	.mode = STEDMA40_MODE_LOGICAL,
	.dir = DMA_DEV_TO_MEM,
	.dev_type = DB8500_DMA_DEV32_SD_MM1,
};

static struct stedma40_chan_cfg sdi1_dma_cfg_tx = {
	.mode = STEDMA40_MODE_LOGICAL,
	.dir = DMA_MEM_TO_DEV,
	.dev_type = DB8500_DMA_DEV32_SD_MM1,
};
#endif

struct mmci_platform_data mop500_sdi1_data = {
	.ocr_mask	= MMC_VDD_29_30,
	.f_max		= 100000000,
	.capabilities	= MMC_CAP_4_BIT_DATA |
				MMC_CAP_NONREMOVABLE,
	.gpio_cd	= -1,
	.gpio_wp	= -1,
#ifdef CONFIG_STE_DMA40
	.dma_filter	= stedma40_filter,
	.dma_rx_param	= &sdi1_dma_cfg_rx,
	.dma_tx_param	= &sdi1_dma_cfg_tx,
#endif
};

/*
 * SDI 2 (POP eMMC, not on DB8500ed)
 */

#ifdef CONFIG_STE_DMA40
struct stedma40_chan_cfg mop500_sdi2_dma_cfg_rx = {
	.mode = STEDMA40_MODE_LOGICAL,
	.dir = DMA_DEV_TO_MEM,
	.dev_type =  DB8500_DMA_DEV28_SD_MM2,
};

static struct stedma40_chan_cfg mop500_sdi2_dma_cfg_tx = {
	.mode = STEDMA40_MODE_LOGICAL,
	.dir = DMA_MEM_TO_DEV,
	.dev_type = DB8500_DMA_DEV28_SD_MM2,
};
#endif

struct mmci_platform_data mop500_sdi2_data = {
	.ocr_mask	= MMC_VDD_165_195,
	.f_max		= 100000000,
	.capabilities	= MMC_CAP_4_BIT_DATA |
				MMC_CAP_8_BIT_DATA |
				MMC_CAP_NONREMOVABLE |
				MMC_CAP_MMC_HIGHSPEED |
				MMC_CAP_ERASE |
				MMC_CAP_CMD23,
	.gpio_cd	= -1,
	.gpio_wp	= -1,
#ifdef CONFIG_STE_DMA40
	.dma_filter	= stedma40_filter,
	.dma_rx_param	= &mop500_sdi2_dma_cfg_rx,
	.dma_tx_param	= &mop500_sdi2_dma_cfg_tx,
#endif
};

/*
 * SDI 4 (on-board eMMC)
 */

#ifdef CONFIG_STE_DMA40
struct stedma40_chan_cfg mop500_sdi4_dma_cfg_rx = {
	.mode = STEDMA40_MODE_LOGICAL,
	.dir = DMA_DEV_TO_MEM,
	.dev_type =  DB8500_DMA_DEV42_SD_MM4,
};

static struct stedma40_chan_cfg mop500_sdi4_dma_cfg_tx = {
	.mode = STEDMA40_MODE_LOGICAL,
	.dir = DMA_MEM_TO_DEV,
	.dev_type = DB8500_DMA_DEV42_SD_MM4,
};
#endif

struct mmci_platform_data mop500_sdi4_data = {
	.f_max		= 100000000,
	.capabilities	= MMC_CAP_4_BIT_DATA |
				MMC_CAP_8_BIT_DATA |
				MMC_CAP_NONREMOVABLE |
				MMC_CAP_MMC_HIGHSPEED |
				MMC_CAP_ERASE |
				MMC_CAP_CMD23,
	.gpio_cd	= -1,
	.gpio_wp	= -1,
#ifdef CONFIG_STE_DMA40
	.dma_filter	= stedma40_filter,
	.dma_rx_param	= &mop500_sdi4_dma_cfg_rx,
	.dma_tx_param	= &mop500_sdi4_dma_cfg_tx,
#endif
};
Commit	Line	Data
008f8a2f HP	1	/*
	2	* Copyright (C) ST-Ericsson SA 2010
	3	*
	4	* Author: Hanumath Prasad <hanumath.prasad@stericsson.com>
	5	* License terms: GNU General Public License (GPL) version 2
	6	*/
	7
	8	#include <linux/kernel.h>
	9	#include <linux/gpio.h>
	10	#include <linux/amba/bus.h>
	11	#include <linux/amba/mmci.h>
	12	#include <linux/mmc/host.h>
	13	#include <linux/platform_device.h>
865fab60	14	#include <linux/platform_data/dma-ste-dma40.h>
008f8a2f	15
4b4f757c	16	#include <asm/mach-types.h>
e657bcf6	17	#include "devices.h"
008f8a2f	18
174e7796	19	#include "db8500-regs.h"
fbf1eadf	20	#include "devices-db8500.h"
008f8a2f	21	#include "board-mop500.h"
5d7b8467	22	#include "ste-dma40-db8500.h"
008f8a2f	23
c15def1c LW	24	/*
	25	* v2 has a new version of this block that need to be forced, the number found
	26	* in hardware is incorrect
	27	*/
	28	#define U8500_SDI_V2_PERIPHID 0x10480180
	29
b8410a15 RV	30	/*
	31	* SDI 0 (MicroSD slot)
	32	*/
	33
5d7b8467 LW	34	#ifdef CONFIG_STE_DMA40
	35	struct stedma40_chan_cfg mop500_sdi0_dma_cfg_rx = {
	36	.mode = STEDMA40_MODE_LOGICAL,
98b68ab5	37	.dir = DMA_DEV_TO_MEM,
26955c07	38	.dev_type = DB8500_DMA_DEV29_SD_MM0,
5d7b8467 LW	39	};
	40
	41	static struct stedma40_chan_cfg mop500_sdi0_dma_cfg_tx = {
	42	.mode = STEDMA40_MODE_LOGICAL,
98b68ab5	43	.dir = DMA_MEM_TO_DEV,
26955c07	44	.dev_type = DB8500_DMA_DEV29_SD_MM0,
5d7b8467 LW	45	};
	46	#endif
	47
5e1ac7db	48	struct mmci_platform_data mop500_sdi0_data = {
b6ff56a4	49	.f_max = 100000000,
02a73437 LW	50	.capabilities = MMC_CAP_4_BIT_DATA \|
02a73437 LW	51	MMC_CAP_SD_HIGHSPEED \|
fd1cc1b9	52	MMC_CAP_MMC_HIGHSPEED \|
714c0b00 UH	53	MMC_CAP_ERASE \|
	54	MMC_CAP_UHS_SDR12 \|
	55	MMC_CAP_UHS_SDR25,
b8410a15	56	.gpio_wp = -1,
bc521818 UH	57	.sigdir = MCI_ST_FBCLKEN \|
	58	MCI_ST_CMDDIREN \|
	59	MCI_ST_DATA0DIREN \|
	60	MCI_ST_DATA2DIREN,
5d7b8467 LW	61	#ifdef CONFIG_STE_DMA40
	62	.dma_filter = stedma40_filter,
	63	.dma_rx_param = &mop500_sdi0_dma_cfg_rx,
	64	.dma_tx_param = &mop500_sdi0_dma_cfg_tx,
	65	#endif
b8410a15 RV	66	};
b8410a15 RV	67
76d6717b SNX	68	/*
	69	* SDI1 (SDIO WLAN)
	70	*/
	71	#ifdef CONFIG_STE_DMA40
	72	static struct stedma40_chan_cfg sdi1_dma_cfg_rx = {
	73	.mode = STEDMA40_MODE_LOGICAL,
98b68ab5	74	.dir = DMA_DEV_TO_MEM,
26955c07	75	.dev_type = DB8500_DMA_DEV32_SD_MM1,
76d6717b SNX	76	};
	77
	78	static struct stedma40_chan_cfg sdi1_dma_cfg_tx = {
	79	.mode = STEDMA40_MODE_LOGICAL,
98b68ab5	80	.dir = DMA_MEM_TO_DEV,
26955c07	81	.dev_type = DB8500_DMA_DEV32_SD_MM1,
76d6717b SNX	82	};
	83	#endif
	84
9cf24b15	85	struct mmci_platform_data mop500_sdi1_data = {
76d6717b	86	.ocr_mask = MMC_VDD_29_30,
b6ff56a4	87	.f_max = 100000000,
a7de8b30 UH	88	.capabilities = MMC_CAP_4_BIT_DATA \|
a7de8b30 UH	89	MMC_CAP_NONREMOVABLE,
76d6717b SNX	90	.gpio_cd = -1,
	91	.gpio_wp = -1,
	92	#ifdef CONFIG_STE_DMA40
	93	.dma_filter = stedma40_filter,
	94	.dma_rx_param = &sdi1_dma_cfg_rx,
	95	.dma_tx_param = &sdi1_dma_cfg_tx,
	96	#endif
	97	};
	98
008f8a2f HP	99	/*
	100	* SDI 2 (POP eMMC, not on DB8500ed)
	101	*/
	102
5d7b8467 LW	103	#ifdef CONFIG_STE_DMA40
	104	struct stedma40_chan_cfg mop500_sdi2_dma_cfg_rx = {
	105	.mode = STEDMA40_MODE_LOGICAL,
98b68ab5	106	.dir = DMA_DEV_TO_MEM,
26955c07	107	.dev_type = DB8500_DMA_DEV28_SD_MM2,
5d7b8467 LW	108	};
	109
	110	static struct stedma40_chan_cfg mop500_sdi2_dma_cfg_tx = {
	111	.mode = STEDMA40_MODE_LOGICAL,
98b68ab5	112	.dir = DMA_MEM_TO_DEV,
26955c07	113	.dev_type = DB8500_DMA_DEV28_SD_MM2,
5d7b8467 LW	114	};
	115	#endif
	116
9cf24b15	117	struct mmci_platform_data mop500_sdi2_data = {
008f8a2f	118	.ocr_mask = MMC_VDD_165_195,
b6ff56a4	119	.f_max = 100000000,
a2be776d UH	120	.capabilities = MMC_CAP_4_BIT_DATA \|
a2be776d UH	121	MMC_CAP_8_BIT_DATA \|
a7de8b30	122	MMC_CAP_NONREMOVABLE \|
a2be776d	123	MMC_CAP_MMC_HIGHSPEED \|
fd1cc1b9	124	MMC_CAP_ERASE \|
a2be776d	125	MMC_CAP_CMD23,
008f8a2f HP	126	.gpio_cd = -1,
008f8a2f HP	127	.gpio_wp = -1,
5d7b8467 LW	128	#ifdef CONFIG_STE_DMA40
	129	.dma_filter = stedma40_filter,
	130	.dma_rx_param = &mop500_sdi2_dma_cfg_rx,
	131	.dma_tx_param = &mop500_sdi2_dma_cfg_tx,
	132	#endif
008f8a2f HP	133	};
	134
	135	/*
	136	* SDI 4 (on-board eMMC)
	137	*/
	138
5d7b8467 LW	139	#ifdef CONFIG_STE_DMA40
	140	struct stedma40_chan_cfg mop500_sdi4_dma_cfg_rx = {
	141	.mode = STEDMA40_MODE_LOGICAL,
98b68ab5	142	.dir = DMA_DEV_TO_MEM,
26955c07	143	.dev_type = DB8500_DMA_DEV42_SD_MM4,
5d7b8467 LW	144	};
	145
	146	static struct stedma40_chan_cfg mop500_sdi4_dma_cfg_tx = {
	147	.mode = STEDMA40_MODE_LOGICAL,
98b68ab5	148	.dir = DMA_MEM_TO_DEV,
26955c07	149	.dev_type = DB8500_DMA_DEV42_SD_MM4,
5d7b8467 LW	150	};
	151	#endif
	152
5e1ac7db	153	struct mmci_platform_data mop500_sdi4_data = {
b6ff56a4	154	.f_max = 100000000,
a2be776d UH	155	.capabilities = MMC_CAP_4_BIT_DATA \|
a2be776d UH	156	MMC_CAP_8_BIT_DATA \|
a7de8b30	157	MMC_CAP_NONREMOVABLE \|
a2be776d	158	MMC_CAP_MMC_HIGHSPEED \|
fd1cc1b9	159	MMC_CAP_ERASE \|
a2be776d	160	MMC_CAP_CMD23,
008f8a2f HP	161	.gpio_cd = -1,
008f8a2f HP	162	.gpio_wp = -1,
5d7b8467 LW	163	#ifdef CONFIG_STE_DMA40
	164	.dma_filter = stedma40_filter,
	165	.dma_rx_param = &mop500_sdi4_dma_cfg_rx,
	166	.dma_tx_param = &mop500_sdi4_dma_cfg_tx,
	167	#endif
008f8a2f	168	};