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c6b503ca SK |
1 | /* |
2 | * Copyright (C) 2009 ST-Ericsson | |
1df20afc | 3 | * Copyright (C) 2009 STMicroelectronics |
c6b503ca SK |
4 | * |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License version 2 as | |
7 | * published by the Free Software Foundation. | |
8 | */ | |
9 | #include <linux/module.h> | |
10 | #include <linux/kernel.h> | |
11 | #include <linux/list.h> | |
12 | #include <linux/errno.h> | |
13 | #include <linux/err.h> | |
14 | #include <linux/clk.h> | |
1df20afc | 15 | #include <linux/io.h> |
c6b503ca SK |
16 | |
17 | #include <asm/clkdev.h> | |
18 | ||
ba327b1e | 19 | #include <plat/mtu.h> |
1df20afc RV |
20 | #include <mach/hardware.h> |
21 | #include "clock.h" | |
22 | ||
23 | #define PRCC_PCKEN 0x00 | |
24 | #define PRCC_PCKDIS 0x04 | |
25 | #define PRCC_KCKEN 0x08 | |
26 | #define PRCC_KCKDIS 0x0C | |
27 | ||
28 | #define PRCM_YYCLKEN0_MGT_SET 0x510 | |
29 | #define PRCM_YYCLKEN1_MGT_SET 0x514 | |
30 | #define PRCM_YYCLKEN0_MGT_CLR 0x518 | |
31 | #define PRCM_YYCLKEN1_MGT_CLR 0x51C | |
32 | #define PRCM_YYCLKEN0_MGT_VAL 0x520 | |
33 | #define PRCM_YYCLKEN1_MGT_VAL 0x524 | |
34 | ||
35 | #define PRCM_SVAMMDSPCLK_MGT 0x008 | |
36 | #define PRCM_SIAMMDSPCLK_MGT 0x00C | |
37 | #define PRCM_SGACLK_MGT 0x014 | |
38 | #define PRCM_UARTCLK_MGT 0x018 | |
39 | #define PRCM_MSP02CLK_MGT 0x01C | |
40 | #define PRCM_MSP1CLK_MGT 0x288 | |
41 | #define PRCM_I2CCLK_MGT 0x020 | |
42 | #define PRCM_SDMMCCLK_MGT 0x024 | |
43 | #define PRCM_SLIMCLK_MGT 0x028 | |
44 | #define PRCM_PER1CLK_MGT 0x02C | |
45 | #define PRCM_PER2CLK_MGT 0x030 | |
46 | #define PRCM_PER3CLK_MGT 0x034 | |
47 | #define PRCM_PER5CLK_MGT 0x038 | |
48 | #define PRCM_PER6CLK_MGT 0x03C | |
49 | #define PRCM_PER7CLK_MGT 0x040 | |
50 | #define PRCM_LCDCLK_MGT 0x044 | |
51 | #define PRCM_BMLCLK_MGT 0x04C | |
52 | #define PRCM_HSITXCLK_MGT 0x050 | |
53 | #define PRCM_HSIRXCLK_MGT 0x054 | |
54 | #define PRCM_HDMICLK_MGT 0x058 | |
55 | #define PRCM_APEATCLK_MGT 0x05C | |
56 | #define PRCM_APETRACECLK_MGT 0x060 | |
57 | #define PRCM_MCDECLK_MGT 0x064 | |
58 | #define PRCM_IPI2CCLK_MGT 0x068 | |
59 | #define PRCM_DSIALTCLK_MGT 0x06C | |
60 | #define PRCM_DMACLK_MGT 0x074 | |
61 | #define PRCM_B2R2CLK_MGT 0x078 | |
62 | #define PRCM_TVCLK_MGT 0x07C | |
ba327b1e LW |
63 | #define PRCM_TCR 0x1C8 |
64 | #define PRCM_TCR_STOPPED (1 << 16) | |
65 | #define PRCM_TCR_DOZE_MODE (1 << 17) | |
1df20afc RV |
66 | #define PRCM_UNIPROCLK_MGT 0x278 |
67 | #define PRCM_SSPCLK_MGT 0x280 | |
68 | #define PRCM_RNGCLK_MGT 0x284 | |
69 | #define PRCM_UICCCLK_MGT 0x27C | |
70 | ||
71 | #define PRCM_MGT_ENABLE (1 << 8) | |
72 | ||
73 | static DEFINE_SPINLOCK(clocks_lock); | |
74 | ||
75 | static void __clk_enable(struct clk *clk) | |
76 | { | |
77 | if (clk->enabled++ == 0) { | |
78 | if (clk->parent_cluster) | |
79 | __clk_enable(clk->parent_cluster); | |
80 | ||
81 | if (clk->parent_periph) | |
82 | __clk_enable(clk->parent_periph); | |
83 | ||
84 | if (clk->ops && clk->ops->enable) | |
85 | clk->ops->enable(clk); | |
86 | } | |
87 | } | |
c6b503ca SK |
88 | |
89 | int clk_enable(struct clk *clk) | |
90 | { | |
1df20afc RV |
91 | unsigned long flags; |
92 | ||
93 | spin_lock_irqsave(&clocks_lock, flags); | |
94 | __clk_enable(clk); | |
95 | spin_unlock_irqrestore(&clocks_lock, flags); | |
96 | ||
c6b503ca SK |
97 | return 0; |
98 | } | |
99 | EXPORT_SYMBOL(clk_enable); | |
100 | ||
1df20afc RV |
101 | static void __clk_disable(struct clk *clk) |
102 | { | |
103 | if (--clk->enabled == 0) { | |
104 | if (clk->ops && clk->ops->disable) | |
105 | clk->ops->disable(clk); | |
106 | ||
107 | if (clk->parent_periph) | |
108 | __clk_disable(clk->parent_periph); | |
109 | ||
110 | if (clk->parent_cluster) | |
111 | __clk_disable(clk->parent_cluster); | |
112 | } | |
113 | } | |
114 | ||
c6b503ca SK |
115 | void clk_disable(struct clk *clk) |
116 | { | |
1df20afc RV |
117 | unsigned long flags; |
118 | ||
119 | WARN_ON(!clk->enabled); | |
120 | ||
121 | spin_lock_irqsave(&clocks_lock, flags); | |
122 | __clk_disable(clk); | |
123 | spin_unlock_irqrestore(&clocks_lock, flags); | |
c6b503ca SK |
124 | } |
125 | EXPORT_SYMBOL(clk_disable); | |
126 | ||
ba327b1e LW |
127 | /* |
128 | * The MTU has a separate, rather complex muxing setup | |
129 | * with alternative parents (peripheral cluster or | |
130 | * ULP or fixed 32768 Hz) depending on settings | |
131 | */ | |
132 | static unsigned long clk_mtu_get_rate(struct clk *clk) | |
133 | { | |
134 | void __iomem *addr = __io_address(U8500_PRCMU_BASE) | |
135 | + PRCM_TCR; | |
136 | u32 tcr = readl(addr); | |
137 | int mtu = (int) clk->data; | |
138 | /* | |
139 | * One of these is selected eventually | |
140 | * TODO: Replace the constant with a reference | |
141 | * to the ULP source once this is modeled. | |
142 | */ | |
143 | unsigned long clk32k = 32768; | |
144 | unsigned long mturate; | |
145 | unsigned long retclk; | |
146 | ||
147 | /* Get the rate from the parent as a default */ | |
148 | if (clk->parent_periph) | |
149 | mturate = clk_get_rate(clk->parent_periph); | |
150 | else if (clk->parent_cluster) | |
151 | mturate = clk_get_rate(clk->parent_cluster); | |
152 | else | |
153 | /* We need to be connected SOMEWHERE */ | |
154 | BUG(); | |
155 | ||
156 | /* | |
157 | * Are we in doze mode? | |
158 | * In this mode the parent peripheral or the fixed 32768 Hz | |
159 | * clock is fed into the block. | |
160 | */ | |
161 | if (!(tcr & PRCM_TCR_DOZE_MODE)) { | |
162 | /* | |
163 | * Here we're using the clock input from the APE ULP | |
164 | * clock domain. But first: are the timers stopped? | |
165 | */ | |
166 | if (tcr & PRCM_TCR_STOPPED) { | |
167 | clk32k = 0; | |
168 | mturate = 0; | |
169 | } else { | |
170 | /* Else default mode: 0 and 2.4 MHz */ | |
171 | clk32k = 0; | |
172 | if (cpu_is_u5500()) | |
173 | /* DB5500 divides by 8 */ | |
174 | mturate /= 8; | |
175 | else if (cpu_is_u8500ed()) { | |
176 | /* | |
177 | * This clocking setting must not be used | |
178 | * in the ED chip, it is simply not | |
179 | * connected anywhere! | |
180 | */ | |
181 | mturate = 0; | |
182 | BUG(); | |
183 | } else | |
184 | /* | |
185 | * In this mode the ulp38m4 clock is divided | |
186 | * by a factor 16, on the DB8500 typically | |
187 | * 38400000 / 16 ~ 2.4 MHz. | |
188 | * TODO: Replace the constant with a reference | |
189 | * to the ULP source once this is modeled. | |
190 | */ | |
191 | mturate = 38400000 / 16; | |
192 | } | |
193 | } | |
194 | ||
195 | /* Return the clock selected for this MTU */ | |
196 | if (tcr & (1 << mtu)) | |
197 | retclk = clk32k; | |
198 | else | |
199 | retclk = mturate; | |
200 | ||
201 | pr_info("MTU%d clock rate: %lu Hz\n", mtu, retclk); | |
202 | return retclk; | |
203 | } | |
204 | ||
c6b503ca SK |
205 | unsigned long clk_get_rate(struct clk *clk) |
206 | { | |
1df20afc RV |
207 | unsigned long rate; |
208 | ||
ba327b1e LW |
209 | /* |
210 | * If there is a custom getrate callback for this clock, | |
211 | * it will take precedence. | |
212 | */ | |
213 | if (clk->get_rate) | |
214 | return clk->get_rate(clk); | |
215 | ||
1df20afc RV |
216 | if (clk->ops && clk->ops->get_rate) |
217 | return clk->ops->get_rate(clk); | |
218 | ||
219 | rate = clk->rate; | |
220 | if (!rate) { | |
221 | if (clk->parent_periph) | |
222 | rate = clk_get_rate(clk->parent_periph); | |
223 | else if (clk->parent_cluster) | |
224 | rate = clk_get_rate(clk->parent_cluster); | |
225 | } | |
226 | ||
227 | return rate; | |
c6b503ca SK |
228 | } |
229 | EXPORT_SYMBOL(clk_get_rate); | |
230 | ||
231 | long clk_round_rate(struct clk *clk, unsigned long rate) | |
232 | { | |
233 | /*TODO*/ | |
234 | return rate; | |
235 | } | |
236 | EXPORT_SYMBOL(clk_round_rate); | |
237 | ||
238 | int clk_set_rate(struct clk *clk, unsigned long rate) | |
239 | { | |
240 | clk->rate = rate; | |
241 | return 0; | |
242 | } | |
243 | EXPORT_SYMBOL(clk_set_rate); | |
244 | ||
1df20afc RV |
245 | static void clk_prcmu_enable(struct clk *clk) |
246 | { | |
247 | void __iomem *cg_set_reg = __io_address(U8500_PRCMU_BASE) | |
248 | + PRCM_YYCLKEN0_MGT_SET + clk->prcmu_cg_off; | |
249 | ||
250 | writel(1 << clk->prcmu_cg_bit, cg_set_reg); | |
251 | } | |
252 | ||
253 | static void clk_prcmu_disable(struct clk *clk) | |
254 | { | |
255 | void __iomem *cg_clr_reg = __io_address(U8500_PRCMU_BASE) | |
256 | + PRCM_YYCLKEN0_MGT_CLR + clk->prcmu_cg_off; | |
257 | ||
258 | writel(1 << clk->prcmu_cg_bit, cg_clr_reg); | |
259 | } | |
260 | ||
261 | /* ED doesn't have the combined set/clr registers */ | |
262 | static void clk_prcmu_ed_enable(struct clk *clk) | |
263 | { | |
264 | void __iomem *addr = __io_address(U8500_PRCMU_BASE) | |
265 | + clk->prcmu_cg_mgt; | |
266 | ||
267 | writel(readl(addr) | PRCM_MGT_ENABLE, addr); | |
268 | } | |
269 | ||
270 | static void clk_prcmu_ed_disable(struct clk *clk) | |
271 | { | |
272 | void __iomem *addr = __io_address(U8500_PRCMU_BASE) | |
273 | + clk->prcmu_cg_mgt; | |
274 | ||
275 | writel(readl(addr) & ~PRCM_MGT_ENABLE, addr); | |
276 | } | |
277 | ||
278 | static struct clkops clk_prcmu_ops = { | |
279 | .enable = clk_prcmu_enable, | |
280 | .disable = clk_prcmu_disable, | |
c6b503ca SK |
281 | }; |
282 | ||
1df20afc RV |
283 | static unsigned int clkrst_base[] = { |
284 | [1] = U8500_CLKRST1_BASE, | |
285 | [2] = U8500_CLKRST2_BASE, | |
286 | [3] = U8500_CLKRST3_BASE, | |
287 | [5] = U8500_CLKRST5_BASE, | |
288 | [6] = U8500_CLKRST6_BASE, | |
289 | [7] = U8500_CLKRST7_BASE_ED, | |
c6b503ca SK |
290 | }; |
291 | ||
1df20afc RV |
292 | static void clk_prcc_enable(struct clk *clk) |
293 | { | |
294 | void __iomem *addr = __io_address(clkrst_base[clk->cluster]); | |
295 | ||
296 | if (clk->prcc_kernel != -1) | |
297 | writel(1 << clk->prcc_kernel, addr + PRCC_KCKEN); | |
298 | ||
299 | if (clk->prcc_bus != -1) | |
300 | writel(1 << clk->prcc_bus, addr + PRCC_PCKEN); | |
301 | } | |
302 | ||
303 | static void clk_prcc_disable(struct clk *clk) | |
304 | { | |
305 | void __iomem *addr = __io_address(clkrst_base[clk->cluster]); | |
306 | ||
307 | if (clk->prcc_bus != -1) | |
308 | writel(1 << clk->prcc_bus, addr + PRCC_PCKDIS); | |
309 | ||
310 | if (clk->prcc_kernel != -1) | |
311 | writel(1 << clk->prcc_kernel, addr + PRCC_KCKDIS); | |
312 | } | |
313 | ||
314 | static struct clkops clk_prcc_ops = { | |
315 | .enable = clk_prcc_enable, | |
316 | .disable = clk_prcc_disable, | |
317 | }; | |
318 | ||
319 | static struct clk clk_32khz = { | |
320 | .rate = 32000, | |
321 | }; | |
322 | ||
323 | /* | |
324 | * PRCMU level clock gating | |
325 | */ | |
326 | ||
327 | /* Bank 0 */ | |
328 | static DEFINE_PRCMU_CLK(svaclk, 0x0, 2, SVAMMDSPCLK); | |
329 | static DEFINE_PRCMU_CLK(siaclk, 0x0, 3, SIAMMDSPCLK); | |
330 | static DEFINE_PRCMU_CLK(sgaclk, 0x0, 4, SGACLK); | |
331 | static DEFINE_PRCMU_CLK_RATE(uartclk, 0x0, 5, UARTCLK, 38400000); | |
332 | static DEFINE_PRCMU_CLK(msp02clk, 0x0, 6, MSP02CLK); | |
333 | static DEFINE_PRCMU_CLK(msp1clk, 0x0, 7, MSP1CLK); /* v1 */ | |
334 | static DEFINE_PRCMU_CLK_RATE(i2cclk, 0x0, 8, I2CCLK, 48000000); | |
335 | static DEFINE_PRCMU_CLK_RATE(sdmmcclk, 0x0, 9, SDMMCCLK, 50000000); | |
336 | static DEFINE_PRCMU_CLK(slimclk, 0x0, 10, SLIMCLK); | |
337 | static DEFINE_PRCMU_CLK(per1clk, 0x0, 11, PER1CLK); | |
338 | static DEFINE_PRCMU_CLK(per2clk, 0x0, 12, PER2CLK); | |
339 | static DEFINE_PRCMU_CLK(per3clk, 0x0, 13, PER3CLK); | |
340 | static DEFINE_PRCMU_CLK(per5clk, 0x0, 14, PER5CLK); | |
341 | static DEFINE_PRCMU_CLK_RATE(per6clk, 0x0, 15, PER6CLK, 133330000); | |
342 | static DEFINE_PRCMU_CLK_RATE(per7clk, 0x0, 16, PER7CLK, 100000000); | |
343 | static DEFINE_PRCMU_CLK(lcdclk, 0x0, 17, LCDCLK); | |
344 | static DEFINE_PRCMU_CLK(bmlclk, 0x0, 18, BMLCLK); | |
345 | static DEFINE_PRCMU_CLK(hsitxclk, 0x0, 19, HSITXCLK); | |
346 | static DEFINE_PRCMU_CLK(hsirxclk, 0x0, 20, HSIRXCLK); | |
347 | static DEFINE_PRCMU_CLK(hdmiclk, 0x0, 21, HDMICLK); | |
348 | static DEFINE_PRCMU_CLK(apeatclk, 0x0, 22, APEATCLK); | |
349 | static DEFINE_PRCMU_CLK(apetraceclk, 0x0, 23, APETRACECLK); | |
350 | static DEFINE_PRCMU_CLK(mcdeclk, 0x0, 24, MCDECLK); | |
351 | static DEFINE_PRCMU_CLK(ipi2clk, 0x0, 25, IPI2CCLK); | |
352 | static DEFINE_PRCMU_CLK(dsialtclk, 0x0, 26, DSIALTCLK); /* v1 */ | |
353 | static DEFINE_PRCMU_CLK(dmaclk, 0x0, 27, DMACLK); | |
354 | static DEFINE_PRCMU_CLK(b2r2clk, 0x0, 28, B2R2CLK); | |
355 | static DEFINE_PRCMU_CLK(tvclk, 0x0, 29, TVCLK); | |
356 | static DEFINE_PRCMU_CLK(uniproclk, 0x0, 30, UNIPROCLK); /* v1 */ | |
357 | static DEFINE_PRCMU_CLK_RATE(sspclk, 0x0, 31, SSPCLK, 48000000); /* v1 */ | |
358 | ||
359 | /* Bank 1 */ | |
360 | static DEFINE_PRCMU_CLK(rngclk, 0x4, 0, RNGCLK); /* v1 */ | |
361 | static DEFINE_PRCMU_CLK(uiccclk, 0x4, 1, UICCCLK); /* v1 */ | |
362 | ||
363 | /* | |
364 | * PRCC level clock gating | |
365 | * Format: per#, clk, PCKEN bit, KCKEN bit, parent | |
366 | */ | |
367 | ||
368 | /* Peripheral Cluster #1 */ | |
369 | static DEFINE_PRCC_CLK(1, i2c4, 10, 9, &clk_i2cclk); | |
370 | static DEFINE_PRCC_CLK(1, gpio0, 9, -1, NULL); | |
371 | static DEFINE_PRCC_CLK(1, slimbus0, 8, 8, &clk_slimclk); | |
372 | static DEFINE_PRCC_CLK(1, spi3_ed, 7, 7, NULL); | |
373 | static DEFINE_PRCC_CLK(1, spi3_v1, 7, -1, NULL); | |
374 | static DEFINE_PRCC_CLK(1, i2c2, 6, 6, &clk_i2cclk); | |
375 | static DEFINE_PRCC_CLK(1, sdi0, 5, 5, &clk_sdmmcclk); | |
376 | static DEFINE_PRCC_CLK(1, msp1_ed, 4, 4, &clk_msp02clk); | |
377 | static DEFINE_PRCC_CLK(1, msp1_v1, 4, 4, &clk_msp1clk); | |
378 | static DEFINE_PRCC_CLK(1, msp0, 3, 3, &clk_msp02clk); | |
379 | static DEFINE_PRCC_CLK(1, i2c1, 2, 2, &clk_i2cclk); | |
380 | static DEFINE_PRCC_CLK(1, uart1, 1, 1, &clk_uartclk); | |
381 | static DEFINE_PRCC_CLK(1, uart0, 0, 0, &clk_uartclk); | |
382 | ||
383 | /* Peripheral Cluster #2 */ | |
384 | ||
385 | static DEFINE_PRCC_CLK(2, gpio1_ed, 12, -1, NULL); | |
386 | static DEFINE_PRCC_CLK(2, ssitx_ed, 11, -1, NULL); | |
387 | static DEFINE_PRCC_CLK(2, ssirx_ed, 10, -1, NULL); | |
388 | static DEFINE_PRCC_CLK(2, spi0_ed, 9, -1, NULL); | |
389 | static DEFINE_PRCC_CLK(2, sdi3_ed, 8, 6, &clk_sdmmcclk); | |
390 | static DEFINE_PRCC_CLK(2, sdi1_ed, 7, 5, &clk_sdmmcclk); | |
391 | static DEFINE_PRCC_CLK(2, msp2_ed, 6, 4, &clk_msp02clk); | |
392 | static DEFINE_PRCC_CLK(2, sdi4_ed, 4, 2, &clk_sdmmcclk); | |
393 | static DEFINE_PRCC_CLK(2, pwl_ed, 3, 1, NULL); | |
394 | static DEFINE_PRCC_CLK(2, spi1_ed, 2, -1, NULL); | |
395 | static DEFINE_PRCC_CLK(2, spi2_ed, 1, -1, NULL); | |
396 | static DEFINE_PRCC_CLK(2, i2c3_ed, 0, 0, &clk_i2cclk); | |
397 | ||
398 | static DEFINE_PRCC_CLK(2, gpio1_v1, 11, -1, NULL); | |
399 | static DEFINE_PRCC_CLK(2, ssitx_v1, 10, 7, NULL); | |
400 | static DEFINE_PRCC_CLK(2, ssirx_v1, 9, 6, NULL); | |
401 | static DEFINE_PRCC_CLK(2, spi0_v1, 8, -1, NULL); | |
402 | static DEFINE_PRCC_CLK(2, sdi3_v1, 7, 5, &clk_sdmmcclk); | |
403 | static DEFINE_PRCC_CLK(2, sdi1_v1, 6, 4, &clk_sdmmcclk); | |
404 | static DEFINE_PRCC_CLK(2, msp2_v1, 5, 3, &clk_msp02clk); | |
405 | static DEFINE_PRCC_CLK(2, sdi4_v1, 4, 2, &clk_sdmmcclk); | |
406 | static DEFINE_PRCC_CLK(2, pwl_v1, 3, 1, NULL); | |
407 | static DEFINE_PRCC_CLK(2, spi1_v1, 2, -1, NULL); | |
408 | static DEFINE_PRCC_CLK(2, spi2_v1, 1, -1, NULL); | |
409 | static DEFINE_PRCC_CLK(2, i2c3_v1, 0, 0, &clk_i2cclk); | |
410 | ||
411 | /* Peripheral Cluster #3 */ | |
412 | static DEFINE_PRCC_CLK(3, gpio2, 8, -1, NULL); | |
413 | static DEFINE_PRCC_CLK(3, sdi5, 7, 7, &clk_sdmmcclk); | |
414 | static DEFINE_PRCC_CLK(3, uart2, 6, 6, &clk_uartclk); | |
415 | static DEFINE_PRCC_CLK(3, ske, 5, 5, &clk_32khz); | |
416 | static DEFINE_PRCC_CLK(3, sdi2, 4, 4, &clk_sdmmcclk); | |
417 | static DEFINE_PRCC_CLK(3, i2c0, 3, 3, &clk_i2cclk); | |
418 | static DEFINE_PRCC_CLK(3, ssp1_ed, 2, 2, &clk_i2cclk); | |
419 | static DEFINE_PRCC_CLK(3, ssp0_ed, 1, 1, &clk_i2cclk); | |
420 | static DEFINE_PRCC_CLK(3, ssp1_v1, 2, 2, &clk_sspclk); | |
421 | static DEFINE_PRCC_CLK(3, ssp0_v1, 1, 1, &clk_sspclk); | |
422 | static DEFINE_PRCC_CLK(3, fsmc, 0, -1, NULL); | |
423 | ||
424 | /* Peripheral Cluster #4 is in the always on domain */ | |
425 | ||
426 | /* Peripheral Cluster #5 */ | |
427 | static DEFINE_PRCC_CLK(5, gpio3, 1, -1, NULL); | |
428 | static DEFINE_PRCC_CLK(5, usb_ed, 0, 0, &clk_i2cclk); | |
429 | static DEFINE_PRCC_CLK(5, usb_v1, 0, 0, NULL); | |
430 | ||
431 | /* Peripheral Cluster #6 */ | |
432 | ||
ba327b1e LW |
433 | /* MTU ID in data */ |
434 | static DEFINE_PRCC_CLK_CUSTOM(6, mtu1_v1, 8, -1, NULL, clk_mtu_get_rate, 1); | |
435 | static DEFINE_PRCC_CLK_CUSTOM(6, mtu0_v1, 7, -1, NULL, clk_mtu_get_rate, 0); | |
1df20afc RV |
436 | static DEFINE_PRCC_CLK(6, cfgreg_v1, 6, 6, NULL); |
437 | static DEFINE_PRCC_CLK(6, dmc_ed, 6, 6, NULL); | |
438 | static DEFINE_PRCC_CLK(6, hash1, 5, -1, NULL); | |
439 | static DEFINE_PRCC_CLK(6, unipro_v1, 4, 1, &clk_uniproclk); | |
440 | static DEFINE_PRCC_CLK(6, cryp1_ed, 4, -1, NULL); | |
441 | static DEFINE_PRCC_CLK(6, pka, 3, -1, NULL); | |
442 | static DEFINE_PRCC_CLK(6, hash0, 2, -1, NULL); | |
443 | static DEFINE_PRCC_CLK(6, cryp0, 1, -1, NULL); | |
444 | static DEFINE_PRCC_CLK(6, rng_ed, 0, 0, &clk_i2cclk); | |
445 | static DEFINE_PRCC_CLK(6, rng_v1, 0, 0, &clk_rngclk); | |
446 | ||
447 | /* Peripheral Cluster #7 */ | |
448 | ||
449 | static DEFINE_PRCC_CLK(7, tzpc0_ed, 4, -1, NULL); | |
ba327b1e LW |
450 | /* MTU ID in data */ |
451 | static DEFINE_PRCC_CLK_CUSTOM(7, mtu1_ed, 3, -1, NULL, clk_mtu_get_rate, 1); | |
452 | static DEFINE_PRCC_CLK_CUSTOM(7, mtu0_ed, 2, -1, NULL, clk_mtu_get_rate, 0); | |
1df20afc RV |
453 | static DEFINE_PRCC_CLK(7, wdg_ed, 1, -1, NULL); |
454 | static DEFINE_PRCC_CLK(7, cfgreg_ed, 0, -1, NULL); | |
455 | ||
456 | static struct clk_lookup u8500_common_clks[] = { | |
457 | /* Peripheral Cluster #1 */ | |
af7dc228 RV |
458 | CLK(gpio0, "gpio.0", NULL), |
459 | CLK(gpio0, "gpio.1", NULL), | |
1df20afc RV |
460 | CLK(slimbus0, "slimbus0", NULL), |
461 | CLK(i2c2, "nmk-i2c.2", NULL), | |
462 | CLK(sdi0, "sdi0", NULL), | |
463 | CLK(msp0, "msp0", NULL), | |
464 | CLK(i2c1, "nmk-i2c.1", NULL), | |
465 | CLK(uart1, "uart1", NULL), | |
466 | CLK(uart0, "uart0", NULL), | |
467 | ||
468 | /* Peripheral Cluster #3 */ | |
af7dc228 RV |
469 | CLK(gpio2, "gpio.2", NULL), |
470 | CLK(gpio2, "gpio.3", NULL), | |
471 | CLK(gpio2, "gpio.4", NULL), | |
472 | CLK(gpio2, "gpio.5", NULL), | |
1df20afc RV |
473 | CLK(sdi5, "sdi5", NULL), |
474 | CLK(uart2, "uart2", NULL), | |
475 | CLK(ske, "ske", NULL), | |
476 | CLK(sdi2, "sdi2", NULL), | |
477 | CLK(i2c0, "nmk-i2c.0", NULL), | |
478 | CLK(fsmc, "fsmc", NULL), | |
479 | ||
480 | /* Peripheral Cluster #5 */ | |
af7dc228 | 481 | CLK(gpio3, "gpio.8", NULL), |
1df20afc RV |
482 | |
483 | /* Peripheral Cluster #6 */ | |
484 | CLK(hash1, "hash1", NULL), | |
485 | CLK(pka, "pka", NULL), | |
486 | CLK(hash0, "hash0", NULL), | |
487 | CLK(cryp0, "cryp0", NULL), | |
488 | ||
489 | /* PRCMU level clock gating */ | |
490 | ||
491 | /* Bank 0 */ | |
492 | CLK(svaclk, "sva", NULL), | |
493 | CLK(siaclk, "sia", NULL), | |
494 | CLK(sgaclk, "sga", NULL), | |
495 | CLK(slimclk, "slim", NULL), | |
496 | CLK(lcdclk, "lcd", NULL), | |
497 | CLK(bmlclk, "bml", NULL), | |
498 | CLK(hsitxclk, "stm-hsi.0", NULL), | |
499 | CLK(hsirxclk, "stm-hsi.1", NULL), | |
500 | CLK(hdmiclk, "hdmi", NULL), | |
501 | CLK(apeatclk, "apeat", NULL), | |
502 | CLK(apetraceclk, "apetrace", NULL), | |
503 | CLK(mcdeclk, "mcde", NULL), | |
504 | CLK(ipi2clk, "ipi2", NULL), | |
505 | CLK(dmaclk, "dma40", NULL), | |
506 | CLK(b2r2clk, "b2r2", NULL), | |
507 | CLK(tvclk, "tv", NULL), | |
508 | }; | |
509 | ||
510 | static struct clk_lookup u8500_ed_clks[] = { | |
511 | /* Peripheral Cluster #1 */ | |
512 | CLK(spi3_ed, "spi3", NULL), | |
513 | CLK(msp1_ed, "msp1", NULL), | |
514 | ||
515 | /* Peripheral Cluster #2 */ | |
af7dc228 RV |
516 | CLK(gpio1_ed, "gpio.6", NULL), |
517 | CLK(gpio1_ed, "gpio.7", NULL), | |
1df20afc RV |
518 | CLK(ssitx_ed, "ssitx", NULL), |
519 | CLK(ssirx_ed, "ssirx", NULL), | |
520 | CLK(spi0_ed, "spi0", NULL), | |
521 | CLK(sdi3_ed, "sdi3", NULL), | |
522 | CLK(sdi1_ed, "sdi1", NULL), | |
523 | CLK(msp2_ed, "msp2", NULL), | |
524 | CLK(sdi4_ed, "sdi4", NULL), | |
525 | CLK(pwl_ed, "pwl", NULL), | |
526 | CLK(spi1_ed, "spi1", NULL), | |
527 | CLK(spi2_ed, "spi2", NULL), | |
528 | CLK(i2c3_ed, "nmk-i2c.3", NULL), | |
529 | ||
530 | /* Peripheral Cluster #3 */ | |
531 | CLK(ssp1_ed, "ssp1", NULL), | |
532 | CLK(ssp0_ed, "ssp0", NULL), | |
533 | ||
534 | /* Peripheral Cluster #5 */ | |
535 | CLK(usb_ed, "musb_hdrc.0", "usb"), | |
536 | ||
537 | /* Peripheral Cluster #6 */ | |
538 | CLK(dmc_ed, "dmc", NULL), | |
539 | CLK(cryp1_ed, "cryp1", NULL), | |
540 | CLK(rng_ed, "rng", NULL), | |
541 | ||
542 | /* Peripheral Cluster #7 */ | |
543 | CLK(tzpc0_ed, "tzpc0", NULL), | |
544 | CLK(mtu1_ed, "mtu1", NULL), | |
545 | CLK(mtu0_ed, "mtu0", NULL), | |
546 | CLK(wdg_ed, "wdg", NULL), | |
547 | CLK(cfgreg_ed, "cfgreg", NULL), | |
548 | }; | |
549 | ||
550 | static struct clk_lookup u8500_v1_clks[] = { | |
551 | /* Peripheral Cluster #1 */ | |
552 | CLK(i2c4, "nmk-i2c.4", NULL), | |
553 | CLK(spi3_v1, "spi3", NULL), | |
554 | CLK(msp1_v1, "msp1", NULL), | |
555 | ||
556 | /* Peripheral Cluster #2 */ | |
af7dc228 RV |
557 | CLK(gpio1_v1, "gpio.6", NULL), |
558 | CLK(gpio1_v1, "gpio.7", NULL), | |
1df20afc RV |
559 | CLK(ssitx_v1, "ssitx", NULL), |
560 | CLK(ssirx_v1, "ssirx", NULL), | |
561 | CLK(spi0_v1, "spi0", NULL), | |
562 | CLK(sdi3_v1, "sdi3", NULL), | |
563 | CLK(sdi1_v1, "sdi1", NULL), | |
564 | CLK(msp2_v1, "msp2", NULL), | |
565 | CLK(sdi4_v1, "sdi4", NULL), | |
566 | CLK(pwl_v1, "pwl", NULL), | |
567 | CLK(spi1_v1, "spi1", NULL), | |
568 | CLK(spi2_v1, "spi2", NULL), | |
569 | CLK(i2c3_v1, "nmk-i2c.3", NULL), | |
570 | ||
571 | /* Peripheral Cluster #3 */ | |
572 | CLK(ssp1_v1, "ssp1", NULL), | |
573 | CLK(ssp0_v1, "ssp0", NULL), | |
574 | ||
575 | /* Peripheral Cluster #5 */ | |
576 | CLK(usb_v1, "musb_hdrc.0", "usb"), | |
577 | ||
578 | /* Peripheral Cluster #6 */ | |
579 | CLK(mtu1_v1, "mtu1", NULL), | |
580 | CLK(mtu0_v1, "mtu0", NULL), | |
581 | CLK(cfgreg_v1, "cfgreg", NULL), | |
582 | CLK(hash1, "hash1", NULL), | |
583 | CLK(unipro_v1, "unipro", NULL), | |
584 | CLK(rng_v1, "rng", NULL), | |
585 | ||
586 | /* PRCMU level clock gating */ | |
587 | ||
588 | /* Bank 0 */ | |
589 | CLK(uniproclk, "uniproclk", NULL), | |
590 | CLK(dsialtclk, "dsialt", NULL), | |
591 | ||
592 | /* Bank 1 */ | |
593 | CLK(rngclk, "rng", NULL), | |
594 | CLK(uiccclk, "uicc", NULL), | |
c6b503ca SK |
595 | }; |
596 | ||
ba327b1e | 597 | int __init clk_init(void) |
c6b503ca | 598 | { |
1df20afc RV |
599 | if (cpu_is_u8500ed()) { |
600 | clk_prcmu_ops.enable = clk_prcmu_ed_enable; | |
601 | clk_prcmu_ops.disable = clk_prcmu_ed_disable; | |
ba327b1e | 602 | clk_per6clk.rate = 100000000; |
591d8dd7 RV |
603 | } else if (cpu_is_u5500()) { |
604 | /* Clock tree for U5500 not implemented yet */ | |
605 | clk_prcc_ops.enable = clk_prcc_ops.disable = NULL; | |
606 | clk_prcmu_ops.enable = clk_prcmu_ops.disable = NULL; | |
ba327b1e | 607 | clk_per6clk.rate = 26000000; |
1df20afc RV |
608 | } |
609 | ||
610 | clkdev_add_table(u8500_common_clks, ARRAY_SIZE(u8500_common_clks)); | |
611 | if (cpu_is_u8500ed()) | |
612 | clkdev_add_table(u8500_ed_clks, ARRAY_SIZE(u8500_ed_clks)); | |
613 | else | |
614 | clkdev_add_table(u8500_v1_clks, ARRAY_SIZE(u8500_v1_clks)); | |
615 | ||
c6b503ca SK |
616 | return 0; |
617 | } |