projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 6055930c RV |
1 | /* |
| 2 | * Copyright (C) ST-Ericsson SA 2010 | |
| 3 | * | |
| 4 | * Author: Rabin Vincent <rabin.vincent@stericsson.com> | |
| 5 | * License terms: GNU General Public License (GPL) version 2 | |
| 6 | */ | |
| 7 | ||
| 8 | #ifndef __MACH_IRQS_DB8500_H | |
| 9 | #define __MACH_IRQS_DB8500_H | |
| 10 | ||
| 11 | #define IRQ_DB8500_MTU0 (IRQ_SHPI_START + 4) | |
| 12 | #define IRQ_DB8500_SPI2 (IRQ_SHPI_START + 6) | |
| 13 | #define IRQ_DB8500_PMU (IRQ_SHPI_START + 7) | |
| 14 | #define IRQ_DB8500_SPI0 (IRQ_SHPI_START + 8) | |
| 15 | #define IRQ_DB8500_RTT (IRQ_SHPI_START + 9) | |
| 16 | #define IRQ_DB8500_PKA (IRQ_SHPI_START + 10) | |
| 17 | #define IRQ_DB8500_UART0 (IRQ_SHPI_START + 11) | |
| 18 | #define IRQ_DB8500_I2C3 (IRQ_SHPI_START + 12) | |
| 19 | #define IRQ_DB8500_L2CC (IRQ_SHPI_START + 13) | |
| 20 | #define IRQ_DB8500_SSP0 (IRQ_SHPI_START + 14) | |
| 21 | #define IRQ_DB8500_CRYP1 (IRQ_SHPI_START + 15) | |
| 22 | #define IRQ_DB8500_MSP1_RX (IRQ_SHPI_START + 16) | |
| 23 | #define IRQ_DB8500_MTU1 (IRQ_SHPI_START + 17) | |
| 24 | #define IRQ_DB8500_RTC (IRQ_SHPI_START + 18) | |
| 25 | #define IRQ_DB8500_UART1 (IRQ_SHPI_START + 19) | |
| 26 | #define IRQ_DB8500_USB_WAKEUP (IRQ_SHPI_START + 20) | |
| 27 | #define IRQ_DB8500_I2C0 (IRQ_SHPI_START + 21) | |
| 28 | #define IRQ_DB8500_I2C1 (IRQ_SHPI_START + 22) | |
| 29 | #define IRQ_DB8500_USBOTG (IRQ_SHPI_START + 23) | |
| 30 | #define IRQ_DB8500_DMA_SECURE (IRQ_SHPI_START + 24) | |
| 31 | #define IRQ_DB8500_DMA (IRQ_SHPI_START + 25) | |
| 32 | #define IRQ_DB8500_UART2 (IRQ_SHPI_START + 26) | |
| 33 | #define IRQ_DB8500_ICN_PMU1 (IRQ_SHPI_START + 27) | |
| 34 | #define IRQ_DB8500_ICN_PMU2 (IRQ_SHPI_START + 28) | |
| 35 | #define IRQ_DB8500_HSIR_EXCEP (IRQ_SHPI_START + 29) | |
| 36 | #define IRQ_DB8500_MSP0 (IRQ_SHPI_START + 31) | |
| 37 | #define IRQ_DB8500_HSIR_CH0_OVRRUN (IRQ_SHPI_START + 32) | |
| 38 | #define IRQ_DB8500_HSIR_CH1_OVRRUN (IRQ_SHPI_START + 33) | |
| 39 | #define IRQ_DB8500_HSIR_CH2_OVRRUN (IRQ_SHPI_START + 34) | |
| 40 | #define IRQ_DB8500_HSIR_CH3_OVRRUN (IRQ_SHPI_START + 35) | |
| 41 | #define IRQ_DB8500_HSIR_CH4_OVRRUN (IRQ_SHPI_START + 36) | |
| 42 | #define IRQ_DB8500_HSIR_CH5_OVRRUN (IRQ_SHPI_START + 37) | |
| 43 | #define IRQ_DB8500_HSIR_CH6_OVRRUN (IRQ_SHPI_START + 38) | |
| 44 | #define IRQ_DB8500_HSIR_CH7_OVRRUN (IRQ_SHPI_START + 39) | |
| 45 | #define IRQ_DB8500_AB8500 (IRQ_SHPI_START + 40) | |
| 46 | #define IRQ_DB8500_SDMMC2 (IRQ_SHPI_START + 41) | |
| 47 | #define IRQ_DB8500_SIA (IRQ_SHPI_START + 42) | |
| 48 | #define IRQ_DB8500_SIA2 (IRQ_SHPI_START + 43) | |
| 49 | #define IRQ_DB8500_SVA (IRQ_SHPI_START + 44) | |
| 50 | #define IRQ_DB8500_SVA2 (IRQ_SHPI_START + 45) | |
| 51 | #define IRQ_DB8500_PRCMU0 (IRQ_SHPI_START + 46) | |
| 52 | #define IRQ_DB8500_PRCMU1 (IRQ_SHPI_START + 47) | |
| 53 | #define IRQ_DB8500_DISP (IRQ_SHPI_START + 48) | |
| 54 | #define IRQ_DB8500_SPI3 (IRQ_SHPI_START + 49) | |
| 55 | #define IRQ_DB8500_SDMMC1 (IRQ_SHPI_START + 50) | |
| 56 | #define IRQ_DB8500_I2C4 (IRQ_SHPI_START + 51) | |
| 57 | #define IRQ_DB8500_SSP1 (IRQ_SHPI_START + 52) | |
| 58 | #define IRQ_DB8500_SKE (IRQ_SHPI_START + 53) | |
| 59 | #define IRQ_DB8500_KB (IRQ_SHPI_START + 54) | |
| 60 | #define IRQ_DB8500_I2C2 (IRQ_SHPI_START + 55) | |
| 61 | #define IRQ_DB8500_B2R2 (IRQ_SHPI_START + 56) | |
| 62 | #define IRQ_DB8500_CRYP0 (IRQ_SHPI_START + 57) | |
| 63 | #define IRQ_DB8500_SDMMC3 (IRQ_SHPI_START + 59) | |
| 64 | #define IRQ_DB8500_SDMMC0 (IRQ_SHPI_START + 60) | |
| 65 | #define IRQ_DB8500_HSEM (IRQ_SHPI_START + 61) | |
| 66 | #define IRQ_DB8500_MSP1 (IRQ_SHPI_START + 62) | |
| 67 | #define IRQ_DB8500_SBAG (IRQ_SHPI_START + 63) | |
| 68 | #define IRQ_DB8500_SPI1 (IRQ_SHPI_START + 96) | |
| 69 | #define IRQ_DB8500_SRPTIMER (IRQ_SHPI_START + 97) | |
| 70 | #define IRQ_DB8500_MSP2 (IRQ_SHPI_START + 98) | |
| 71 | #define IRQ_DB8500_SDMMC4 (IRQ_SHPI_START + 99) | |
| 72 | #define IRQ_DB8500_SDMMC5 (IRQ_SHPI_START + 100) | |
| 73 | #define IRQ_DB8500_HSIRD0 (IRQ_SHPI_START + 104) | |
| 74 | #define IRQ_DB8500_HSIRD1 (IRQ_SHPI_START + 105) | |
| 75 | #define IRQ_DB8500_HSITD0 (IRQ_SHPI_START + 106) | |
| 76 | #define IRQ_DB8500_HSITD1 (IRQ_SHPI_START + 107) | |
| 77 | #define IRQ_DB8500_CTI0 (IRQ_SHPI_START + 108) | |
| 78 | #define IRQ_DB8500_CTI1 (IRQ_SHPI_START + 109) | |
| 79 | #define IRQ_DB8500_ICN_ERR (IRQ_SHPI_START + 110) | |
| 80 | #define IRQ_DB8500_MALI_PPMMU (IRQ_SHPI_START + 112) | |
| 81 | #define IRQ_DB8500_MALI_PP (IRQ_SHPI_START + 113) | |
| 82 | #define IRQ_DB8500_MALI_GPMMU (IRQ_SHPI_START + 114) | |
| 83 | #define IRQ_DB8500_MALI_GP (IRQ_SHPI_START + 115) | |
| 84 | #define IRQ_DB8500_MALI (IRQ_SHPI_START + 116) | |
| 85 | #define IRQ_DB8500_PRCMU_SEM (IRQ_SHPI_START + 118) | |
| 86 | #define IRQ_DB8500_GPIO0 (IRQ_SHPI_START + 119) | |
| 87 | #define IRQ_DB8500_GPIO1 (IRQ_SHPI_START + 120) | |
| 88 | #define IRQ_DB8500_GPIO2 (IRQ_SHPI_START + 121) | |
| 89 | #define IRQ_DB8500_GPIO3 (IRQ_SHPI_START + 122) | |
| 90 | #define IRQ_DB8500_GPIO4 (IRQ_SHPI_START + 123) | |
| 91 | #define IRQ_DB8500_GPIO5 (IRQ_SHPI_START + 124) | |
| 92 | #define IRQ_DB8500_GPIO6 (IRQ_SHPI_START + 125) | |
| 93 | #define IRQ_DB8500_GPIO7 (IRQ_SHPI_START + 126) | |
| 94 | #define IRQ_DB8500_GPIO8 (IRQ_SHPI_START + 127) | |
| 95 | ||
| 06be2efa RV |
96 | #define IRQ_CA_WAKE_REQ_ED (IRQ_SHPI_START + 71) |
| 97 | #define IRQ_AC_READ_NOTIFICATION_0_ED (IRQ_SHPI_START + 66) | |
| 98 | #define IRQ_AC_READ_NOTIFICATION_1_ED (IRQ_SHPI_START + 64) | |
| 99 | #define IRQ_CA_MSG_PEND_NOTIFICATION_0_ED (IRQ_SHPI_START + 67) | |
| 100 | #define IRQ_CA_MSG_PEND_NOTIFICATION_1_ED (IRQ_SHPI_START + 65) | |
| 101 | ||
| 102 | #define IRQ_CA_WAKE_REQ_V1 (IRQ_SHPI_START + 83) | |
| 103 | #define IRQ_AC_READ_NOTIFICATION_0_V1 (IRQ_SHPI_START + 78) | |
| 104 | #define IRQ_AC_READ_NOTIFICATION_1_V1 (IRQ_SHPI_START + 76) | |
| 105 | #define IRQ_CA_MSG_PEND_NOTIFICATION_0_V1 (IRQ_SHPI_START + 79) | |
| 106 | #define IRQ_CA_MSG_PEND_NOTIFICATION_1_V1 (IRQ_SHPI_START + 77) | |
| 107 | ||
| 108 | #ifdef CONFIG_UX500_SOC_DB8500 | |
| 109 | ||
| 110 | /* Virtual interrupts corresponding to the PRCMU wakeups. */ | |
| 111 | #define IRQ_PRCMU_BASE IRQ_SOC_START | |
| 06be2efa RV |
112 | #define IRQ_PRCMU_END (IRQ_PRCMU_BASE + 23) |
| 113 | ||
| 114 | /* | |
| 115 | * We may have several SoCs, but only one will run at a | |
| 116 | * time, so the one with most IRQs will bump this ahead, | |
| 117 | * but the IRQ_SOC_START remains the same for either SoC. | |
| 118 | */ | |
| 119 | #if IRQ_SOC_END < IRQ_PRCMU_END | |
| 120 | #undef IRQ_SOC_END | |
| 121 | #define IRQ_SOC_END IRQ_PRCMU_END | |
| 122 | #endif | |
| 123 | ||
| 124 | #endif /* CONFIG_UX500_SOC_DB8500 */ | |
| 6055930c | 125 | #endif |