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64b889b3 MS |
1 | /* |
2 | * Xilinx SLCR driver | |
3 | * | |
4 | * Copyright (c) 2011-2013 Xilinx Inc. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License | |
8 | * as published by the Free Software Foundation; either version | |
9 | * 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * You should have received a copy of the GNU General Public | |
12 | * License along with this program; if not, write to the Free | |
13 | * Software Foundation, Inc., 675 Mass Ave, Cambridge, MA | |
14 | * 02139, USA. | |
15 | */ | |
16 | ||
64b889b3 | 17 | #include <linux/io.h> |
64b889b3 | 18 | #include <linux/of_address.h> |
64b889b3 MS |
19 | #include <linux/clk/zynq.h> |
20 | #include "common.h" | |
21 | ||
b5f177ff SB |
22 | /* register offsets */ |
23 | #define SLCR_UNLOCK_OFFSET 0x8 /* SCLR unlock register */ | |
96790f0a | 24 | #define SLCR_PS_RST_CTRL_OFFSET 0x200 /* PS Software Reset Control */ |
b5f177ff SB |
25 | #define SLCR_A9_CPU_RST_CTRL_OFFSET 0x244 /* CPU Software Reset Control */ |
26 | #define SLCR_REBOOT_STATUS_OFFSET 0x258 /* PS Reboot Status */ | |
aa7eb2bb | 27 | |
b5f177ff | 28 | #define SLCR_UNLOCK_MAGIC 0xDF0D |
aa7eb2bb MS |
29 | #define SLCR_A9_CPU_CLKSTOP 0x10 |
30 | #define SLCR_A9_CPU_RST 0x1 | |
31 | ||
64b889b3 MS |
32 | void __iomem *zynq_slcr_base; |
33 | ||
96790f0a MS |
34 | /** |
35 | * zynq_slcr_system_reset - Reset the entire system. | |
36 | */ | |
37 | void zynq_slcr_system_reset(void) | |
38 | { | |
39 | u32 reboot; | |
40 | ||
41 | /* | |
42 | * Unlock the SLCR then reset the system. | |
43 | * Note that this seems to require raw i/o | |
44 | * functions or there's a lockup? | |
45 | */ | |
b5f177ff | 46 | writel(SLCR_UNLOCK_MAGIC, zynq_slcr_base + SLCR_UNLOCK_OFFSET); |
96790f0a MS |
47 | |
48 | /* | |
49 | * Clear 0x0F000000 bits of reboot status register to workaround | |
50 | * the FSBL not loading the bitstream after soft-reboot | |
51 | * This is a temporary solution until we know more. | |
52 | */ | |
b5f177ff SB |
53 | reboot = readl(zynq_slcr_base + SLCR_REBOOT_STATUS_OFFSET); |
54 | writel(reboot & 0xF0FFFFFF, zynq_slcr_base + SLCR_REBOOT_STATUS_OFFSET); | |
96790f0a MS |
55 | writel(1, zynq_slcr_base + SLCR_PS_RST_CTRL_OFFSET); |
56 | } | |
57 | ||
aa7eb2bb MS |
58 | /** |
59 | * zynq_slcr_cpu_start - Start cpu | |
60 | * @cpu: cpu number | |
61 | */ | |
62 | void zynq_slcr_cpu_start(int cpu) | |
63 | { | |
3db9e860 SB |
64 | u32 reg = readl(zynq_slcr_base + SLCR_A9_CPU_RST_CTRL_OFFSET); |
65 | reg &= ~(SLCR_A9_CPU_RST << cpu); | |
66 | writel(reg, zynq_slcr_base + SLCR_A9_CPU_RST_CTRL_OFFSET); | |
67 | reg &= ~(SLCR_A9_CPU_CLKSTOP << cpu); | |
68 | writel(reg, zynq_slcr_base + SLCR_A9_CPU_RST_CTRL_OFFSET); | |
aa7eb2bb MS |
69 | } |
70 | ||
71 | /** | |
72 | * zynq_slcr_cpu_stop - Stop cpu | |
73 | * @cpu: cpu number | |
74 | */ | |
75 | void zynq_slcr_cpu_stop(int cpu) | |
76 | { | |
3db9e860 SB |
77 | u32 reg = readl(zynq_slcr_base + SLCR_A9_CPU_RST_CTRL_OFFSET); |
78 | reg |= (SLCR_A9_CPU_CLKSTOP | SLCR_A9_CPU_RST) << cpu; | |
79 | writel(reg, zynq_slcr_base + SLCR_A9_CPU_RST_CTRL_OFFSET); | |
aa7eb2bb MS |
80 | } |
81 | ||
64b889b3 MS |
82 | /** |
83 | * zynq_slcr_init | |
84 | * Returns 0 on success, negative errno otherwise. | |
85 | * | |
86 | * Called early during boot from platform code to remap SLCR area. | |
87 | */ | |
88 | int __init zynq_slcr_init(void) | |
89 | { | |
90 | struct device_node *np; | |
91 | ||
92 | np = of_find_compatible_node(NULL, NULL, "xlnx,zynq-slcr"); | |
93 | if (!np) { | |
94 | pr_err("%s: no slcr node found\n", __func__); | |
95 | BUG(); | |
96 | } | |
97 | ||
98 | zynq_slcr_base = of_iomap(np, 0); | |
99 | if (!zynq_slcr_base) { | |
100 | pr_err("%s: Unable to map I/O memory\n", __func__); | |
101 | BUG(); | |
102 | } | |
103 | ||
104 | /* unlock the SLCR so that registers can be changed */ | |
b5f177ff | 105 | writel(SLCR_UNLOCK_MAGIC, zynq_slcr_base + SLCR_UNLOCK_OFFSET); |
64b889b3 MS |
106 | |
107 | pr_info("%s mapped to %p\n", np->name, zynq_slcr_base); | |
108 | ||
30e1e285 | 109 | zynq_clock_init(zynq_slcr_base); |
64b889b3 MS |
110 | |
111 | of_node_put(np); | |
112 | ||
113 | return 0; | |
114 | } |