Commit | Line | Data |
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64b889b3 MS |
1 | /* |
2 | * Xilinx SLCR driver | |
3 | * | |
4 | * Copyright (c) 2011-2013 Xilinx Inc. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License | |
8 | * as published by the Free Software Foundation; either version | |
9 | * 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * You should have received a copy of the GNU General Public | |
12 | * License along with this program; if not, write to the Free | |
13 | * Software Foundation, Inc., 675 Mass Ave, Cambridge, MA | |
14 | * 02139, USA. | |
15 | */ | |
16 | ||
64b889b3 | 17 | #include <linux/io.h> |
64e68617 | 18 | #include <linux/reboot.h> |
016f4dca | 19 | #include <linux/mfd/syscon.h> |
64b889b3 | 20 | #include <linux/of_address.h> |
016f4dca | 21 | #include <linux/regmap.h> |
64b889b3 MS |
22 | #include <linux/clk/zynq.h> |
23 | #include "common.h" | |
24 | ||
b5f177ff SB |
25 | /* register offsets */ |
26 | #define SLCR_UNLOCK_OFFSET 0x8 /* SCLR unlock register */ | |
96790f0a | 27 | #define SLCR_PS_RST_CTRL_OFFSET 0x200 /* PS Software Reset Control */ |
b5f177ff SB |
28 | #define SLCR_A9_CPU_RST_CTRL_OFFSET 0x244 /* CPU Software Reset Control */ |
29 | #define SLCR_REBOOT_STATUS_OFFSET 0x258 /* PS Reboot Status */ | |
00f7dc63 | 30 | #define SLCR_PSS_IDCODE 0x530 /* PS IDCODE */ |
aa7eb2bb | 31 | |
b5f177ff | 32 | #define SLCR_UNLOCK_MAGIC 0xDF0D |
aa7eb2bb MS |
33 | #define SLCR_A9_CPU_CLKSTOP 0x10 |
34 | #define SLCR_A9_CPU_RST 0x1 | |
00f7dc63 MS |
35 | #define SLCR_PSS_IDCODE_DEVICE_SHIFT 12 |
36 | #define SLCR_PSS_IDCODE_DEVICE_MASK 0x1F | |
aa7eb2bb | 37 | |
7b274efe | 38 | static void __iomem *zynq_slcr_base; |
016f4dca | 39 | static struct regmap *zynq_slcr_regmap; |
64b889b3 | 40 | |
871c6971 MS |
41 | /** |
42 | * zynq_slcr_write - Write to a register in SLCR block | |
43 | * | |
44 | * @val: Value to write to the register | |
45 | * @offset: Register offset in SLCR block | |
46 | * | |
47 | * Return: a negative value on error, 0 on success | |
48 | */ | |
49 | static int zynq_slcr_write(u32 val, u32 offset) | |
50 | { | |
871c6971 MS |
51 | return regmap_write(zynq_slcr_regmap, offset, val); |
52 | } | |
53 | ||
54 | /** | |
55 | * zynq_slcr_read - Read a register in SLCR block | |
56 | * | |
57 | * @val: Pointer to value to be read from SLCR | |
58 | * @offset: Register offset in SLCR block | |
59 | * | |
60 | * Return: a negative value on error, 0 on success | |
61 | */ | |
62 | static int zynq_slcr_read(u32 *val, u32 offset) | |
63 | { | |
3329659d | 64 | return regmap_read(zynq_slcr_regmap, offset, val); |
871c6971 MS |
65 | } |
66 | ||
56880073 MS |
67 | /** |
68 | * zynq_slcr_unlock - Unlock SLCR registers | |
69 | * | |
70 | * Return: a negative value on error, 0 on success | |
71 | */ | |
72 | static inline int zynq_slcr_unlock(void) | |
73 | { | |
74 | zynq_slcr_write(SLCR_UNLOCK_MAGIC, SLCR_UNLOCK_OFFSET); | |
75 | ||
76 | return 0; | |
77 | } | |
78 | ||
00f7dc63 MS |
79 | /** |
80 | * zynq_slcr_get_device_id - Read device code id | |
81 | * | |
82 | * Return: Device code id | |
83 | */ | |
84 | u32 zynq_slcr_get_device_id(void) | |
85 | { | |
86 | u32 val; | |
87 | ||
88 | zynq_slcr_read(&val, SLCR_PSS_IDCODE); | |
89 | val >>= SLCR_PSS_IDCODE_DEVICE_SHIFT; | |
90 | val &= SLCR_PSS_IDCODE_DEVICE_MASK; | |
91 | ||
92 | return val; | |
93 | } | |
94 | ||
96790f0a | 95 | /** |
64e68617 JC |
96 | * zynq_slcr_system_restart - Restart the entire system. |
97 | * | |
98 | * @nb: Pointer to restart notifier block (unused) | |
99 | * @action: Reboot mode (unused) | |
100 | * @data: Restart handler private data (unused) | |
101 | * | |
102 | * Return: 0 always | |
96790f0a | 103 | */ |
64e68617 JC |
104 | static |
105 | int zynq_slcr_system_restart(struct notifier_block *nb, | |
106 | unsigned long action, void *data) | |
96790f0a MS |
107 | { |
108 | u32 reboot; | |
109 | ||
96790f0a MS |
110 | /* |
111 | * Clear 0x0F000000 bits of reboot status register to workaround | |
112 | * the FSBL not loading the bitstream after soft-reboot | |
113 | * This is a temporary solution until we know more. | |
114 | */ | |
871c6971 MS |
115 | zynq_slcr_read(&reboot, SLCR_REBOOT_STATUS_OFFSET); |
116 | zynq_slcr_write(reboot & 0xF0FFFFFF, SLCR_REBOOT_STATUS_OFFSET); | |
117 | zynq_slcr_write(1, SLCR_PS_RST_CTRL_OFFSET); | |
64e68617 | 118 | return 0; |
96790f0a MS |
119 | } |
120 | ||
64e68617 JC |
121 | static struct notifier_block zynq_slcr_restart_nb = { |
122 | .notifier_call = zynq_slcr_system_restart, | |
123 | .priority = 192, | |
124 | }; | |
125 | ||
aa7eb2bb MS |
126 | /** |
127 | * zynq_slcr_cpu_start - Start cpu | |
128 | * @cpu: cpu number | |
129 | */ | |
130 | void zynq_slcr_cpu_start(int cpu) | |
131 | { | |
871c6971 MS |
132 | u32 reg; |
133 | ||
134 | zynq_slcr_read(®, SLCR_A9_CPU_RST_CTRL_OFFSET); | |
3db9e860 | 135 | reg &= ~(SLCR_A9_CPU_RST << cpu); |
871c6971 | 136 | zynq_slcr_write(reg, SLCR_A9_CPU_RST_CTRL_OFFSET); |
3db9e860 | 137 | reg &= ~(SLCR_A9_CPU_CLKSTOP << cpu); |
871c6971 | 138 | zynq_slcr_write(reg, SLCR_A9_CPU_RST_CTRL_OFFSET); |
50c7960a SB |
139 | |
140 | zynq_slcr_cpu_state_write(cpu, false); | |
aa7eb2bb MS |
141 | } |
142 | ||
143 | /** | |
144 | * zynq_slcr_cpu_stop - Stop cpu | |
145 | * @cpu: cpu number | |
146 | */ | |
147 | void zynq_slcr_cpu_stop(int cpu) | |
148 | { | |
871c6971 MS |
149 | u32 reg; |
150 | ||
151 | zynq_slcr_read(®, SLCR_A9_CPU_RST_CTRL_OFFSET); | |
3db9e860 | 152 | reg |= (SLCR_A9_CPU_CLKSTOP | SLCR_A9_CPU_RST) << cpu; |
871c6971 | 153 | zynq_slcr_write(reg, SLCR_A9_CPU_RST_CTRL_OFFSET); |
aa7eb2bb MS |
154 | } |
155 | ||
64b889b3 | 156 | /** |
50c7960a SB |
157 | * zynq_slcr_cpu_state - Read/write cpu state |
158 | * @cpu: cpu number | |
016f4dca | 159 | * |
50c7960a SB |
160 | * SLCR_REBOOT_STATUS save upper 2 bits (31/30 cpu states for cpu0 and cpu1) |
161 | * 0 means cpu is running, 1 cpu is going to die. | |
162 | * | |
163 | * Return: true if cpu is running, false if cpu is going to die | |
164 | */ | |
165 | bool zynq_slcr_cpu_state_read(int cpu) | |
166 | { | |
167 | u32 state; | |
168 | ||
169 | state = readl(zynq_slcr_base + SLCR_REBOOT_STATUS_OFFSET); | |
170 | state &= 1 << (31 - cpu); | |
171 | ||
172 | return !state; | |
173 | } | |
174 | ||
175 | /** | |
176 | * zynq_slcr_cpu_state - Read/write cpu state | |
177 | * @cpu: cpu number | |
178 | * @die: cpu state - true if cpu is going to die | |
179 | * | |
180 | * SLCR_REBOOT_STATUS save upper 2 bits (31/30 cpu states for cpu0 and cpu1) | |
181 | * 0 means cpu is running, 1 cpu is going to die. | |
182 | */ | |
183 | void zynq_slcr_cpu_state_write(int cpu, bool die) | |
184 | { | |
185 | u32 state, mask; | |
186 | ||
187 | state = readl(zynq_slcr_base + SLCR_REBOOT_STATUS_OFFSET); | |
188 | mask = 1 << (31 - cpu); | |
189 | if (die) | |
190 | state |= mask; | |
191 | else | |
192 | state &= ~mask; | |
193 | writel(state, zynq_slcr_base + SLCR_REBOOT_STATUS_OFFSET); | |
194 | } | |
195 | ||
016f4dca MS |
196 | /** |
197 | * zynq_early_slcr_init - Early slcr init function | |
198 | * | |
199 | * Return: 0 on success, negative errno otherwise. | |
200 | * | |
201 | * Called very early during boot from platform code to unlock SLCR. | |
202 | */ | |
203 | int __init zynq_early_slcr_init(void) | |
64b889b3 MS |
204 | { |
205 | struct device_node *np; | |
206 | ||
207 | np = of_find_compatible_node(NULL, NULL, "xlnx,zynq-slcr"); | |
208 | if (!np) { | |
209 | pr_err("%s: no slcr node found\n", __func__); | |
210 | BUG(); | |
211 | } | |
212 | ||
213 | zynq_slcr_base = of_iomap(np, 0); | |
214 | if (!zynq_slcr_base) { | |
215 | pr_err("%s: Unable to map I/O memory\n", __func__); | |
216 | BUG(); | |
217 | } | |
218 | ||
5e218280 ST |
219 | np->data = (__force void *)zynq_slcr_base; |
220 | ||
3329659d MS |
221 | zynq_slcr_regmap = syscon_regmap_lookup_by_compatible("xlnx,zynq-slcr"); |
222 | if (IS_ERR(zynq_slcr_regmap)) { | |
223 | pr_err("%s: failed to find zynq-slcr\n", __func__); | |
224 | return -ENODEV; | |
225 | } | |
226 | ||
64b889b3 | 227 | /* unlock the SLCR so that registers can be changed */ |
56880073 | 228 | zynq_slcr_unlock(); |
64b889b3 | 229 | |
64e68617 JC |
230 | register_restart_handler(&zynq_slcr_restart_nb); |
231 | ||
64b889b3 MS |
232 | pr_info("%s mapped to %p\n", np->name, zynq_slcr_base); |
233 | ||
64b889b3 MS |
234 | of_node_put(np); |
235 | ||
236 | return 0; | |
237 | } |