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64b889b3 MS |
1 | /* |
2 | * Xilinx SLCR driver | |
3 | * | |
4 | * Copyright (c) 2011-2013 Xilinx Inc. | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or | |
7 | * modify it under the terms of the GNU General Public License | |
8 | * as published by the Free Software Foundation; either version | |
9 | * 2 of the License, or (at your option) any later version. | |
10 | * | |
11 | * You should have received a copy of the GNU General Public | |
12 | * License along with this program; if not, write to the Free | |
13 | * Software Foundation, Inc., 675 Mass Ave, Cambridge, MA | |
14 | * 02139, USA. | |
15 | */ | |
16 | ||
64b889b3 | 17 | #include <linux/io.h> |
64b889b3 | 18 | #include <linux/of_address.h> |
64b889b3 MS |
19 | #include <linux/clk/zynq.h> |
20 | #include "common.h" | |
21 | ||
22 | #define SLCR_UNLOCK_MAGIC 0xDF0D | |
23 | #define SLCR_UNLOCK 0x8 /* SCLR unlock register */ | |
24 | ||
96790f0a | 25 | #define SLCR_PS_RST_CTRL_OFFSET 0x200 /* PS Software Reset Control */ |
aa7eb2bb MS |
26 | |
27 | #define SLCR_A9_CPU_CLKSTOP 0x10 | |
28 | #define SLCR_A9_CPU_RST 0x1 | |
29 | ||
30 | #define SLCR_A9_CPU_RST_CTRL 0x244 /* CPU Software Reset Control */ | |
96790f0a MS |
31 | #define SLCR_REBOOT_STATUS 0x258 /* PS Reboot Status */ |
32 | ||
64b889b3 MS |
33 | void __iomem *zynq_slcr_base; |
34 | ||
96790f0a MS |
35 | /** |
36 | * zynq_slcr_system_reset - Reset the entire system. | |
37 | */ | |
38 | void zynq_slcr_system_reset(void) | |
39 | { | |
40 | u32 reboot; | |
41 | ||
42 | /* | |
43 | * Unlock the SLCR then reset the system. | |
44 | * Note that this seems to require raw i/o | |
45 | * functions or there's a lockup? | |
46 | */ | |
47 | writel(SLCR_UNLOCK_MAGIC, zynq_slcr_base + SLCR_UNLOCK); | |
48 | ||
49 | /* | |
50 | * Clear 0x0F000000 bits of reboot status register to workaround | |
51 | * the FSBL not loading the bitstream after soft-reboot | |
52 | * This is a temporary solution until we know more. | |
53 | */ | |
54 | reboot = readl(zynq_slcr_base + SLCR_REBOOT_STATUS); | |
55 | writel(reboot & 0xF0FFFFFF, zynq_slcr_base + SLCR_REBOOT_STATUS); | |
56 | writel(1, zynq_slcr_base + SLCR_PS_RST_CTRL_OFFSET); | |
57 | } | |
58 | ||
aa7eb2bb MS |
59 | /** |
60 | * zynq_slcr_cpu_start - Start cpu | |
61 | * @cpu: cpu number | |
62 | */ | |
63 | void zynq_slcr_cpu_start(int cpu) | |
64 | { | |
65 | /* enable CPUn */ | |
66 | writel(SLCR_A9_CPU_CLKSTOP << cpu, | |
67 | zynq_slcr_base + SLCR_A9_CPU_RST_CTRL); | |
68 | /* enable CLK for CPUn */ | |
69 | writel(0x0 << cpu, zynq_slcr_base + SLCR_A9_CPU_RST_CTRL); | |
70 | } | |
71 | ||
72 | /** | |
73 | * zynq_slcr_cpu_stop - Stop cpu | |
74 | * @cpu: cpu number | |
75 | */ | |
76 | void zynq_slcr_cpu_stop(int cpu) | |
77 | { | |
78 | /* stop CLK and reset CPUn */ | |
79 | writel((SLCR_A9_CPU_CLKSTOP | SLCR_A9_CPU_RST) << cpu, | |
80 | zynq_slcr_base + SLCR_A9_CPU_RST_CTRL); | |
81 | } | |
82 | ||
64b889b3 MS |
83 | /** |
84 | * zynq_slcr_init | |
85 | * Returns 0 on success, negative errno otherwise. | |
86 | * | |
87 | * Called early during boot from platform code to remap SLCR area. | |
88 | */ | |
89 | int __init zynq_slcr_init(void) | |
90 | { | |
91 | struct device_node *np; | |
92 | ||
93 | np = of_find_compatible_node(NULL, NULL, "xlnx,zynq-slcr"); | |
94 | if (!np) { | |
95 | pr_err("%s: no slcr node found\n", __func__); | |
96 | BUG(); | |
97 | } | |
98 | ||
99 | zynq_slcr_base = of_iomap(np, 0); | |
100 | if (!zynq_slcr_base) { | |
101 | pr_err("%s: Unable to map I/O memory\n", __func__); | |
102 | BUG(); | |
103 | } | |
104 | ||
105 | /* unlock the SLCR so that registers can be changed */ | |
106 | writel(SLCR_UNLOCK_MAGIC, zynq_slcr_base + SLCR_UNLOCK); | |
107 | ||
108 | pr_info("%s mapped to %p\n", np->name, zynq_slcr_base); | |
109 | ||
30e1e285 | 110 | zynq_clock_init(zynq_slcr_base); |
64b889b3 MS |
111 | |
112 | of_node_put(np); | |
113 | ||
114 | return 0; | |
115 | } |