[deliverable/linux.git] / arch / arm / mach-zynq / timer.c

/*
 * This file contains driver for the Xilinx PS Timer Counter IP.
 *
 *  Copyright (C) 2011 Xilinx
 *
 * based on arch/mips/kernel/time.c timer driver
 *
 * This software is licensed under the terms of the GNU General Public
 * License version 2, as published by the Free Software Foundation, and
 * may be copied, distributed, and modified under those terms.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/types.h>
#include <linux/clocksource.h>
#include <linux/clockchips.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/of_irq.h>
#include <linux/slab.h>
#include <linux/clk-provider.h>

#include "common.h"

/*
 * Timer Register Offset Definitions of Timer 1, Increment base address by 4
 * and use same offsets for Timer 2
 */
#define XTTCPSS_CLK_CNTRL_OFFSET	0x00 /* Clock Control Reg, RW */
#define XTTCPSS_CNT_CNTRL_OFFSET	0x0C /* Counter Control Reg, RW */
#define XTTCPSS_COUNT_VAL_OFFSET	0x18 /* Counter Value Reg, RO */
#define XTTCPSS_INTR_VAL_OFFSET		0x24 /* Interval Count Reg, RW */
#define XTTCPSS_MATCH_1_OFFSET		0x30 /* Match 1 Value Reg, RW */
#define XTTCPSS_MATCH_2_OFFSET		0x3C /* Match 2 Value Reg, RW */
#define XTTCPSS_MATCH_3_OFFSET		0x48 /* Match 3 Value Reg, RW */
#define XTTCPSS_ISR_OFFSET		0x54 /* Interrupt Status Reg, RO */
#define XTTCPSS_IER_OFFSET		0x60 /* Interrupt Enable Reg, RW */

#define XTTCPSS_CNT_CNTRL_DISABLE_MASK	0x1

/* Setup the timers to use pre-scaling, using a fixed value for now that will
 * work across most input frequency, but it may need to be more dynamic
 */
#define PRESCALE_EXPONENT	11	/* 2 ^ PRESCALE_EXPONENT = PRESCALE */
#define PRESCALE		2048	/* The exponent must match this */
#define CLK_CNTRL_PRESCALE	((PRESCALE_EXPONENT - 1) << 1)
#define CLK_CNTRL_PRESCALE_EN	1
#define CNT_CNTRL_RESET		(1<<4)

/**
 * struct xttcpss_timer - This definition defines local timer structure
 *
 * @base_addr:	Base address of timer
 **/
struct xttcpss_timer {
	void __iomem	*base_addr;
};

struct xttcpss_timer_clocksource {
	struct xttcpss_timer	xttc;
	struct clocksource	cs;
};

#define to_xttcpss_timer_clksrc(x) \
		container_of(x, struct xttcpss_timer_clocksource, cs)

struct xttcpss_timer_clockevent {
	struct xttcpss_timer		xttc;
	struct clock_event_device	ce;
	struct clk			*clk;
};

#define to_xttcpss_timer_clkevent(x) \
		container_of(x, struct xttcpss_timer_clockevent, ce)

/**
 * xttcpss_set_interval - Set the timer interval value
 *
 * @timer:	Pointer to the timer instance
 * @cycles:	Timer interval ticks
 **/
static void xttcpss_set_interval(struct xttcpss_timer *timer,
					unsigned long cycles)
{
	u32 ctrl_reg;

	/* Disable the counter, set the counter value  and re-enable counter */
	ctrl_reg = __raw_readl(timer->base_addr + XTTCPSS_CNT_CNTRL_OFFSET);
	ctrl_reg |= XTTCPSS_CNT_CNTRL_DISABLE_MASK;
	__raw_writel(ctrl_reg, timer->base_addr + XTTCPSS_CNT_CNTRL_OFFSET);

	__raw_writel(cycles, timer->base_addr + XTTCPSS_INTR_VAL_OFFSET);

	/* Reset the counter (0x10) so that it starts from 0, one-shot
	   mode makes this needed for timing to be right. */
	ctrl_reg |= CNT_CNTRL_RESET;
	ctrl_reg &= ~XTTCPSS_CNT_CNTRL_DISABLE_MASK;
	__raw_writel(ctrl_reg, timer->base_addr + XTTCPSS_CNT_CNTRL_OFFSET);
}

/**
 * xttcpss_clock_event_interrupt - Clock event timer interrupt handler
 *
 * @irq:	IRQ number of the Timer
 * @dev_id:	void pointer to the xttcpss_timer instance
 *
 * returns: Always IRQ_HANDLED - success
 **/
static irqreturn_t xttcpss_clock_event_interrupt(int irq, void *dev_id)
{
	struct xttcpss_timer_clockevent *xttce = dev_id;
	struct xttcpss_timer *timer = &xttce->xttc;

	/* Acknowledge the interrupt and call event handler */
	__raw_writel(__raw_readl(timer->base_addr + XTTCPSS_ISR_OFFSET),
			timer->base_addr + XTTCPSS_ISR_OFFSET);

	xttce->ce.event_handler(&xttce->ce);

	return IRQ_HANDLED;
}

/**
 * __xttc_clocksource_read - Reads the timer counter register
 *
 * returns: Current timer counter register value
 **/
static cycle_t __xttc_clocksource_read(struct clocksource *cs)
{
	struct xttcpss_timer *timer = &to_xttcpss_timer_clksrc(cs)->xttc;

	return (cycle_t)__raw_readl(timer->base_addr +
				XTTCPSS_COUNT_VAL_OFFSET);
}

/**
 * xttcpss_set_next_event - Sets the time interval for next event
 *
 * @cycles:	Timer interval ticks
 * @evt:	Address of clock event instance
 *
 * returns: Always 0 - success
 **/
static int xttcpss_set_next_event(unsigned long cycles,
					struct clock_event_device *evt)
{
	struct xttcpss_timer_clockevent *xttce = to_xttcpss_timer_clkevent(evt);
	struct xttcpss_timer *timer = &xttce->xttc;

	xttcpss_set_interval(timer, cycles);
	return 0;
}

/**
 * xttcpss_set_mode - Sets the mode of timer
 *
 * @mode:	Mode to be set
 * @evt:	Address of clock event instance
 **/
static void xttcpss_set_mode(enum clock_event_mode mode,
					struct clock_event_device *evt)
{
	struct xttcpss_timer_clockevent *xttce = to_xttcpss_timer_clkevent(evt);
	struct xttcpss_timer *timer = &xttce->xttc;
	u32 ctrl_reg;

	switch (mode) {
	case CLOCK_EVT_MODE_PERIODIC:
		xttcpss_set_interval(timer,
				     DIV_ROUND_CLOSEST(clk_get_rate(xttce->clk),
						       PRESCALE * HZ));
		break;
	case CLOCK_EVT_MODE_ONESHOT:
	case CLOCK_EVT_MODE_UNUSED:
	case CLOCK_EVT_MODE_SHUTDOWN:
		ctrl_reg = __raw_readl(timer->base_addr +
					XTTCPSS_CNT_CNTRL_OFFSET);
		ctrl_reg |= XTTCPSS_CNT_CNTRL_DISABLE_MASK;
		__raw_writel(ctrl_reg,
				timer->base_addr + XTTCPSS_CNT_CNTRL_OFFSET);
		break;
	case CLOCK_EVT_MODE_RESUME:
		ctrl_reg = __raw_readl(timer->base_addr +
					XTTCPSS_CNT_CNTRL_OFFSET);
		ctrl_reg &= ~XTTCPSS_CNT_CNTRL_DISABLE_MASK;
		__raw_writel(ctrl_reg,
				timer->base_addr + XTTCPSS_CNT_CNTRL_OFFSET);
		break;
	}
}

static void __init zynq_ttc_setup_clocksource(struct device_node *np,
					     void __iomem *base)
{
	struct xttcpss_timer_clocksource *ttccs;
	struct clk *clk;
	int err;
	u32 reg;

	ttccs = kzalloc(sizeof(*ttccs), GFP_KERNEL);
	if (WARN_ON(!ttccs))
		return;

	err = of_property_read_u32(np, "reg", &reg);
	if (WARN_ON(err))
		return;

	clk = of_clk_get_by_name(np, "cpu_1x");
	if (WARN_ON(IS_ERR(clk)))
		return;

	err = clk_prepare_enable(clk);
	if (WARN_ON(err))
		return;

	ttccs->xttc.base_addr = base + reg * 4;

	ttccs->cs.name = np->name;
	ttccs->cs.rating = 200;
	ttccs->cs.read = __xttc_clocksource_read;
	ttccs->cs.mask = CLOCKSOURCE_MASK(16);
	ttccs->cs.flags = CLOCK_SOURCE_IS_CONTINUOUS;

	__raw_writel(0x0,  ttccs->xttc.base_addr + XTTCPSS_IER_OFFSET);
	__raw_writel(CLK_CNTRL_PRESCALE | CLK_CNTRL_PRESCALE_EN,
		     ttccs->xttc.base_addr + XTTCPSS_CLK_CNTRL_OFFSET);
	__raw_writel(CNT_CNTRL_RESET,
		     ttccs->xttc.base_addr + XTTCPSS_CNT_CNTRL_OFFSET);

	err = clocksource_register_hz(&ttccs->cs, clk_get_rate(clk) / PRESCALE);
	if (WARN_ON(err))
		return;
}

static void __init zynq_ttc_setup_clockevent(struct device_node *np,
					    void __iomem *base)
{
	struct xttcpss_timer_clockevent *ttcce;
	int err, irq;
	u32 reg;

	ttcce = kzalloc(sizeof(*ttcce), GFP_KERNEL);
	if (WARN_ON(!ttcce))
		return;

	err = of_property_read_u32(np, "reg", &reg);
	if (WARN_ON(err))
		return;

	ttcce->xttc.base_addr = base + reg * 4;

	ttcce->clk = of_clk_get_by_name(np, "cpu_1x");
	if (WARN_ON(IS_ERR(ttcce->clk)))
		return;

	err = clk_prepare_enable(ttcce->clk);
	if (WARN_ON(err))
		return;

	irq = irq_of_parse_and_map(np, 0);
	if (WARN_ON(!irq))
		return;

	ttcce->ce.name = np->name;
	ttcce->ce.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT;
	ttcce->ce.set_next_event = xttcpss_set_next_event;
	ttcce->ce.set_mode = xttcpss_set_mode;
	ttcce->ce.rating = 200;
	ttcce->ce.irq = irq;

	__raw_writel(0x23, ttcce->xttc.base_addr + XTTCPSS_CNT_CNTRL_OFFSET);
	__raw_writel(CLK_CNTRL_PRESCALE | CLK_CNTRL_PRESCALE_EN,
		     ttcce->xttc.base_addr + XTTCPSS_CLK_CNTRL_OFFSET);
	__raw_writel(0x1,  ttcce->xttc.base_addr + XTTCPSS_IER_OFFSET);

	err = request_irq(irq, xttcpss_clock_event_interrupt, IRQF_TIMER,
			  np->name, ttcce);
	if (WARN_ON(err))
		return;

	clockevents_config_and_register(&ttcce->ce,
					clk_get_rate(ttcce->clk) / PRESCALE,
					1, 0xfffe);
}

static const __initconst struct of_device_id zynq_ttc_match[] = {
	{ .compatible = "xlnx,ttc-counter-clocksource",
		.data = zynq_ttc_setup_clocksource, },
	{ .compatible = "xlnx,ttc-counter-clockevent",
		.data = zynq_ttc_setup_clockevent, },
	{}
};

/**
 * xttcpss_timer_init - Initialize the timer
 *
 * Initializes the timer hardware and register the clock source and clock event
 * timers with Linux kernal timer framework
 **/
void __init xttcpss_timer_init(void)
{
	struct device_node *np;

	for_each_compatible_node(np, NULL, "xlnx,ttc") {
		struct device_node *np_chld;
		void __iomem *base;

		base = of_iomap(np, 0);
		if (WARN_ON(!base))
			return;

		for_each_available_child_of_node(np, np_chld) {
			int (*cb)(struct device_node *np, void __iomem *base);
			const struct of_device_id *match;

			match = of_match_node(zynq_ttc_match, np_chld);
			if (match) {
				cb = match->data;
				cb(np_chld, base);
			}
		}
	}
}
Commit	Line	Data
b85a3ef4 JL	1	/*
	2	* This file contains driver for the Xilinx PS Timer Counter IP.
	3	*
	4	* Copyright (C) 2011 Xilinx
	5	*
	6	* based on arch/mips/kernel/time.c timer driver
	7	*
	8	* This software is licensed under the terms of the GNU General Public
	9	* License version 2, as published by the Free Software Foundation, and
	10	* may be copied, distributed, and modified under those terms.
	11	*
	12	* This program is distributed in the hope that it will be useful,
	13	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	14	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	15	* GNU General Public License for more details.
	16	*/
	17
	18	#include <linux/kernel.h>
	19	#include <linux/init.h>
	20	#include <linux/interrupt.h>
	21	#include <linux/irq.h>
	22	#include <linux/types.h>
	23	#include <linux/clocksource.h>
	24	#include <linux/clockchips.h>
	25	#include <linux/io.h>
91dc985c JC	26	#include <linux/of.h>
	27	#include <linux/of_address.h>
	28	#include <linux/of_irq.h>
	29	#include <linux/slab.h>
	30	#include <linux/clk-provider.h>
b85a3ef4	31
b85a3ef4 JL	32	#include "common.h"
b85a3ef4 JL	33
b85a3ef4 JL	34	/*
	35	* Timer Register Offset Definitions of Timer 1, Increment base address by 4
	36	* and use same offsets for Timer 2
	37	*/
	38	#define XTTCPSS_CLK_CNTRL_OFFSET 0x00 /* Clock Control Reg, RW */
	39	#define XTTCPSS_CNT_CNTRL_OFFSET 0x0C /* Counter Control Reg, RW */
	40	#define XTTCPSS_COUNT_VAL_OFFSET 0x18 /* Counter Value Reg, RO */
	41	#define XTTCPSS_INTR_VAL_OFFSET 0x24 /* Interval Count Reg, RW */
	42	#define XTTCPSS_MATCH_1_OFFSET 0x30 /* Match 1 Value Reg, RW */
	43	#define XTTCPSS_MATCH_2_OFFSET 0x3C /* Match 2 Value Reg, RW */
	44	#define XTTCPSS_MATCH_3_OFFSET 0x48 /* Match 3 Value Reg, RW */
	45	#define XTTCPSS_ISR_OFFSET 0x54 /* Interrupt Status Reg, RO */
	46	#define XTTCPSS_IER_OFFSET 0x60 /* Interrupt Enable Reg, RW */
	47
	48	#define XTTCPSS_CNT_CNTRL_DISABLE_MASK 0x1
	49
91dc985c JC	50	/* Setup the timers to use pre-scaling, using a fixed value for now that will
	51	* work across most input frequency, but it may need to be more dynamic
	52	*/
	53	#define PRESCALE_EXPONENT 11 /* 2 ^ PRESCALE_EXPONENT = PRESCALE */
	54	#define PRESCALE 2048 /* The exponent must match this */
	55	#define CLK_CNTRL_PRESCALE ((PRESCALE_EXPONENT - 1) << 1)
	56	#define CLK_CNTRL_PRESCALE_EN 1
	57	#define CNT_CNTRL_RESET (1<<4)
b85a3ef4 JL	58
	59	/**
	60	* struct xttcpss_timer - This definition defines local timer structure
	61	*
	62	* @base_addr: Base address of timer
	63	**/
	64	struct xttcpss_timer {
91dc985c JC	65	void __iomem *base_addr;
	66	};
	67
	68	struct xttcpss_timer_clocksource {
	69	struct xttcpss_timer xttc;
	70	struct clocksource cs;
b85a3ef4 JL	71	};
b85a3ef4 JL	72
91dc985c JC	73	#define to_xttcpss_timer_clksrc(x) \
	74	container_of(x, struct xttcpss_timer_clocksource, cs)
	75
	76	struct xttcpss_timer_clockevent {
	77	struct xttcpss_timer xttc;
	78	struct clock_event_device ce;
	79	struct clk *clk;
	80	};
	81
	82	#define to_xttcpss_timer_clkevent(x) \
	83	container_of(x, struct xttcpss_timer_clockevent, ce)
b85a3ef4 JL	84
	85	/**
	86	* xttcpss_set_interval - Set the timer interval value
	87	*
	88	* @timer: Pointer to the timer instance
	89	* @cycles: Timer interval ticks
	90	**/
	91	static void xttcpss_set_interval(struct xttcpss_timer *timer,
	92	unsigned long cycles)
	93	{
	94	u32 ctrl_reg;
	95
	96	/* Disable the counter, set the counter value and re-enable counter */
	97	ctrl_reg = __raw_readl(timer->base_addr + XTTCPSS_CNT_CNTRL_OFFSET);
	98	ctrl_reg \|= XTTCPSS_CNT_CNTRL_DISABLE_MASK;
	99	__raw_writel(ctrl_reg, timer->base_addr + XTTCPSS_CNT_CNTRL_OFFSET);
	100
	101	__raw_writel(cycles, timer->base_addr + XTTCPSS_INTR_VAL_OFFSET);
	102
	103	/* Reset the counter (0x10) so that it starts from 0, one-shot
	104	mode makes this needed for timing to be right. */
91dc985c	105	ctrl_reg \|= CNT_CNTRL_RESET;
b85a3ef4 JL	106	ctrl_reg &= ~XTTCPSS_CNT_CNTRL_DISABLE_MASK;
	107	__raw_writel(ctrl_reg, timer->base_addr + XTTCPSS_CNT_CNTRL_OFFSET);
	108	}
	109
	110	/**
	111	* xttcpss_clock_event_interrupt - Clock event timer interrupt handler
	112	*
	113	* @irq: IRQ number of the Timer
	114	* @dev_id: void pointer to the xttcpss_timer instance
	115	*
	116	* returns: Always IRQ_HANDLED - success
	117	**/
	118	static irqreturn_t xttcpss_clock_event_interrupt(int irq, void *dev_id)
	119	{
91dc985c JC	120	struct xttcpss_timer_clockevent *xttce = dev_id;
91dc985c JC	121	struct xttcpss_timer *timer = &xttce->xttc;
b85a3ef4 JL	122
	123	/* Acknowledge the interrupt and call event handler */
	124	__raw_writel(__raw_readl(timer->base_addr + XTTCPSS_ISR_OFFSET),
	125	timer->base_addr + XTTCPSS_ISR_OFFSET);
	126
91dc985c	127	xttce->ce.event_handler(&xttce->ce);
b85a3ef4 JL	128
	129	return IRQ_HANDLED;
	130	}
	131
b85a3ef4	132	/**
91dc985c	133	* __xttc_clocksource_read - Reads the timer counter register
b85a3ef4 JL	134	*
	135	* returns: Current timer counter register value
	136	**/
91dc985c	137	static cycle_t __xttc_clocksource_read(struct clocksource *cs)
b85a3ef4	138	{
91dc985c	139	struct xttcpss_timer *timer = &to_xttcpss_timer_clksrc(cs)->xttc;
b85a3ef4 JL	140
	141	return (cycle_t)__raw_readl(timer->base_addr +
	142	XTTCPSS_COUNT_VAL_OFFSET);
	143	}
	144
b85a3ef4 JL	145	/**
	146	* xttcpss_set_next_event - Sets the time interval for next event
	147	*
	148	* @cycles: Timer interval ticks
	149	* @evt: Address of clock event instance
	150	*
	151	* returns: Always 0 - success
	152	**/
	153	static int xttcpss_set_next_event(unsigned long cycles,
	154	struct clock_event_device *evt)
	155	{
91dc985c JC	156	struct xttcpss_timer_clockevent *xttce = to_xttcpss_timer_clkevent(evt);
91dc985c JC	157	struct xttcpss_timer *timer = &xttce->xttc;
b85a3ef4 JL	158
	159	xttcpss_set_interval(timer, cycles);
	160	return 0;
	161	}
	162
	163	/**
	164	* xttcpss_set_mode - Sets the mode of timer
	165	*
	166	* @mode: Mode to be set
	167	* @evt: Address of clock event instance
	168	**/
	169	static void xttcpss_set_mode(enum clock_event_mode mode,
	170	struct clock_event_device *evt)
	171	{
91dc985c JC	172	struct xttcpss_timer_clockevent *xttce = to_xttcpss_timer_clkevent(evt);
91dc985c JC	173	struct xttcpss_timer *timer = &xttce->xttc;
b85a3ef4 JL	174	u32 ctrl_reg;
	175
	176	switch (mode) {
	177	case CLOCK_EVT_MODE_PERIODIC:
91dc985c JC	178	xttcpss_set_interval(timer,
	179	DIV_ROUND_CLOSEST(clk_get_rate(xttce->clk),
	180	PRESCALE * HZ));
b85a3ef4 JL	181	break;
	182	case CLOCK_EVT_MODE_ONESHOT:
	183	case CLOCK_EVT_MODE_UNUSED:
	184	case CLOCK_EVT_MODE_SHUTDOWN:
	185	ctrl_reg = __raw_readl(timer->base_addr +
	186	XTTCPSS_CNT_CNTRL_OFFSET);
	187	ctrl_reg \|= XTTCPSS_CNT_CNTRL_DISABLE_MASK;
	188	__raw_writel(ctrl_reg,
	189	timer->base_addr + XTTCPSS_CNT_CNTRL_OFFSET);
	190	break;
	191	case CLOCK_EVT_MODE_RESUME:
	192	ctrl_reg = __raw_readl(timer->base_addr +
	193	XTTCPSS_CNT_CNTRL_OFFSET);
	194	ctrl_reg &= ~XTTCPSS_CNT_CNTRL_DISABLE_MASK;
	195	__raw_writel(ctrl_reg,
	196	timer->base_addr + XTTCPSS_CNT_CNTRL_OFFSET);
	197	break;
	198	}
	199	}
	200
91dc985c JC	201	static void __init zynq_ttc_setup_clocksource(struct device_node *np,
	202	void __iomem *base)
	203	{
	204	struct xttcpss_timer_clocksource *ttccs;
	205	struct clk *clk;
	206	int err;
	207	u32 reg;
	208
	209	ttccs = kzalloc(sizeof(*ttccs), GFP_KERNEL);
	210	if (WARN_ON(!ttccs))
	211	return;
	212
	213	err = of_property_read_u32(np, "reg", &reg);
	214	if (WARN_ON(err))
	215	return;
	216
	217	clk = of_clk_get_by_name(np, "cpu_1x");
	218	if (WARN_ON(IS_ERR(clk)))
	219	return;
	220
	221	err = clk_prepare_enable(clk);
	222	if (WARN_ON(err))
	223	return;
	224
	225	ttccs->xttc.base_addr = base + reg * 4;
	226
	227	ttccs->cs.name = np->name;
	228	ttccs->cs.rating = 200;
	229	ttccs->cs.read = __xttc_clocksource_read;
	230	ttccs->cs.mask = CLOCKSOURCE_MASK(16);
	231	ttccs->cs.flags = CLOCK_SOURCE_IS_CONTINUOUS;
	232
	233	__raw_writel(0x0, ttccs->xttc.base_addr + XTTCPSS_IER_OFFSET);
	234	__raw_writel(CLK_CNTRL_PRESCALE \| CLK_CNTRL_PRESCALE_EN,
	235	ttccs->xttc.base_addr + XTTCPSS_CLK_CNTRL_OFFSET);
	236	__raw_writel(CNT_CNTRL_RESET,
	237	ttccs->xttc.base_addr + XTTCPSS_CNT_CNTRL_OFFSET);
	238
	239	err = clocksource_register_hz(&ttccs->cs, clk_get_rate(clk) / PRESCALE);
	240	if (WARN_ON(err))
	241	return;
	242	}
	243
	244	static void __init zynq_ttc_setup_clockevent(struct device_node *np,
	245	void __iomem *base)
	246	{
	247	struct xttcpss_timer_clockevent *ttcce;
	248	int err, irq;
	249	u32 reg;
	250
	251	ttcce = kzalloc(sizeof(*ttcce), GFP_KERNEL);
	252	if (WARN_ON(!ttcce))
	253	return;
	254
	255	err = of_property_read_u32(np, "reg", &reg);
	256	if (WARN_ON(err))
	257	return;
	258
	259	ttcce->xttc.base_addr = base + reg * 4;
	260
	261	ttcce->clk = of_clk_get_by_name(np, "cpu_1x");
	262	if (WARN_ON(IS_ERR(ttcce->clk)))
	263	return;
	264
265	err = clk_prepare_enable(ttcce->clk);
266	if (WARN_ON(err))
267	return;
268
269	irq = irq_of_parse_and_map(np, 0);
270	if (WARN_ON(!irq))
271	return;
272
273	ttcce->ce.name = np->name;
274	ttcce->ce.features = CLOCK_EVT_FEAT_PERIODIC \| CLOCK_EVT_FEAT_ONESHOT;
275	ttcce->ce.set_next_event = xttcpss_set_next_event;
276	ttcce->ce.set_mode = xttcpss_set_mode;
277	ttcce->ce.rating = 200;
278	ttcce->ce.irq = irq;
279
280	__raw_writel(0x23, ttcce->xttc.base_addr + XTTCPSS_CNT_CNTRL_OFFSET);
281	__raw_writel(CLK_CNTRL_PRESCALE \| CLK_CNTRL_PRESCALE_EN,
282	ttcce->xttc.base_addr + XTTCPSS_CLK_CNTRL_OFFSET);
283	__raw_writel(0x1, ttcce->xttc.base_addr + XTTCPSS_IER_OFFSET);
284
285	err = request_irq(irq, xttcpss_clock_event_interrupt, IRQF_TIMER,
286	np->name, ttcce);
287	if (WARN_ON(err))
288	return;
289
290	clockevents_config_and_register(&ttcce->ce,
291	clk_get_rate(ttcce->clk) / PRESCALE,
292	1, 0xfffe);
293	}
294
295	static const __initconst struct of_device_id zynq_ttc_match[] = {
296	{ .compatible = "xlnx,ttc-counter-clocksource",
297	.data = zynq_ttc_setup_clocksource, },
298	{ .compatible = "xlnx,ttc-counter-clockevent",
299	.data = zynq_ttc_setup_clockevent, },
300	{}
b85a3ef4 JL	301	};
	302
	303	/**
	304	* xttcpss_timer_init - Initialize the timer
	305	*
	306	* Initializes the timer hardware and register the clock source and clock event
	307	* timers with Linux kernal timer framework
	308	**/
03e07595	309	void __init xttcpss_timer_init(void)
b85a3ef4	310	{
91dc985c JC	311	struct device_node *np;
	312
	313	for_each_compatible_node(np, NULL, "xlnx,ttc") {
	314	struct device_node *np_chld;
	315	void __iomem *base;
	316
	317	base = of_iomap(np, 0);
	318	if (WARN_ON(!base))
	319	return;
	320
	321	for_each_available_child_of_node(np, np_chld) {
	322	int (cb)(struct device_node np, void __iomem *base);
	323	const struct of_device_id *match;
	324
	325	match = of_match_node(zynq_ttc_match, np_chld);
	326	if (match) {
	327	cb = match->data;
	328	cb(np_chld, base);
	329	}
	330	}
	331	}
b85a3ef4	332	}