Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | comment "Processor Type" |
2 | ||
1da177e4 LT |
3 | # Select CPU types depending on the architecture selected. This selects |
4 | # which CPUs we support in the kernel image, and the compiler instruction | |
5 | # optimiser behaviour. | |
6 | ||
07e0da78 HC |
7 | # ARM7TDMI |
8 | config CPU_ARM7TDMI | |
9 | bool "Support ARM7TDMI processor" | |
6b237a35 | 10 | depends on !MMU |
07e0da78 HC |
11 | select CPU_32v4T |
12 | select CPU_ABRT_LV4T | |
13 | select CPU_CACHE_V4 | |
b1b3f49c | 14 | select CPU_PABRT_LEGACY |
07e0da78 HC |
15 | help |
16 | A 32-bit RISC microprocessor based on the ARM7 processor core | |
17 | which has no memory control unit and cache. | |
18 | ||
19 | Say Y if you want support for the ARM7TDMI processor. | |
20 | Otherwise, say N. | |
21 | ||
1da177e4 LT |
22 | # ARM720T |
23 | config CPU_ARM720T | |
c750815e | 24 | bool "Support ARM720T processor" if ARCH_INTEGRATOR |
260e98ed | 25 | select CPU_32v4T |
1da177e4 LT |
26 | select CPU_ABRT_LV4T |
27 | select CPU_CACHE_V4 | |
28 | select CPU_CACHE_VIVT | |
f9c21a6e | 29 | select CPU_COPY_V4WT if MMU |
b1b3f49c RK |
30 | select CPU_CP15_MMU |
31 | select CPU_PABRT_LEGACY | |
f9c21a6e | 32 | select CPU_TLB_V4WT if MMU |
1da177e4 LT |
33 | help |
34 | A 32-bit RISC processor with 8kByte Cache, Write Buffer and | |
35 | MMU built around an ARM7TDMI core. | |
36 | ||
37 | Say Y if you want support for the ARM720T processor. | |
38 | Otherwise, say N. | |
39 | ||
b731c311 HC |
40 | # ARM740T |
41 | config CPU_ARM740T | |
42 | bool "Support ARM740T processor" if ARCH_INTEGRATOR | |
6b237a35 | 43 | depends on !MMU |
b731c311 HC |
44 | select CPU_32v4T |
45 | select CPU_ABRT_LV4T | |
46 | select CPU_CACHE_V3 # although the core is v4t | |
47 | select CPU_CP15_MPU | |
b1b3f49c | 48 | select CPU_PABRT_LEGACY |
b731c311 HC |
49 | help |
50 | A 32-bit RISC processor with 8KB cache or 4KB variants, | |
51 | write buffer and MPU(Protection Unit) built around | |
52 | an ARM7TDMI core. | |
53 | ||
54 | Say Y if you want support for the ARM740T processor. | |
55 | Otherwise, say N. | |
56 | ||
43f5f014 HC |
57 | # ARM9TDMI |
58 | config CPU_ARM9TDMI | |
59 | bool "Support ARM9TDMI processor" | |
6b237a35 | 60 | depends on !MMU |
43f5f014 | 61 | select CPU_32v4T |
0f45d7f3 | 62 | select CPU_ABRT_NOMMU |
43f5f014 | 63 | select CPU_CACHE_V4 |
b1b3f49c | 64 | select CPU_PABRT_LEGACY |
43f5f014 HC |
65 | help |
66 | A 32-bit RISC microprocessor based on the ARM9 processor core | |
67 | which has no memory control unit and cache. | |
68 | ||
69 | Say Y if you want support for the ARM9TDMI processor. | |
70 | Otherwise, say N. | |
71 | ||
1da177e4 LT |
72 | # ARM920T |
73 | config CPU_ARM920T | |
c750815e | 74 | bool "Support ARM920T processor" if ARCH_INTEGRATOR |
260e98ed | 75 | select CPU_32v4T |
1da177e4 LT |
76 | select CPU_ABRT_EV4T |
77 | select CPU_CACHE_V4WT | |
78 | select CPU_CACHE_VIVT | |
f9c21a6e | 79 | select CPU_COPY_V4WB if MMU |
b1b3f49c RK |
80 | select CPU_CP15_MMU |
81 | select CPU_PABRT_LEGACY | |
f9c21a6e | 82 | select CPU_TLB_V4WBI if MMU |
1da177e4 LT |
83 | help |
84 | The ARM920T is licensed to be produced by numerous vendors, | |
c768e676 | 85 | and is used in the Cirrus EP93xx and the Samsung S3C2410. |
1da177e4 LT |
86 | |
87 | Say Y if you want support for the ARM920T processor. | |
88 | Otherwise, say N. | |
89 | ||
90 | # ARM922T | |
91 | config CPU_ARM922T | |
92 | bool "Support ARM922T processor" if ARCH_INTEGRATOR | |
260e98ed | 93 | select CPU_32v4T |
1da177e4 LT |
94 | select CPU_ABRT_EV4T |
95 | select CPU_CACHE_V4WT | |
96 | select CPU_CACHE_VIVT | |
f9c21a6e | 97 | select CPU_COPY_V4WB if MMU |
b1b3f49c RK |
98 | select CPU_CP15_MMU |
99 | select CPU_PABRT_LEGACY | |
f9c21a6e | 100 | select CPU_TLB_V4WBI if MMU |
1da177e4 LT |
101 | help |
102 | The ARM922T is a version of the ARM920T, but with smaller | |
103 | instruction and data caches. It is used in Altera's | |
c53c9cf6 | 104 | Excalibur XA device family and Micrel's KS8695 Centaur. |
1da177e4 LT |
105 | |
106 | Say Y if you want support for the ARM922T processor. | |
107 | Otherwise, say N. | |
108 | ||
109 | # ARM925T | |
110 | config CPU_ARM925T | |
b288f75f | 111 | bool "Support ARM925T processor" if ARCH_OMAP1 |
260e98ed | 112 | select CPU_32v4T |
1da177e4 LT |
113 | select CPU_ABRT_EV4T |
114 | select CPU_CACHE_V4WT | |
115 | select CPU_CACHE_VIVT | |
f9c21a6e | 116 | select CPU_COPY_V4WB if MMU |
b1b3f49c RK |
117 | select CPU_CP15_MMU |
118 | select CPU_PABRT_LEGACY | |
f9c21a6e | 119 | select CPU_TLB_V4WBI if MMU |
1da177e4 LT |
120 | help |
121 | The ARM925T is a mix between the ARM920T and ARM926T, but with | |
122 | different instruction and data caches. It is used in TI's OMAP | |
123 | device family. | |
124 | ||
125 | Say Y if you want support for the ARM925T processor. | |
126 | Otherwise, say N. | |
127 | ||
128 | # ARM926T | |
129 | config CPU_ARM926T | |
c750815e | 130 | bool "Support ARM926T processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB |
1da177e4 LT |
131 | select CPU_32v5 |
132 | select CPU_ABRT_EV5TJ | |
133 | select CPU_CACHE_VIVT | |
f9c21a6e | 134 | select CPU_COPY_V4WB if MMU |
b1b3f49c RK |
135 | select CPU_CP15_MMU |
136 | select CPU_PABRT_LEGACY | |
f9c21a6e | 137 | select CPU_TLB_V4WBI if MMU |
1da177e4 LT |
138 | help |
139 | This is a variant of the ARM920. It has slightly different | |
140 | instruction sequences for cache and TLB operations. Curiously, | |
141 | there is no documentation on it at the ARM corporate website. | |
142 | ||
143 | Say Y if you want support for the ARM926T processor. | |
144 | Otherwise, say N. | |
145 | ||
28853ac8 PZ |
146 | # FA526 |
147 | config CPU_FA526 | |
148 | bool | |
149 | select CPU_32v4 | |
150 | select CPU_ABRT_EV4 | |
28853ac8 | 151 | select CPU_CACHE_FA |
b1b3f49c | 152 | select CPU_CACHE_VIVT |
28853ac8 | 153 | select CPU_COPY_FA if MMU |
b1b3f49c RK |
154 | select CPU_CP15_MMU |
155 | select CPU_PABRT_LEGACY | |
28853ac8 PZ |
156 | select CPU_TLB_FA if MMU |
157 | help | |
158 | The FA526 is a version of the ARMv4 compatible processor with | |
159 | Branch Target Buffer, Unified TLB and cache line size 16. | |
160 | ||
161 | Say Y if you want support for the FA526 processor. | |
162 | Otherwise, say N. | |
163 | ||
d60674eb HC |
164 | # ARM940T |
165 | config CPU_ARM940T | |
166 | bool "Support ARM940T processor" if ARCH_INTEGRATOR | |
6b237a35 | 167 | depends on !MMU |
d60674eb | 168 | select CPU_32v4T |
0f45d7f3 | 169 | select CPU_ABRT_NOMMU |
d60674eb HC |
170 | select CPU_CACHE_VIVT |
171 | select CPU_CP15_MPU | |
b1b3f49c | 172 | select CPU_PABRT_LEGACY |
d60674eb HC |
173 | help |
174 | ARM940T is a member of the ARM9TDMI family of general- | |
3cb2fccc | 175 | purpose microprocessors with MPU and separate 4KB |
d60674eb HC |
176 | instruction and 4KB data cases, each with a 4-word line |
177 | length. | |
178 | ||
179 | Say Y if you want support for the ARM940T processor. | |
180 | Otherwise, say N. | |
181 | ||
f37f46eb HC |
182 | # ARM946E-S |
183 | config CPU_ARM946E | |
184 | bool "Support ARM946E-S processor" if ARCH_INTEGRATOR | |
6b237a35 | 185 | depends on !MMU |
f37f46eb | 186 | select CPU_32v5 |
0f45d7f3 | 187 | select CPU_ABRT_NOMMU |
f37f46eb HC |
188 | select CPU_CACHE_VIVT |
189 | select CPU_CP15_MPU | |
b1b3f49c | 190 | select CPU_PABRT_LEGACY |
f37f46eb HC |
191 | help |
192 | ARM946E-S is a member of the ARM9E-S family of high- | |
193 | performance, 32-bit system-on-chip processor solutions. | |
194 | The TCM and ARMv5TE 32-bit instruction set is supported. | |
195 | ||
196 | Say Y if you want support for the ARM946E-S processor. | |
197 | Otherwise, say N. | |
198 | ||
1da177e4 LT |
199 | # ARM1020 - needs validating |
200 | config CPU_ARM1020 | |
c750815e | 201 | bool "Support ARM1020T (rev 0) processor" if ARCH_INTEGRATOR |
1da177e4 LT |
202 | select CPU_32v5 |
203 | select CPU_ABRT_EV4T | |
204 | select CPU_CACHE_V4WT | |
205 | select CPU_CACHE_VIVT | |
f9c21a6e | 206 | select CPU_COPY_V4WB if MMU |
b1b3f49c RK |
207 | select CPU_CP15_MMU |
208 | select CPU_PABRT_LEGACY | |
f9c21a6e | 209 | select CPU_TLB_V4WBI if MMU |
1da177e4 LT |
210 | help |
211 | The ARM1020 is the 32K cached version of the ARM10 processor, | |
212 | with an addition of a floating-point unit. | |
213 | ||
214 | Say Y if you want support for the ARM1020 processor. | |
215 | Otherwise, say N. | |
216 | ||
217 | # ARM1020E - needs validating | |
218 | config CPU_ARM1020E | |
c750815e | 219 | bool "Support ARM1020E processor" if ARCH_INTEGRATOR |
b1b3f49c | 220 | depends on n |
1da177e4 LT |
221 | select CPU_32v5 |
222 | select CPU_ABRT_EV4T | |
223 | select CPU_CACHE_V4WT | |
224 | select CPU_CACHE_VIVT | |
f9c21a6e | 225 | select CPU_COPY_V4WB if MMU |
b1b3f49c RK |
226 | select CPU_CP15_MMU |
227 | select CPU_PABRT_LEGACY | |
f9c21a6e | 228 | select CPU_TLB_V4WBI if MMU |
1da177e4 LT |
229 | |
230 | # ARM1022E | |
231 | config CPU_ARM1022 | |
c750815e | 232 | bool "Support ARM1022E processor" if ARCH_INTEGRATOR |
1da177e4 LT |
233 | select CPU_32v5 |
234 | select CPU_ABRT_EV4T | |
235 | select CPU_CACHE_VIVT | |
f9c21a6e | 236 | select CPU_COPY_V4WB if MMU # can probably do better |
b1b3f49c RK |
237 | select CPU_CP15_MMU |
238 | select CPU_PABRT_LEGACY | |
f9c21a6e | 239 | select CPU_TLB_V4WBI if MMU |
1da177e4 LT |
240 | help |
241 | The ARM1022E is an implementation of the ARMv5TE architecture | |
242 | based upon the ARM10 integer core with a 16KiB L1 Harvard cache, | |
243 | embedded trace macrocell, and a floating-point unit. | |
244 | ||
245 | Say Y if you want support for the ARM1022E processor. | |
246 | Otherwise, say N. | |
247 | ||
248 | # ARM1026EJ-S | |
249 | config CPU_ARM1026 | |
c750815e | 250 | bool "Support ARM1026EJ-S processor" if ARCH_INTEGRATOR |
1da177e4 LT |
251 | select CPU_32v5 |
252 | select CPU_ABRT_EV5T # But need Jazelle, but EV5TJ ignores bit 10 | |
253 | select CPU_CACHE_VIVT | |
f9c21a6e | 254 | select CPU_COPY_V4WB if MMU # can probably do better |
b1b3f49c RK |
255 | select CPU_CP15_MMU |
256 | select CPU_PABRT_LEGACY | |
f9c21a6e | 257 | select CPU_TLB_V4WBI if MMU |
1da177e4 LT |
258 | help |
259 | The ARM1026EJ-S is an implementation of the ARMv5TEJ architecture | |
260 | based upon the ARM10 integer core. | |
261 | ||
262 | Say Y if you want support for the ARM1026EJ-S processor. | |
263 | Otherwise, say N. | |
264 | ||
265 | # SA110 | |
266 | config CPU_SA110 | |
c750815e | 267 | bool "Support StrongARM(R) SA-110 processor" if ARCH_RPC |
1da177e4 LT |
268 | select CPU_32v3 if ARCH_RPC |
269 | select CPU_32v4 if !ARCH_RPC | |
270 | select CPU_ABRT_EV4 | |
271 | select CPU_CACHE_V4WB | |
272 | select CPU_CACHE_VIVT | |
f9c21a6e | 273 | select CPU_COPY_V4WB if MMU |
b1b3f49c RK |
274 | select CPU_CP15_MMU |
275 | select CPU_PABRT_LEGACY | |
f9c21a6e | 276 | select CPU_TLB_V4WB if MMU |
1da177e4 LT |
277 | help |
278 | The Intel StrongARM(R) SA-110 is a 32-bit microprocessor and | |
279 | is available at five speeds ranging from 100 MHz to 233 MHz. | |
280 | More information is available at | |
281 | <http://developer.intel.com/design/strong/sa110.htm>. | |
282 | ||
283 | Say Y if you want support for the SA-110 processor. | |
284 | Otherwise, say N. | |
285 | ||
286 | # SA1100 | |
287 | config CPU_SA1100 | |
288 | bool | |
1da177e4 LT |
289 | select CPU_32v4 |
290 | select CPU_ABRT_EV4 | |
291 | select CPU_CACHE_V4WB | |
292 | select CPU_CACHE_VIVT | |
fefdaa06 | 293 | select CPU_CP15_MMU |
b1b3f49c | 294 | select CPU_PABRT_LEGACY |
f9c21a6e | 295 | select CPU_TLB_V4WB if MMU |
1da177e4 LT |
296 | |
297 | # XScale | |
298 | config CPU_XSCALE | |
299 | bool | |
1da177e4 LT |
300 | select CPU_32v5 |
301 | select CPU_ABRT_EV5T | |
302 | select CPU_CACHE_VIVT | |
fefdaa06 | 303 | select CPU_CP15_MMU |
b1b3f49c | 304 | select CPU_PABRT_LEGACY |
f9c21a6e | 305 | select CPU_TLB_V4WBI if MMU |
1da177e4 | 306 | |
23bdf86a LB |
307 | # XScale Core Version 3 |
308 | config CPU_XSC3 | |
309 | bool | |
23bdf86a LB |
310 | select CPU_32v5 |
311 | select CPU_ABRT_EV5T | |
312 | select CPU_CACHE_VIVT | |
fefdaa06 | 313 | select CPU_CP15_MMU |
b1b3f49c | 314 | select CPU_PABRT_LEGACY |
f9c21a6e | 315 | select CPU_TLB_V4WBI if MMU |
23bdf86a LB |
316 | select IO_36 |
317 | ||
49cbe786 EM |
318 | # Marvell PJ1 (Mohawk) |
319 | config CPU_MOHAWK | |
320 | bool | |
321 | select CPU_32v5 | |
322 | select CPU_ABRT_EV5T | |
49cbe786 | 323 | select CPU_CACHE_VIVT |
b1b3f49c | 324 | select CPU_COPY_V4WB if MMU |
49cbe786 | 325 | select CPU_CP15_MMU |
b1b3f49c | 326 | select CPU_PABRT_LEGACY |
49cbe786 | 327 | select CPU_TLB_V4WBI if MMU |
49cbe786 | 328 | |
e50d6409 AH |
329 | # Feroceon |
330 | config CPU_FEROCEON | |
331 | bool | |
e50d6409 AH |
332 | select CPU_32v5 |
333 | select CPU_ABRT_EV5T | |
334 | select CPU_CACHE_VIVT | |
0ed15071 | 335 | select CPU_COPY_FEROCEON if MMU |
b1b3f49c RK |
336 | select CPU_CP15_MMU |
337 | select CPU_PABRT_LEGACY | |
99c6dc11 | 338 | select CPU_TLB_FEROCEON if MMU |
e50d6409 | 339 | |
d910a0aa TP |
340 | config CPU_FEROCEON_OLD_ID |
341 | bool "Accept early Feroceon cores with an ARM926 ID" | |
342 | depends on CPU_FEROCEON && !CPU_ARM926T | |
343 | default y | |
344 | help | |
345 | This enables the usage of some old Feroceon cores | |
346 | for which the CPU ID is equal to the ARM926 ID. | |
347 | Relevant for Feroceon-1850 and early Feroceon-2850. | |
348 | ||
a4553358 HZ |
349 | # Marvell PJ4 |
350 | config CPU_PJ4 | |
351 | bool | |
a4553358 | 352 | select ARM_THUMBEE |
b1b3f49c | 353 | select CPU_V7 |
a4553358 | 354 | |
1da177e4 LT |
355 | # ARMv6 |
356 | config CPU_V6 | |
c786282e | 357 | bool "Support ARM V6 processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX |
1da177e4 LT |
358 | select CPU_32v6 |
359 | select CPU_ABRT_EV6 | |
360 | select CPU_CACHE_V6 | |
361 | select CPU_CACHE_VIPT | |
b1b3f49c | 362 | select CPU_COPY_V6 if MMU |
fefdaa06 | 363 | select CPU_CP15_MMU |
7b4c965a | 364 | select CPU_HAS_ASID if MMU |
b1b3f49c | 365 | select CPU_PABRT_V6 |
f9c21a6e | 366 | select CPU_TLB_V6 if MMU |
1da177e4 | 367 | |
4a5f79e7 | 368 | # ARMv6k |
e399b1a4 | 369 | config CPU_V6K |
c786282e | 370 | bool "Support ARM V6K processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX |
e399b1a4 | 371 | select CPU_32v6 |
60799c6d | 372 | select CPU_32v6K |
e399b1a4 | 373 | select CPU_ABRT_EV6 |
e399b1a4 RK |
374 | select CPU_CACHE_V6 |
375 | select CPU_CACHE_VIPT | |
b1b3f49c | 376 | select CPU_COPY_V6 if MMU |
e399b1a4 RK |
377 | select CPU_CP15_MMU |
378 | select CPU_HAS_ASID if MMU | |
b1b3f49c | 379 | select CPU_PABRT_V6 |
e399b1a4 | 380 | select CPU_TLB_V6 if MMU |
4a5f79e7 | 381 | |
23688e99 CM |
382 | # ARMv7 |
383 | config CPU_V7 | |
1b504bbe | 384 | bool "Support ARM V7 processor" if ARCH_INTEGRATOR || MACH_REALVIEW_EB || MACH_REALVIEW_PBX |
15490ef8 | 385 | select CPU_32v6K |
23688e99 CM |
386 | select CPU_32v7 |
387 | select CPU_ABRT_EV7 | |
388 | select CPU_CACHE_V7 | |
389 | select CPU_CACHE_VIPT | |
b1b3f49c | 390 | select CPU_COPY_V6 if MMU |
23688e99 | 391 | select CPU_CP15_MMU |
2eb8c82b | 392 | select CPU_HAS_ASID if MMU |
b1b3f49c | 393 | select CPU_PABRT_V7 |
2ccdd1e7 | 394 | select CPU_TLB_V7 if MMU |
23688e99 | 395 | |
1da177e4 LT |
396 | # Figure out what processor architecture version we should be using. |
397 | # This defines the compiler instruction set which depends on the machine type. | |
398 | config CPU_32v3 | |
399 | bool | |
8762df4d | 400 | select CPU_USE_DOMAINS if MMU |
b1b3f49c RK |
401 | select NEEDS_SYSCALL_FOR_CMPXCHG if SMP |
402 | select TLS_REG_EMUL if SMP || !MMU | |
1da177e4 LT |
403 | |
404 | config CPU_32v4 | |
405 | bool | |
8762df4d | 406 | select CPU_USE_DOMAINS if MMU |
b1b3f49c RK |
407 | select NEEDS_SYSCALL_FOR_CMPXCHG if SMP |
408 | select TLS_REG_EMUL if SMP || !MMU | |
1da177e4 | 409 | |
260e98ed LB |
410 | config CPU_32v4T |
411 | bool | |
8762df4d | 412 | select CPU_USE_DOMAINS if MMU |
b1b3f49c RK |
413 | select NEEDS_SYSCALL_FOR_CMPXCHG if SMP |
414 | select TLS_REG_EMUL if SMP || !MMU | |
260e98ed | 415 | |
1da177e4 LT |
416 | config CPU_32v5 |
417 | bool | |
8762df4d | 418 | select CPU_USE_DOMAINS if MMU |
b1b3f49c RK |
419 | select NEEDS_SYSCALL_FOR_CMPXCHG if SMP |
420 | select TLS_REG_EMUL if SMP || !MMU | |
1da177e4 LT |
421 | |
422 | config CPU_32v6 | |
423 | bool | |
8762df4d | 424 | select CPU_USE_DOMAINS if CPU_V6 && MMU |
b1b3f49c | 425 | select TLS_REG_EMUL if !CPU_32v6K && !MMU |
1da177e4 | 426 | |
e399b1a4 | 427 | config CPU_32v6K |
60799c6d | 428 | bool |
1da177e4 | 429 | |
23688e99 CM |
430 | config CPU_32v7 |
431 | bool | |
432 | ||
1da177e4 | 433 | # The abort model |
0f45d7f3 HC |
434 | config CPU_ABRT_NOMMU |
435 | bool | |
436 | ||
1da177e4 LT |
437 | config CPU_ABRT_EV4 |
438 | bool | |
439 | ||
440 | config CPU_ABRT_EV4T | |
441 | bool | |
442 | ||
443 | config CPU_ABRT_LV4T | |
444 | bool | |
445 | ||
446 | config CPU_ABRT_EV5T | |
447 | bool | |
448 | ||
449 | config CPU_ABRT_EV5TJ | |
450 | bool | |
451 | ||
452 | config CPU_ABRT_EV6 | |
453 | bool | |
454 | ||
23688e99 CM |
455 | config CPU_ABRT_EV7 |
456 | bool | |
457 | ||
4fb28474 | 458 | config CPU_PABRT_LEGACY |
48d7927b PB |
459 | bool |
460 | ||
4fb28474 KS |
461 | config CPU_PABRT_V6 |
462 | bool | |
463 | ||
464 | config CPU_PABRT_V7 | |
48d7927b PB |
465 | bool |
466 | ||
1da177e4 LT |
467 | # The cache model |
468 | config CPU_CACHE_V3 | |
469 | bool | |
470 | ||
471 | config CPU_CACHE_V4 | |
472 | bool | |
473 | ||
474 | config CPU_CACHE_V4WT | |
475 | bool | |
476 | ||
477 | config CPU_CACHE_V4WB | |
478 | bool | |
479 | ||
480 | config CPU_CACHE_V6 | |
481 | bool | |
482 | ||
23688e99 CM |
483 | config CPU_CACHE_V7 |
484 | bool | |
485 | ||
1da177e4 LT |
486 | config CPU_CACHE_VIVT |
487 | bool | |
488 | ||
489 | config CPU_CACHE_VIPT | |
490 | bool | |
491 | ||
28853ac8 PZ |
492 | config CPU_CACHE_FA |
493 | bool | |
494 | ||
f9c21a6e | 495 | if MMU |
1da177e4 | 496 | # The copy-page model |
1da177e4 LT |
497 | config CPU_COPY_V4WT |
498 | bool | |
499 | ||
500 | config CPU_COPY_V4WB | |
501 | bool | |
502 | ||
0ed15071 LB |
503 | config CPU_COPY_FEROCEON |
504 | bool | |
505 | ||
28853ac8 PZ |
506 | config CPU_COPY_FA |
507 | bool | |
508 | ||
1da177e4 LT |
509 | config CPU_COPY_V6 |
510 | bool | |
511 | ||
512 | # This selects the TLB model | |
1da177e4 LT |
513 | config CPU_TLB_V4WT |
514 | bool | |
515 | help | |
516 | ARM Architecture Version 4 TLB with writethrough cache. | |
517 | ||
518 | config CPU_TLB_V4WB | |
519 | bool | |
520 | help | |
521 | ARM Architecture Version 4 TLB with writeback cache. | |
522 | ||
523 | config CPU_TLB_V4WBI | |
524 | bool | |
525 | help | |
526 | ARM Architecture Version 4 TLB with writeback cache and invalidate | |
527 | instruction cache entry. | |
528 | ||
99c6dc11 LB |
529 | config CPU_TLB_FEROCEON |
530 | bool | |
531 | help | |
532 | Feroceon TLB (v4wbi with non-outer-cachable page table walks). | |
533 | ||
28853ac8 PZ |
534 | config CPU_TLB_FA |
535 | bool | |
536 | help | |
537 | Faraday ARM FA526 architecture, unified TLB with writeback cache | |
538 | and invalidate instruction cache entry. Branch target buffer is | |
539 | also supported. | |
540 | ||
1da177e4 LT |
541 | config CPU_TLB_V6 |
542 | bool | |
543 | ||
2ccdd1e7 CM |
544 | config CPU_TLB_V7 |
545 | bool | |
546 | ||
e220ba60 DE |
547 | config VERIFY_PERMISSION_FAULT |
548 | bool | |
f9c21a6e HC |
549 | endif |
550 | ||
516793c6 RK |
551 | config CPU_HAS_ASID |
552 | bool | |
553 | help | |
554 | This indicates whether the CPU has the ASID register; used to | |
555 | tag TLB and possibly cache entries. | |
556 | ||
fefdaa06 HC |
557 | config CPU_CP15 |
558 | bool | |
559 | help | |
560 | Processor has the CP15 register. | |
561 | ||
562 | config CPU_CP15_MMU | |
563 | bool | |
564 | select CPU_CP15 | |
565 | help | |
566 | Processor has the CP15 register, which has MMU related registers. | |
567 | ||
568 | config CPU_CP15_MPU | |
569 | bool | |
570 | select CPU_CP15 | |
571 | help | |
572 | Processor has the CP15 register, which has MPU related registers. | |
573 | ||
247055aa CM |
574 | config CPU_USE_DOMAINS |
575 | bool | |
247055aa CM |
576 | help |
577 | This option enables or disables the use of domain switching | |
578 | via the set_fs() function. | |
579 | ||
23bdf86a LB |
580 | # |
581 | # CPU supports 36-bit I/O | |
582 | # | |
583 | config IO_36 | |
584 | bool | |
585 | ||
1da177e4 LT |
586 | comment "Processor Features" |
587 | ||
497b7e94 CM |
588 | config ARM_LPAE |
589 | bool "Support for the Large Physical Address Extension" | |
08a183f0 CM |
590 | depends on MMU && CPU_32v7 && !CPU_32v6 && !CPU_32v5 && \ |
591 | !CPU_32v4 && !CPU_32v3 | |
497b7e94 CM |
592 | help |
593 | Say Y if you have an ARMv7 processor supporting the LPAE page | |
594 | table format and you would like to access memory beyond the | |
595 | 4GB limit. The resulting kernel image will not run on | |
596 | processors without the LPA extension. | |
597 | ||
598 | If unsure, say N. | |
599 | ||
600 | config ARCH_PHYS_ADDR_T_64BIT | |
601 | def_bool ARM_LPAE | |
602 | ||
603 | config ARCH_DMA_ADDR_T_64BIT | |
604 | bool | |
605 | ||
1da177e4 LT |
606 | config ARM_THUMB |
607 | bool "Support Thumb user binaries" | |
e399b1a4 | 608 | depends on CPU_ARM720T || CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020 || CPU_ARM1020E || CPU_ARM1022 || CPU_ARM1026 || CPU_XSCALE || CPU_XSC3 || CPU_MOHAWK || CPU_V6 || CPU_V6K || CPU_V7 || CPU_FEROCEON |
1da177e4 LT |
609 | default y |
610 | help | |
611 | Say Y if you want to include kernel support for running user space | |
612 | Thumb binaries. | |
613 | ||
614 | The Thumb instruction set is a compressed form of the standard ARM | |
615 | instruction set resulting in smaller binaries at the expense of | |
616 | slightly less efficient code. | |
617 | ||
618 | If you don't know what this all is, saying Y is a safe choice. | |
619 | ||
d7f864be CM |
620 | config ARM_THUMBEE |
621 | bool "Enable ThumbEE CPU extension" | |
622 | depends on CPU_V7 | |
623 | help | |
624 | Say Y here if you have a CPU with the ThumbEE extension and code to | |
625 | make use of it. Say N for code that can run on CPUs without ThumbEE. | |
626 | ||
5b6728d4 DM |
627 | config ARM_VIRT_EXT |
628 | bool "Native support for the ARM Virtualization Extensions" | |
629 | depends on MMU && CPU_V7 | |
630 | help | |
631 | Enable the kernel to make use of the ARM Virtualization | |
632 | Extensions to install hypervisors without run-time firmware | |
633 | assistance. | |
634 | ||
635 | A compliant bootloader is required in order to make maximum | |
636 | use of this feature. Refer to Documentation/arm/Booting for | |
637 | details. | |
638 | ||
639 | It is safe to enable this option even if the kernel may not be | |
640 | booted in HYP mode, may not have support for the | |
641 | virtualization extensions, or may be booted with a | |
642 | non-compliant bootloader. | |
643 | ||
64d2dc38 LL |
644 | config SWP_EMULATE |
645 | bool "Emulate SWP/SWPB instructions" | |
bd1274dc | 646 | depends on !CPU_USE_DOMAINS && CPU_V7 |
64d2dc38 | 647 | default y if SMP |
b1b3f49c | 648 | select HAVE_PROC_CPU if PROC_FS |
64d2dc38 LL |
649 | help |
650 | ARMv6 architecture deprecates use of the SWP/SWPB instructions. | |
651 | ARMv7 multiprocessing extensions introduce the ability to disable | |
652 | these instructions, triggering an undefined instruction exception | |
653 | when executed. Say Y here to enable software emulation of these | |
654 | instructions for userspace (not kernel) using LDREX/STREX. | |
655 | Also creates /proc/cpu/swp_emulation for statistics. | |
656 | ||
657 | In some older versions of glibc [<=2.8] SWP is used during futex | |
658 | trylock() operations with the assumption that the code will not | |
659 | be preempted. This invalid assumption may be more likely to fail | |
660 | with SWP emulation enabled, leading to deadlock of the user | |
661 | application. | |
662 | ||
663 | NOTE: when accessing uncached shared regions, LDREX/STREX rely | |
664 | on an external transaction monitoring block called a global | |
665 | monitor to maintain update atomicity. If your system does not | |
666 | implement a global monitor, this option can cause programs that | |
667 | perform SWP operations to uncached memory to deadlock. | |
668 | ||
669 | If unsure, say Y. | |
670 | ||
1da177e4 LT |
671 | config CPU_BIG_ENDIAN |
672 | bool "Build big-endian kernel" | |
673 | depends on ARCH_SUPPORTS_BIG_ENDIAN | |
674 | help | |
675 | Say Y if you plan on running a kernel in big-endian mode. | |
676 | Note that your board must be properly built and your board | |
677 | port must properly enable any big-endian related features | |
678 | of your chipset/board/processor. | |
679 | ||
26584853 CM |
680 | config CPU_ENDIAN_BE8 |
681 | bool | |
682 | depends on CPU_BIG_ENDIAN | |
e399b1a4 | 683 | default CPU_V6 || CPU_V6K || CPU_V7 |
26584853 CM |
684 | help |
685 | Support for the BE-8 (big-endian) mode on ARMv6 and ARMv7 processors. | |
686 | ||
687 | config CPU_ENDIAN_BE32 | |
688 | bool | |
689 | depends on CPU_BIG_ENDIAN | |
690 | default !CPU_ENDIAN_BE8 | |
691 | help | |
692 | Support for the BE-32 (big-endian) mode on pre-ARMv6 processors. | |
693 | ||
6afd6fae | 694 | config CPU_HIGH_VECTOR |
6340aa61 | 695 | depends on !MMU && CPU_CP15 && !CPU_ARM740T |
6afd6fae | 696 | bool "Select the High exception vector" |
6afd6fae HC |
697 | help |
698 | Say Y here to select high exception vector(0xFFFF0000~). | |
9b7333a9 | 699 | The exception vector can vary depending on the platform |
6afd6fae HC |
700 | design in nommu mode. If your platform needs to select |
701 | high exception vector, say Y. | |
702 | Otherwise or if you are unsure, say N, and the low exception | |
703 | vector (0x00000000~) will be used. | |
704 | ||
1da177e4 | 705 | config CPU_ICACHE_DISABLE |
f12d0d7c | 706 | bool "Disable I-Cache (I-bit)" |
357c9c1f | 707 | depends on CPU_CP15 && !(CPU_ARM720T || CPU_ARM740T || CPU_XSCALE || CPU_XSC3) |
1da177e4 LT |
708 | help |
709 | Say Y here to disable the processor instruction cache. Unless | |
710 | you have a reason not to or are unsure, say N. | |
711 | ||
712 | config CPU_DCACHE_DISABLE | |
f12d0d7c HC |
713 | bool "Disable D-Cache (C-bit)" |
714 | depends on CPU_CP15 | |
1da177e4 LT |
715 | help |
716 | Say Y here to disable the processor data cache. Unless | |
717 | you have a reason not to or are unsure, say N. | |
718 | ||
f37f46eb HC |
719 | config CPU_DCACHE_SIZE |
720 | hex | |
721 | depends on CPU_ARM740T || CPU_ARM946E | |
722 | default 0x00001000 if CPU_ARM740T | |
723 | default 0x00002000 # default size for ARM946E-S | |
724 | help | |
725 | Some cores are synthesizable to have various sized cache. For | |
726 | ARM946E-S case, it can vary from 0KB to 1MB. | |
727 | To support such cache operations, it is efficient to know the size | |
728 | before compile time. | |
729 | If your SoC is configured to have a different size, define the value | |
730 | here with proper conditions. | |
731 | ||
1da177e4 LT |
732 | config CPU_DCACHE_WRITETHROUGH |
733 | bool "Force write through D-cache" | |
28853ac8 | 734 | depends on (CPU_ARM740T || CPU_ARM920T || CPU_ARM922T || CPU_ARM925T || CPU_ARM926T || CPU_ARM940T || CPU_ARM946E || CPU_ARM1020 || CPU_FA526) && !CPU_DCACHE_DISABLE |
1da177e4 LT |
735 | default y if CPU_ARM925T |
736 | help | |
737 | Say Y here to use the data cache in writethrough mode. Unless you | |
738 | specifically require this or are unsure, say N. | |
739 | ||
740 | config CPU_CACHE_ROUND_ROBIN | |
741 | bool "Round robin I and D cache replacement algorithm" | |
f37f46eb | 742 | depends on (CPU_ARM926T || CPU_ARM946E || CPU_ARM1020) && (!CPU_ICACHE_DISABLE || !CPU_DCACHE_DISABLE) |
1da177e4 LT |
743 | help |
744 | Say Y here to use the predictable round-robin cache replacement | |
745 | policy. Unless you specifically require this or are unsure, say N. | |
746 | ||
747 | config CPU_BPREDICT_DISABLE | |
748 | bool "Disable branch prediction" | |
e399b1a4 | 749 | depends on CPU_ARM1020 || CPU_V6 || CPU_V6K || CPU_MOHAWK || CPU_XSC3 || CPU_V7 || CPU_FA526 |
1da177e4 LT |
750 | help |
751 | Say Y here to disable branch prediction. If unsure, say N. | |
2d2669b6 | 752 | |
4b0e07a5 NP |
753 | config TLS_REG_EMUL |
754 | bool | |
4b0e07a5 | 755 | help |
70489c88 NP |
756 | An SMP system using a pre-ARMv6 processor (there are apparently |
757 | a few prototypes like that in existence) and therefore access to | |
758 | that required register must be emulated. | |
4b0e07a5 | 759 | |
dcef1f63 NP |
760 | config NEEDS_SYSCALL_FOR_CMPXCHG |
761 | bool | |
dcef1f63 NP |
762 | help |
763 | SMP on a pre-ARMv6 processor? Well OK then. | |
764 | Forget about fast user space cmpxchg support. | |
765 | It is just not possible. | |
766 | ||
ad642d9f CM |
767 | config DMA_CACHE_RWFO |
768 | bool "Enable read/write for ownership DMA cache maintenance" | |
3bc28c8e | 769 | depends on CPU_V6K && SMP |
ad642d9f CM |
770 | default y |
771 | help | |
772 | The Snoop Control Unit on ARM11MPCore does not detect the | |
773 | cache maintenance operations and the dma_{map,unmap}_area() | |
774 | functions may leave stale cache entries on other CPUs. By | |
775 | enabling this option, Read or Write For Ownership in the ARMv6 | |
776 | DMA cache maintenance functions is performed. These LDR/STR | |
777 | instructions change the cache line state to shared or modified | |
778 | so that the cache operation has the desired effect. | |
779 | ||
780 | Note that the workaround is only valid on processors that do | |
781 | not perform speculative loads into the D-cache. For such | |
782 | processors, if cache maintenance operations are not broadcast | |
783 | in hardware, other workarounds are needed (e.g. cache | |
784 | maintenance broadcasting in software via FIQ). | |
785 | ||
953233dc CM |
786 | config OUTER_CACHE |
787 | bool | |
382266ad | 788 | |
319f551a CM |
789 | config OUTER_CACHE_SYNC |
790 | bool | |
791 | help | |
792 | The outer cache has a outer_cache_fns.sync function pointer | |
793 | that can be used to drain the write buffer of the outer cache. | |
794 | ||
99c6dc11 LB |
795 | config CACHE_FEROCEON_L2 |
796 | bool "Enable the Feroceon L2 cache controller" | |
794d15b2 | 797 | depends on ARCH_KIRKWOOD || ARCH_MV78XX0 |
99c6dc11 LB |
798 | default y |
799 | select OUTER_CACHE | |
800 | help | |
801 | This option enables the Feroceon L2 cache controller. | |
802 | ||
4360bb41 RS |
803 | config CACHE_FEROCEON_L2_WRITETHROUGH |
804 | bool "Force Feroceon L2 cache write through" | |
805 | depends on CACHE_FEROCEON_L2 | |
4360bb41 RS |
806 | help |
807 | Say Y here to use the Feroceon L2 cache in writethrough mode. | |
808 | Unless you specifically require this, say N for writeback mode. | |
809 | ||
ce5ea9f3 DM |
810 | config MIGHT_HAVE_CACHE_L2X0 |
811 | bool | |
812 | help | |
813 | This option should be selected by machines which have a L2x0 | |
814 | or PL310 cache controller, but where its use is optional. | |
815 | ||
816 | The only effect of this option is to make CACHE_L2X0 and | |
817 | related options available to the user for configuration. | |
818 | ||
819 | Boards or SoCs which always require the cache controller | |
820 | support to be present should select CACHE_L2X0 directly | |
821 | instead of this option, thus preventing the user from | |
822 | inadvertently configuring a broken kernel. | |
823 | ||
382266ad | 824 | config CACHE_L2X0 |
ce5ea9f3 DM |
825 | bool "Enable the L2x0 outer cache controller" if MIGHT_HAVE_CACHE_L2X0 |
826 | default MIGHT_HAVE_CACHE_L2X0 | |
382266ad | 827 | select OUTER_CACHE |
23107c54 | 828 | select OUTER_CACHE_SYNC |
ba927951 CM |
829 | help |
830 | This option enables the L2x0 PrimeCell. | |
905a09d5 | 831 | |
9a6655e4 CM |
832 | config CACHE_PL310 |
833 | bool | |
834 | depends on CACHE_L2X0 | |
e399b1a4 | 835 | default y if CPU_V7 && !(CPU_V6 || CPU_V6K) |
9a6655e4 CM |
836 | help |
837 | This option enables optimisations for the PL310 cache | |
838 | controller. | |
839 | ||
573a652f LB |
840 | config CACHE_TAUROS2 |
841 | bool "Enable the Tauros2 L2 cache controller" | |
3f408fa0 | 842 | depends on (ARCH_DOVE || ARCH_MMP || CPU_PJ4) |
573a652f LB |
843 | default y |
844 | select OUTER_CACHE | |
845 | help | |
846 | This option enables the Tauros2 L2 cache controller (as | |
847 | found on PJ1/PJ4). | |
848 | ||
905a09d5 EM |
849 | config CACHE_XSC3L2 |
850 | bool "Enable the L2 cache on XScale3" | |
851 | depends on CPU_XSC3 | |
852 | default y | |
853 | select OUTER_CACHE | |
854 | help | |
855 | This option enables the L2 cache on XScale3. | |
910a17e5 | 856 | |
5637a126 RK |
857 | config ARM_L1_CACHE_SHIFT_6 |
858 | bool | |
a092f2b1 | 859 | default y if CPU_V7 |
5637a126 RK |
860 | help |
861 | Setting ARM L1 cache line size to 64 Bytes. | |
862 | ||
910a17e5 KS |
863 | config ARM_L1_CACHE_SHIFT |
864 | int | |
d6d502fa | 865 | default 6 if ARM_L1_CACHE_SHIFT_6 |
910a17e5 | 866 | default 5 |
47ab0dee RK |
867 | |
868 | config ARM_DMA_MEM_BUFFERABLE | |
e399b1a4 | 869 | bool "Use non-cacheable memory for DMA" if (CPU_V6 || CPU_V6K) && !CPU_V7 |
42c4dafe CM |
870 | depends on !(MACH_REALVIEW_PB1176 || REALVIEW_EB_ARM11MP || \ |
871 | MACH_REALVIEW_PB11MP) | |
e399b1a4 | 872 | default y if CPU_V6 || CPU_V6K || CPU_V7 |
47ab0dee RK |
873 | help |
874 | Historically, the kernel has used strongly ordered mappings to | |
875 | provide DMA coherent memory. With the advent of ARMv7, mapping | |
876 | memory with differing types results in unpredictable behaviour, | |
877 | so on these CPUs, this option is forced on. | |
878 | ||
879 | Multiple mappings with differing attributes is also unpredictable | |
880 | on ARMv6 CPUs, but since they do not have aggressive speculative | |
881 | prefetch, no harm appears to occur. | |
882 | ||
883 | However, drivers may be missing the necessary barriers for ARMv6, | |
884 | and therefore turning this on may result in unpredictable driver | |
885 | behaviour. Therefore, we offer this as an option. | |
886 | ||
887 | You are recommended say 'Y' here and debug any affected drivers. | |
ac1d426e | 888 | |
e7c5650f CM |
889 | config ARCH_HAS_BARRIERS |
890 | bool | |
891 | help | |
892 | This option allows the use of custom mandatory barriers | |
893 | included via the mach/barriers.h file. |