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382266ad CM |
1 | /* |
2 | * arch/arm/mm/cache-l2x0.c - L210/L220 cache controller support | |
3 | * | |
4 | * Copyright (C) 2007 ARM Limited | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; if not, write to the Free Software | |
17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | */ | |
19 | #include <linux/init.h> | |
07620976 | 20 | #include <linux/spinlock.h> |
fced80c7 | 21 | #include <linux/io.h> |
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22 | |
23 | #include <asm/cacheflush.h> | |
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24 | #include <asm/hardware/cache-l2x0.h> |
25 | ||
26 | #define CACHE_LINE_SIZE 32 | |
27 | ||
28 | static void __iomem *l2x0_base; | |
07620976 | 29 | static DEFINE_SPINLOCK(l2x0_lock); |
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30 | |
31 | static inline void sync_writel(unsigned long val, unsigned long reg, | |
32 | unsigned long complete_mask) | |
33 | { | |
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34 | unsigned long flags; |
35 | ||
36 | spin_lock_irqsave(&l2x0_lock, flags); | |
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37 | writel(val, l2x0_base + reg); |
38 | /* wait for the operation to complete */ | |
39 | while (readl(l2x0_base + reg) & complete_mask) | |
40 | ; | |
07620976 | 41 | spin_unlock_irqrestore(&l2x0_lock, flags); |
382266ad CM |
42 | } |
43 | ||
44 | static inline void cache_sync(void) | |
45 | { | |
46 | sync_writel(0, L2X0_CACHE_SYNC, 1); | |
47 | } | |
48 | ||
49 | static inline void l2x0_inv_all(void) | |
50 | { | |
51 | /* invalidate all ways */ | |
52 | sync_writel(0xff, L2X0_INV_WAY, 0xff); | |
53 | cache_sync(); | |
54 | } | |
55 | ||
56 | static void l2x0_inv_range(unsigned long start, unsigned long end) | |
57 | { | |
58 | unsigned long addr; | |
59 | ||
4f6627ac RS |
60 | if (start & (CACHE_LINE_SIZE - 1)) { |
61 | start &= ~(CACHE_LINE_SIZE - 1); | |
62 | sync_writel(start, L2X0_CLEAN_INV_LINE_PA, 1); | |
63 | start += CACHE_LINE_SIZE; | |
64 | } | |
65 | ||
66 | if (end & (CACHE_LINE_SIZE - 1)) { | |
67 | end &= ~(CACHE_LINE_SIZE - 1); | |
68 | sync_writel(end, L2X0_CLEAN_INV_LINE_PA, 1); | |
69 | } | |
70 | ||
382266ad CM |
71 | for (addr = start; addr < end; addr += CACHE_LINE_SIZE) |
72 | sync_writel(addr, L2X0_INV_LINE_PA, 1); | |
73 | cache_sync(); | |
74 | } | |
75 | ||
76 | static void l2x0_clean_range(unsigned long start, unsigned long end) | |
77 | { | |
78 | unsigned long addr; | |
79 | ||
80 | start &= ~(CACHE_LINE_SIZE - 1); | |
81 | for (addr = start; addr < end; addr += CACHE_LINE_SIZE) | |
82 | sync_writel(addr, L2X0_CLEAN_LINE_PA, 1); | |
83 | cache_sync(); | |
84 | } | |
85 | ||
86 | static void l2x0_flush_range(unsigned long start, unsigned long end) | |
87 | { | |
88 | unsigned long addr; | |
89 | ||
90 | start &= ~(CACHE_LINE_SIZE - 1); | |
91 | for (addr = start; addr < end; addr += CACHE_LINE_SIZE) | |
92 | sync_writel(addr, L2X0_CLEAN_INV_LINE_PA, 1); | |
93 | cache_sync(); | |
94 | } | |
95 | ||
96 | void __init l2x0_init(void __iomem *base, __u32 aux_val, __u32 aux_mask) | |
97 | { | |
98 | __u32 aux; | |
99 | ||
100 | l2x0_base = base; | |
101 | ||
102 | /* disable L2X0 */ | |
103 | writel(0, l2x0_base + L2X0_CTRL); | |
104 | ||
105 | aux = readl(l2x0_base + L2X0_AUX_CTRL); | |
106 | aux &= aux_mask; | |
107 | aux |= aux_val; | |
108 | writel(aux, l2x0_base + L2X0_AUX_CTRL); | |
109 | ||
110 | l2x0_inv_all(); | |
111 | ||
112 | /* enable L2X0 */ | |
113 | writel(1, l2x0_base + L2X0_CTRL); | |
114 | ||
115 | outer_cache.inv_range = l2x0_inv_range; | |
116 | outer_cache.clean_range = l2x0_clean_range; | |
117 | outer_cache.flush_range = l2x0_flush_range; | |
118 | ||
119 | printk(KERN_INFO "L2X0 cache controller enabled\n"); | |
120 | } |