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d73e60b7 RK |
1 | /* |
2 | * linux/arch/arm/mm/copypage-v4wt.S | |
3 | * | |
4 | * Copyright (C) 1995-1999 Russell King | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | * | |
10 | * This is for CPUs with a writethrough cache and 'flush ID cache' is | |
11 | * the only supported cache operation. | |
12 | */ | |
13 | #include <linux/init.h> | |
063b0a42 | 14 | #include <linux/highmem.h> |
d73e60b7 RK |
15 | |
16 | /* | |
063b0a42 | 17 | * ARMv4 optimised copy_user_highpage |
d73e60b7 RK |
18 | * |
19 | * Since we have writethrough caches, we don't have to worry about | |
20 | * dirty data in the cache. However, we do have to ensure that | |
21 | * subsequent reads are up to date. | |
22 | */ | |
063b0a42 RK |
23 | static void __attribute__((naked)) |
24 | v4wt_copy_user_page(void *kto, const void *kfrom) | |
d73e60b7 RK |
25 | { |
26 | asm("\ | |
27 | stmfd sp!, {r4, lr} @ 2\n\ | |
28 | mov r2, %0 @ 1\n\ | |
29 | ldmia r1!, {r3, r4, ip, lr} @ 4\n\ | |
30 | 1: stmia r0!, {r3, r4, ip, lr} @ 4\n\ | |
31 | ldmia r1!, {r3, r4, ip, lr} @ 4+1\n\ | |
32 | stmia r0!, {r3, r4, ip, lr} @ 4\n\ | |
33 | ldmia r1!, {r3, r4, ip, lr} @ 4\n\ | |
34 | stmia r0!, {r3, r4, ip, lr} @ 4\n\ | |
35 | ldmia r1!, {r3, r4, ip, lr} @ 4\n\ | |
36 | subs r2, r2, #1 @ 1\n\ | |
37 | stmia r0!, {r3, r4, ip, lr} @ 4\n\ | |
38 | ldmneia r1!, {r3, r4, ip, lr} @ 4\n\ | |
39 | bne 1b @ 1\n\ | |
40 | mcr p15, 0, r2, c7, c7, 0 @ flush ID cache\n\ | |
41 | ldmfd sp!, {r4, pc} @ 3" | |
42 | : | |
43 | : "I" (PAGE_SIZE / 64)); | |
44 | } | |
45 | ||
063b0a42 RK |
46 | void v4wt_copy_user_highpage(struct page *to, struct page *from, |
47 | unsigned long vaddr) | |
48 | { | |
49 | void *kto, *kfrom; | |
50 | ||
51 | kto = kmap_atomic(to, KM_USER0); | |
52 | kfrom = kmap_atomic(from, KM_USER1); | |
53 | v4wt_copy_user_page(kto, kfrom); | |
54 | kunmap_atomic(kfrom, KM_USER1); | |
55 | kunmap_atomic(kto, KM_USER0); | |
56 | } | |
57 | ||
d73e60b7 RK |
58 | /* |
59 | * ARMv4 optimised clear_user_page | |
60 | * | |
61 | * Same story as above. | |
62 | */ | |
63 | void __attribute__((naked)) | |
64 | v4wt_clear_user_page(void *kaddr, unsigned long vaddr) | |
65 | { | |
66 | asm("\ | |
67 | str lr, [sp, #-4]!\n\ | |
68 | mov r1, %0 @ 1\n\ | |
69 | mov r2, #0 @ 1\n\ | |
70 | mov r3, #0 @ 1\n\ | |
71 | mov ip, #0 @ 1\n\ | |
72 | mov lr, #0 @ 1\n\ | |
73 | 1: stmia r0!, {r2, r3, ip, lr} @ 4\n\ | |
74 | stmia r0!, {r2, r3, ip, lr} @ 4\n\ | |
75 | stmia r0!, {r2, r3, ip, lr} @ 4\n\ | |
76 | stmia r0!, {r2, r3, ip, lr} @ 4\n\ | |
77 | subs r1, r1, #1 @ 1\n\ | |
78 | bne 1b @ 1\n\ | |
79 | mcr p15, 0, r2, c7, c7, 0 @ flush ID cache\n\ | |
80 | ldr pc, [sp], #4" | |
81 | : | |
82 | : "I" (PAGE_SIZE / 64)); | |
83 | } | |
84 | ||
85 | struct cpu_user_fns v4wt_user_fns __initdata = { | |
86 | .cpu_clear_user_page = v4wt_clear_user_page, | |
063b0a42 | 87 | .cpu_copy_user_highpage = v4wt_copy_user_highpage, |
d73e60b7 | 88 | }; |