Commit | Line | Data |
---|---|---|
1da177e4 | 1 | /* |
0ddbccd1 | 2 | * linux/arch/arm/mm/dma-mapping.c |
1da177e4 LT |
3 | * |
4 | * Copyright (C) 2000-2004 Russell King | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | * | |
10 | * DMA uncached mapping support. | |
11 | */ | |
12 | #include <linux/module.h> | |
13 | #include <linux/mm.h> | |
5a0e3ad6 | 14 | #include <linux/gfp.h> |
1da177e4 LT |
15 | #include <linux/errno.h> |
16 | #include <linux/list.h> | |
17 | #include <linux/init.h> | |
18 | #include <linux/device.h> | |
19 | #include <linux/dma-mapping.h> | |
c7909509 | 20 | #include <linux/dma-contiguous.h> |
39af22a7 | 21 | #include <linux/highmem.h> |
c7909509 | 22 | #include <linux/memblock.h> |
99d1717d | 23 | #include <linux/slab.h> |
4ce63fcd | 24 | #include <linux/iommu.h> |
e9da6e99 | 25 | #include <linux/io.h> |
4ce63fcd | 26 | #include <linux/vmalloc.h> |
158e8bfe | 27 | #include <linux/sizes.h> |
1da177e4 | 28 | |
23759dc6 | 29 | #include <asm/memory.h> |
43377453 | 30 | #include <asm/highmem.h> |
1da177e4 | 31 | #include <asm/cacheflush.h> |
1da177e4 | 32 | #include <asm/tlbflush.h> |
99d1717d | 33 | #include <asm/mach/arch.h> |
4ce63fcd | 34 | #include <asm/dma-iommu.h> |
c7909509 MS |
35 | #include <asm/mach/map.h> |
36 | #include <asm/system_info.h> | |
37 | #include <asm/dma-contiguous.h> | |
37134cd5 | 38 | |
022ae537 RK |
39 | #include "mm.h" |
40 | ||
15237e1f MS |
41 | /* |
42 | * The DMA API is built upon the notion of "buffer ownership". A buffer | |
43 | * is either exclusively owned by the CPU (and therefore may be accessed | |
44 | * by it) or exclusively owned by the DMA device. These helper functions | |
45 | * represent the transitions between these two ownership states. | |
46 | * | |
47 | * Note, however, that on later ARMs, this notion does not work due to | |
48 | * speculative prefetches. We model our approach on the assumption that | |
49 | * the CPU does do speculative prefetches, which means we clean caches | |
50 | * before transfers and delay cache invalidation until transfer completion. | |
51 | * | |
15237e1f | 52 | */ |
51fde349 | 53 | static void __dma_page_cpu_to_dev(struct page *, unsigned long, |
15237e1f | 54 | size_t, enum dma_data_direction); |
51fde349 | 55 | static void __dma_page_dev_to_cpu(struct page *, unsigned long, |
15237e1f MS |
56 | size_t, enum dma_data_direction); |
57 | ||
2dc6a016 MS |
58 | /** |
59 | * arm_dma_map_page - map a portion of a page for streaming DMA | |
60 | * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices | |
61 | * @page: page that buffer resides in | |
62 | * @offset: offset into page for start of buffer | |
63 | * @size: size of buffer to map | |
64 | * @dir: DMA transfer direction | |
65 | * | |
66 | * Ensure that any data held in the cache is appropriately discarded | |
67 | * or written back. | |
68 | * | |
69 | * The device owns this memory once this call has completed. The CPU | |
70 | * can regain ownership by calling dma_unmap_page(). | |
71 | */ | |
51fde349 | 72 | static dma_addr_t arm_dma_map_page(struct device *dev, struct page *page, |
2dc6a016 MS |
73 | unsigned long offset, size_t size, enum dma_data_direction dir, |
74 | struct dma_attrs *attrs) | |
75 | { | |
97ef952a | 76 | if (!arch_is_coherent() && !dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs)) |
51fde349 MS |
77 | __dma_page_cpu_to_dev(page, offset, size, dir); |
78 | return pfn_to_dma(dev, page_to_pfn(page)) + offset; | |
2dc6a016 MS |
79 | } |
80 | ||
81 | /** | |
82 | * arm_dma_unmap_page - unmap a buffer previously mapped through dma_map_page() | |
83 | * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices | |
84 | * @handle: DMA address of buffer | |
85 | * @size: size of buffer (same as passed to dma_map_page) | |
86 | * @dir: DMA transfer direction (same as passed to dma_map_page) | |
87 | * | |
88 | * Unmap a page streaming mode DMA translation. The handle and size | |
89 | * must match what was provided in the previous dma_map_page() call. | |
90 | * All other usages are undefined. | |
91 | * | |
92 | * After this call, reads by the CPU to the buffer are guaranteed to see | |
93 | * whatever the device wrote there. | |
94 | */ | |
51fde349 | 95 | static void arm_dma_unmap_page(struct device *dev, dma_addr_t handle, |
2dc6a016 MS |
96 | size_t size, enum dma_data_direction dir, |
97 | struct dma_attrs *attrs) | |
98 | { | |
97ef952a | 99 | if (!arch_is_coherent() && !dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs)) |
51fde349 MS |
100 | __dma_page_dev_to_cpu(pfn_to_page(dma_to_pfn(dev, handle)), |
101 | handle & ~PAGE_MASK, size, dir); | |
2dc6a016 MS |
102 | } |
103 | ||
51fde349 | 104 | static void arm_dma_sync_single_for_cpu(struct device *dev, |
2dc6a016 MS |
105 | dma_addr_t handle, size_t size, enum dma_data_direction dir) |
106 | { | |
107 | unsigned int offset = handle & (PAGE_SIZE - 1); | |
108 | struct page *page = pfn_to_page(dma_to_pfn(dev, handle-offset)); | |
51fde349 MS |
109 | if (!arch_is_coherent()) |
110 | __dma_page_dev_to_cpu(page, offset, size, dir); | |
2dc6a016 MS |
111 | } |
112 | ||
51fde349 | 113 | static void arm_dma_sync_single_for_device(struct device *dev, |
2dc6a016 MS |
114 | dma_addr_t handle, size_t size, enum dma_data_direction dir) |
115 | { | |
116 | unsigned int offset = handle & (PAGE_SIZE - 1); | |
117 | struct page *page = pfn_to_page(dma_to_pfn(dev, handle-offset)); | |
51fde349 MS |
118 | if (!arch_is_coherent()) |
119 | __dma_page_cpu_to_dev(page, offset, size, dir); | |
2dc6a016 MS |
120 | } |
121 | ||
122 | static int arm_dma_set_mask(struct device *dev, u64 dma_mask); | |
123 | ||
124 | struct dma_map_ops arm_dma_ops = { | |
f99d6034 MS |
125 | .alloc = arm_dma_alloc, |
126 | .free = arm_dma_free, | |
127 | .mmap = arm_dma_mmap, | |
dc2832e1 | 128 | .get_sgtable = arm_dma_get_sgtable, |
2dc6a016 MS |
129 | .map_page = arm_dma_map_page, |
130 | .unmap_page = arm_dma_unmap_page, | |
131 | .map_sg = arm_dma_map_sg, | |
132 | .unmap_sg = arm_dma_unmap_sg, | |
133 | .sync_single_for_cpu = arm_dma_sync_single_for_cpu, | |
134 | .sync_single_for_device = arm_dma_sync_single_for_device, | |
135 | .sync_sg_for_cpu = arm_dma_sync_sg_for_cpu, | |
136 | .sync_sg_for_device = arm_dma_sync_sg_for_device, | |
137 | .set_dma_mask = arm_dma_set_mask, | |
138 | }; | |
139 | EXPORT_SYMBOL(arm_dma_ops); | |
140 | ||
ab6494f0 CM |
141 | static u64 get_coherent_dma_mask(struct device *dev) |
142 | { | |
022ae537 | 143 | u64 mask = (u64)arm_dma_limit; |
ab6494f0 CM |
144 | |
145 | if (dev) { | |
146 | mask = dev->coherent_dma_mask; | |
147 | ||
148 | /* | |
149 | * Sanity check the DMA mask - it must be non-zero, and | |
150 | * must be able to be satisfied by a DMA allocation. | |
151 | */ | |
152 | if (mask == 0) { | |
153 | dev_warn(dev, "coherent DMA mask is unset\n"); | |
154 | return 0; | |
155 | } | |
156 | ||
022ae537 | 157 | if ((~mask) & (u64)arm_dma_limit) { |
ab6494f0 CM |
158 | dev_warn(dev, "coherent DMA mask %#llx is smaller " |
159 | "than system GFP_DMA mask %#llx\n", | |
022ae537 | 160 | mask, (u64)arm_dma_limit); |
ab6494f0 CM |
161 | return 0; |
162 | } | |
163 | } | |
1da177e4 | 164 | |
ab6494f0 CM |
165 | return mask; |
166 | } | |
167 | ||
c7909509 MS |
168 | static void __dma_clear_buffer(struct page *page, size_t size) |
169 | { | |
170 | void *ptr; | |
171 | /* | |
172 | * Ensure that the allocated pages are zeroed, and that any data | |
173 | * lurking in the kernel direct-mapped region is invalidated. | |
174 | */ | |
175 | ptr = page_address(page); | |
4ce63fcd MS |
176 | if (ptr) { |
177 | memset(ptr, 0, size); | |
178 | dmac_flush_range(ptr, ptr + size); | |
179 | outer_flush_range(__pa(ptr), __pa(ptr) + size); | |
180 | } | |
c7909509 MS |
181 | } |
182 | ||
7a9a32a9 RK |
183 | /* |
184 | * Allocate a DMA buffer for 'dev' of size 'size' using the | |
185 | * specified gfp mask. Note that 'size' must be page aligned. | |
186 | */ | |
187 | static struct page *__dma_alloc_buffer(struct device *dev, size_t size, gfp_t gfp) | |
188 | { | |
189 | unsigned long order = get_order(size); | |
190 | struct page *page, *p, *e; | |
7a9a32a9 RK |
191 | |
192 | page = alloc_pages(gfp, order); | |
193 | if (!page) | |
194 | return NULL; | |
195 | ||
196 | /* | |
197 | * Now split the huge page and free the excess pages | |
198 | */ | |
199 | split_page(page, order); | |
200 | for (p = page + (size >> PAGE_SHIFT), e = page + (1 << order); p < e; p++) | |
201 | __free_page(p); | |
202 | ||
c7909509 | 203 | __dma_clear_buffer(page, size); |
7a9a32a9 RK |
204 | |
205 | return page; | |
206 | } | |
207 | ||
208 | /* | |
209 | * Free a DMA buffer. 'size' must be page aligned. | |
210 | */ | |
211 | static void __dma_free_buffer(struct page *page, size_t size) | |
212 | { | |
213 | struct page *e = page + (size >> PAGE_SHIFT); | |
214 | ||
215 | while (page < e) { | |
216 | __free_page(page); | |
217 | page++; | |
218 | } | |
219 | } | |
220 | ||
ab6494f0 | 221 | #ifdef CONFIG_MMU |
e9da6e99 MS |
222 | #ifdef CONFIG_HUGETLB_PAGE |
223 | #error ARM Coherent DMA allocator does not (yet) support huge TLB | |
224 | #endif | |
a5e9d38b | 225 | |
e9da6e99 MS |
226 | static void *__alloc_from_contiguous(struct device *dev, size_t size, |
227 | pgprot_t prot, struct page **ret_page); | |
99d1717d | 228 | |
e9da6e99 MS |
229 | static void *__alloc_remap_buffer(struct device *dev, size_t size, gfp_t gfp, |
230 | pgprot_t prot, struct page **ret_page, | |
231 | const void *caller); | |
99d1717d | 232 | |
e9da6e99 MS |
233 | static void * |
234 | __dma_alloc_remap(struct page *page, size_t size, gfp_t gfp, pgprot_t prot, | |
235 | const void *caller) | |
99d1717d | 236 | { |
e9da6e99 MS |
237 | struct vm_struct *area; |
238 | unsigned long addr; | |
99d1717d | 239 | |
e9da6e99 MS |
240 | /* |
241 | * DMA allocation can be mapped to user space, so lets | |
242 | * set VM_USERMAP flags too. | |
243 | */ | |
244 | area = get_vm_area_caller(size, VM_ARM_DMA_CONSISTENT | VM_USERMAP, | |
245 | caller); | |
246 | if (!area) | |
247 | return NULL; | |
248 | addr = (unsigned long)area->addr; | |
249 | area->phys_addr = __pfn_to_phys(page_to_pfn(page)); | |
99d1717d | 250 | |
e9da6e99 MS |
251 | if (ioremap_page_range(addr, addr + size, area->phys_addr, prot)) { |
252 | vunmap((void *)addr); | |
253 | return NULL; | |
254 | } | |
255 | return (void *)addr; | |
99d1717d | 256 | } |
1da177e4 | 257 | |
e9da6e99 | 258 | static void __dma_free_remap(void *cpu_addr, size_t size) |
88c58f3b | 259 | { |
e9da6e99 MS |
260 | unsigned int flags = VM_ARM_DMA_CONSISTENT | VM_USERMAP; |
261 | struct vm_struct *area = find_vm_area(cpu_addr); | |
262 | if (!area || (area->flags & flags) != flags) { | |
263 | WARN(1, "trying to free invalid coherent area: %p\n", cpu_addr); | |
264 | return; | |
99d1717d | 265 | } |
e9da6e99 MS |
266 | unmap_kernel_range((unsigned long)cpu_addr, size); |
267 | vunmap(cpu_addr); | |
88c58f3b | 268 | } |
88c58f3b | 269 | |
6e5267aa MS |
270 | #define DEFAULT_DMA_COHERENT_POOL_SIZE SZ_256K |
271 | ||
e9da6e99 MS |
272 | struct dma_pool { |
273 | size_t size; | |
274 | spinlock_t lock; | |
275 | unsigned long *bitmap; | |
276 | unsigned long nr_pages; | |
277 | void *vaddr; | |
6b3fe472 | 278 | struct page **pages; |
c7909509 MS |
279 | }; |
280 | ||
e9da6e99 | 281 | static struct dma_pool atomic_pool = { |
6e5267aa | 282 | .size = DEFAULT_DMA_COHERENT_POOL_SIZE, |
e9da6e99 | 283 | }; |
c7909509 MS |
284 | |
285 | static int __init early_coherent_pool(char *p) | |
286 | { | |
e9da6e99 | 287 | atomic_pool.size = memparse(p, &p); |
c7909509 MS |
288 | return 0; |
289 | } | |
290 | early_param("coherent_pool", early_coherent_pool); | |
291 | ||
6e5267aa MS |
292 | void __init init_dma_coherent_pool_size(unsigned long size) |
293 | { | |
294 | /* | |
295 | * Catch any attempt to set the pool size too late. | |
296 | */ | |
297 | BUG_ON(atomic_pool.vaddr); | |
298 | ||
299 | /* | |
300 | * Set architecture specific coherent pool size only if | |
301 | * it has not been changed by kernel command line parameter. | |
302 | */ | |
303 | if (atomic_pool.size == DEFAULT_DMA_COHERENT_POOL_SIZE) | |
304 | atomic_pool.size = size; | |
305 | } | |
306 | ||
c7909509 MS |
307 | /* |
308 | * Initialise the coherent pool for atomic allocations. | |
309 | */ | |
e9da6e99 | 310 | static int __init atomic_pool_init(void) |
c7909509 | 311 | { |
e9da6e99 | 312 | struct dma_pool *pool = &atomic_pool; |
c7909509 | 313 | pgprot_t prot = pgprot_dmacoherent(pgprot_kernel); |
e9da6e99 MS |
314 | unsigned long nr_pages = pool->size >> PAGE_SHIFT; |
315 | unsigned long *bitmap; | |
c7909509 | 316 | struct page *page; |
6b3fe472 | 317 | struct page **pages; |
c7909509 | 318 | void *ptr; |
e9da6e99 | 319 | int bitmap_size = BITS_TO_LONGS(nr_pages) * sizeof(long); |
c7909509 | 320 | |
e9da6e99 MS |
321 | bitmap = kzalloc(bitmap_size, GFP_KERNEL); |
322 | if (!bitmap) | |
323 | goto no_bitmap; | |
c7909509 | 324 | |
6b3fe472 HD |
325 | pages = kzalloc(nr_pages * sizeof(struct page *), GFP_KERNEL); |
326 | if (!pages) | |
327 | goto no_pages; | |
328 | ||
e9da6e99 MS |
329 | if (IS_ENABLED(CONFIG_CMA)) |
330 | ptr = __alloc_from_contiguous(NULL, pool->size, prot, &page); | |
331 | else | |
332 | ptr = __alloc_remap_buffer(NULL, pool->size, GFP_KERNEL, prot, | |
333 | &page, NULL); | |
c7909509 | 334 | if (ptr) { |
6b3fe472 HD |
335 | int i; |
336 | ||
337 | for (i = 0; i < nr_pages; i++) | |
338 | pages[i] = page + i; | |
339 | ||
e9da6e99 MS |
340 | spin_lock_init(&pool->lock); |
341 | pool->vaddr = ptr; | |
6b3fe472 | 342 | pool->pages = pages; |
e9da6e99 MS |
343 | pool->bitmap = bitmap; |
344 | pool->nr_pages = nr_pages; | |
345 | pr_info("DMA: preallocated %u KiB pool for atomic coherent allocations\n", | |
346 | (unsigned)pool->size / 1024); | |
c7909509 MS |
347 | return 0; |
348 | } | |
ec10665c SK |
349 | |
350 | kfree(pages); | |
6b3fe472 | 351 | no_pages: |
e9da6e99 MS |
352 | kfree(bitmap); |
353 | no_bitmap: | |
354 | pr_err("DMA: failed to allocate %u KiB pool for atomic coherent allocation\n", | |
355 | (unsigned)pool->size / 1024); | |
c7909509 MS |
356 | return -ENOMEM; |
357 | } | |
358 | /* | |
359 | * CMA is activated by core_initcall, so we must be called after it. | |
360 | */ | |
e9da6e99 | 361 | postcore_initcall(atomic_pool_init); |
c7909509 MS |
362 | |
363 | struct dma_contig_early_reserve { | |
364 | phys_addr_t base; | |
365 | unsigned long size; | |
366 | }; | |
367 | ||
368 | static struct dma_contig_early_reserve dma_mmu_remap[MAX_CMA_AREAS] __initdata; | |
369 | ||
370 | static int dma_mmu_remap_num __initdata; | |
371 | ||
372 | void __init dma_contiguous_early_fixup(phys_addr_t base, unsigned long size) | |
373 | { | |
374 | dma_mmu_remap[dma_mmu_remap_num].base = base; | |
375 | dma_mmu_remap[dma_mmu_remap_num].size = size; | |
376 | dma_mmu_remap_num++; | |
377 | } | |
378 | ||
379 | void __init dma_contiguous_remap(void) | |
380 | { | |
381 | int i; | |
382 | for (i = 0; i < dma_mmu_remap_num; i++) { | |
383 | phys_addr_t start = dma_mmu_remap[i].base; | |
384 | phys_addr_t end = start + dma_mmu_remap[i].size; | |
385 | struct map_desc map; | |
386 | unsigned long addr; | |
387 | ||
388 | if (end > arm_lowmem_limit) | |
389 | end = arm_lowmem_limit; | |
390 | if (start >= end) | |
39f78e70 | 391 | continue; |
c7909509 MS |
392 | |
393 | map.pfn = __phys_to_pfn(start); | |
394 | map.virtual = __phys_to_virt(start); | |
395 | map.length = end - start; | |
396 | map.type = MT_MEMORY_DMA_READY; | |
397 | ||
398 | /* | |
399 | * Clear previous low-memory mapping | |
400 | */ | |
401 | for (addr = __phys_to_virt(start); addr < __phys_to_virt(end); | |
61f6c7a4 | 402 | addr += PMD_SIZE) |
c7909509 MS |
403 | pmd_clear(pmd_off_k(addr)); |
404 | ||
405 | iotable_init(&map, 1); | |
406 | } | |
407 | } | |
408 | ||
c7909509 MS |
409 | static int __dma_update_pte(pte_t *pte, pgtable_t token, unsigned long addr, |
410 | void *data) | |
411 | { | |
412 | struct page *page = virt_to_page(addr); | |
413 | pgprot_t prot = *(pgprot_t *)data; | |
414 | ||
415 | set_pte_ext(pte, mk_pte(page, prot), 0); | |
416 | return 0; | |
417 | } | |
418 | ||
419 | static void __dma_remap(struct page *page, size_t size, pgprot_t prot) | |
420 | { | |
421 | unsigned long start = (unsigned long) page_address(page); | |
422 | unsigned end = start + size; | |
423 | ||
424 | apply_to_page_range(&init_mm, start, size, __dma_update_pte, &prot); | |
425 | dsb(); | |
426 | flush_tlb_kernel_range(start, end); | |
427 | } | |
428 | ||
429 | static void *__alloc_remap_buffer(struct device *dev, size_t size, gfp_t gfp, | |
430 | pgprot_t prot, struct page **ret_page, | |
431 | const void *caller) | |
432 | { | |
433 | struct page *page; | |
434 | void *ptr; | |
435 | page = __dma_alloc_buffer(dev, size, gfp); | |
436 | if (!page) | |
437 | return NULL; | |
438 | ||
439 | ptr = __dma_alloc_remap(page, size, gfp, prot, caller); | |
440 | if (!ptr) { | |
441 | __dma_free_buffer(page, size); | |
442 | return NULL; | |
443 | } | |
444 | ||
445 | *ret_page = page; | |
446 | return ptr; | |
447 | } | |
448 | ||
e9da6e99 | 449 | static void *__alloc_from_pool(size_t size, struct page **ret_page) |
c7909509 | 450 | { |
e9da6e99 MS |
451 | struct dma_pool *pool = &atomic_pool; |
452 | unsigned int count = PAGE_ALIGN(size) >> PAGE_SHIFT; | |
453 | unsigned int pageno; | |
454 | unsigned long flags; | |
455 | void *ptr = NULL; | |
e4ea6918 | 456 | unsigned long align_mask; |
c7909509 | 457 | |
e9da6e99 MS |
458 | if (!pool->vaddr) { |
459 | WARN(1, "coherent pool not initialised!\n"); | |
c7909509 MS |
460 | return NULL; |
461 | } | |
462 | ||
463 | /* | |
464 | * Align the region allocation - allocations from pool are rather | |
465 | * small, so align them to their order in pages, minimum is a page | |
466 | * size. This helps reduce fragmentation of the DMA space. | |
467 | */ | |
e4ea6918 | 468 | align_mask = (1 << get_order(size)) - 1; |
e9da6e99 MS |
469 | |
470 | spin_lock_irqsave(&pool->lock, flags); | |
471 | pageno = bitmap_find_next_zero_area(pool->bitmap, pool->nr_pages, | |
e4ea6918 | 472 | 0, count, align_mask); |
e9da6e99 MS |
473 | if (pageno < pool->nr_pages) { |
474 | bitmap_set(pool->bitmap, pageno, count); | |
475 | ptr = pool->vaddr + PAGE_SIZE * pageno; | |
6b3fe472 | 476 | *ret_page = pool->pages[pageno]; |
fb71285f MS |
477 | } else { |
478 | pr_err_once("ERROR: %u KiB atomic DMA coherent pool is too small!\n" | |
479 | "Please increase it with coherent_pool= kernel parameter!\n", | |
480 | (unsigned)pool->size / 1024); | |
c7909509 | 481 | } |
e9da6e99 MS |
482 | spin_unlock_irqrestore(&pool->lock, flags); |
483 | ||
484 | return ptr; | |
c7909509 MS |
485 | } |
486 | ||
21d0a759 HD |
487 | static bool __in_atomic_pool(void *start, size_t size) |
488 | { | |
489 | struct dma_pool *pool = &atomic_pool; | |
490 | void *end = start + size; | |
491 | void *pool_start = pool->vaddr; | |
492 | void *pool_end = pool->vaddr + pool->size; | |
493 | ||
f3d87524 | 494 | if (start < pool_start || start >= pool_end) |
21d0a759 HD |
495 | return false; |
496 | ||
497 | if (end <= pool_end) | |
498 | return true; | |
499 | ||
500 | WARN(1, "Wrong coherent size(%p-%p) from atomic pool(%p-%p)\n", | |
501 | start, end - 1, pool_start, pool_end - 1); | |
502 | ||
503 | return false; | |
504 | } | |
505 | ||
e9da6e99 | 506 | static int __free_from_pool(void *start, size_t size) |
c7909509 | 507 | { |
e9da6e99 MS |
508 | struct dma_pool *pool = &atomic_pool; |
509 | unsigned long pageno, count; | |
510 | unsigned long flags; | |
c7909509 | 511 | |
21d0a759 | 512 | if (!__in_atomic_pool(start, size)) |
c7909509 MS |
513 | return 0; |
514 | ||
e9da6e99 MS |
515 | pageno = (start - pool->vaddr) >> PAGE_SHIFT; |
516 | count = size >> PAGE_SHIFT; | |
517 | ||
518 | spin_lock_irqsave(&pool->lock, flags); | |
519 | bitmap_clear(pool->bitmap, pageno, count); | |
520 | spin_unlock_irqrestore(&pool->lock, flags); | |
521 | ||
c7909509 MS |
522 | return 1; |
523 | } | |
524 | ||
525 | static void *__alloc_from_contiguous(struct device *dev, size_t size, | |
526 | pgprot_t prot, struct page **ret_page) | |
527 | { | |
528 | unsigned long order = get_order(size); | |
529 | size_t count = size >> PAGE_SHIFT; | |
530 | struct page *page; | |
531 | ||
532 | page = dma_alloc_from_contiguous(dev, count, order); | |
533 | if (!page) | |
534 | return NULL; | |
535 | ||
536 | __dma_clear_buffer(page, size); | |
537 | __dma_remap(page, size, prot); | |
538 | ||
539 | *ret_page = page; | |
540 | return page_address(page); | |
541 | } | |
542 | ||
543 | static void __free_from_contiguous(struct device *dev, struct page *page, | |
544 | size_t size) | |
545 | { | |
546 | __dma_remap(page, size, pgprot_kernel); | |
547 | dma_release_from_contiguous(dev, page, size >> PAGE_SHIFT); | |
548 | } | |
549 | ||
f99d6034 MS |
550 | static inline pgprot_t __get_dma_pgprot(struct dma_attrs *attrs, pgprot_t prot) |
551 | { | |
552 | prot = dma_get_attr(DMA_ATTR_WRITE_COMBINE, attrs) ? | |
553 | pgprot_writecombine(prot) : | |
554 | pgprot_dmacoherent(prot); | |
555 | return prot; | |
556 | } | |
557 | ||
c7909509 MS |
558 | #define nommu() 0 |
559 | ||
ab6494f0 | 560 | #else /* !CONFIG_MMU */ |
695ae0af | 561 | |
c7909509 MS |
562 | #define nommu() 1 |
563 | ||
f99d6034 | 564 | #define __get_dma_pgprot(attrs, prot) __pgprot(0) |
c7909509 | 565 | #define __alloc_remap_buffer(dev, size, gfp, prot, ret, c) NULL |
e9da6e99 | 566 | #define __alloc_from_pool(size, ret_page) NULL |
c7909509 MS |
567 | #define __alloc_from_contiguous(dev, size, prot, ret) NULL |
568 | #define __free_from_pool(cpu_addr, size) 0 | |
569 | #define __free_from_contiguous(dev, page, size) do { } while (0) | |
570 | #define __dma_free_remap(cpu_addr, size) do { } while (0) | |
31ebf944 RK |
571 | |
572 | #endif /* CONFIG_MMU */ | |
573 | ||
c7909509 MS |
574 | static void *__alloc_simple_buffer(struct device *dev, size_t size, gfp_t gfp, |
575 | struct page **ret_page) | |
ab6494f0 | 576 | { |
c7909509 MS |
577 | struct page *page; |
578 | page = __dma_alloc_buffer(dev, size, gfp); | |
579 | if (!page) | |
580 | return NULL; | |
581 | ||
582 | *ret_page = page; | |
583 | return page_address(page); | |
584 | } | |
585 | ||
586 | ||
587 | ||
588 | static void *__dma_alloc(struct device *dev, size_t size, dma_addr_t *handle, | |
589 | gfp_t gfp, pgprot_t prot, const void *caller) | |
590 | { | |
591 | u64 mask = get_coherent_dma_mask(dev); | |
04da5694 | 592 | struct page *page; |
31ebf944 | 593 | void *addr; |
ab6494f0 | 594 | |
c7909509 MS |
595 | #ifdef CONFIG_DMA_API_DEBUG |
596 | u64 limit = (mask + 1) & ~mask; | |
597 | if (limit && size >= limit) { | |
598 | dev_warn(dev, "coherent allocation too big (requested %#x mask %#llx)\n", | |
599 | size, mask); | |
600 | return NULL; | |
601 | } | |
602 | #endif | |
603 | ||
604 | if (!mask) | |
605 | return NULL; | |
606 | ||
607 | if (mask < 0xffffffffULL) | |
608 | gfp |= GFP_DMA; | |
609 | ||
ea2e7057 SB |
610 | /* |
611 | * Following is a work-around (a.k.a. hack) to prevent pages | |
612 | * with __GFP_COMP being passed to split_page() which cannot | |
613 | * handle them. The real problem is that this flag probably | |
614 | * should be 0 on ARM as it is not supported on this | |
615 | * platform; see CONFIG_HUGETLBFS. | |
616 | */ | |
617 | gfp &= ~(__GFP_COMP); | |
618 | ||
553ac788 | 619 | *handle = DMA_ERROR_CODE; |
04da5694 | 620 | size = PAGE_ALIGN(size); |
ab6494f0 | 621 | |
c7909509 MS |
622 | if (arch_is_coherent() || nommu()) |
623 | addr = __alloc_simple_buffer(dev, size, gfp, &page); | |
e9da6e99 MS |
624 | else if (gfp & GFP_ATOMIC) |
625 | addr = __alloc_from_pool(size, &page); | |
f1ae98da | 626 | else if (!IS_ENABLED(CONFIG_CMA)) |
c7909509 | 627 | addr = __alloc_remap_buffer(dev, size, gfp, prot, &page, caller); |
31ebf944 | 628 | else |
c7909509 | 629 | addr = __alloc_from_contiguous(dev, size, prot, &page); |
695ae0af | 630 | |
31ebf944 | 631 | if (addr) |
9eedd963 | 632 | *handle = pfn_to_dma(dev, page_to_pfn(page)); |
695ae0af | 633 | |
31ebf944 RK |
634 | return addr; |
635 | } | |
1da177e4 LT |
636 | |
637 | /* | |
638 | * Allocate DMA-coherent memory space and return both the kernel remapped | |
639 | * virtual and bus address for that space. | |
640 | */ | |
f99d6034 MS |
641 | void *arm_dma_alloc(struct device *dev, size_t size, dma_addr_t *handle, |
642 | gfp_t gfp, struct dma_attrs *attrs) | |
1da177e4 | 643 | { |
f99d6034 | 644 | pgprot_t prot = __get_dma_pgprot(attrs, pgprot_kernel); |
1fe53268 DB |
645 | void *memory; |
646 | ||
647 | if (dma_alloc_from_coherent(dev, size, handle, &memory)) | |
648 | return memory; | |
649 | ||
f99d6034 | 650 | return __dma_alloc(dev, size, handle, gfp, prot, |
45cd5290 | 651 | __builtin_return_address(0)); |
1da177e4 | 652 | } |
1da177e4 LT |
653 | |
654 | /* | |
f99d6034 | 655 | * Create userspace mapping for the DMA-coherent memory. |
1da177e4 | 656 | */ |
f99d6034 MS |
657 | int arm_dma_mmap(struct device *dev, struct vm_area_struct *vma, |
658 | void *cpu_addr, dma_addr_t dma_addr, size_t size, | |
659 | struct dma_attrs *attrs) | |
1da177e4 | 660 | { |
ab6494f0 CM |
661 | int ret = -ENXIO; |
662 | #ifdef CONFIG_MMU | |
50262a4b MS |
663 | unsigned long nr_vma_pages = (vma->vm_end - vma->vm_start) >> PAGE_SHIFT; |
664 | unsigned long nr_pages = PAGE_ALIGN(size) >> PAGE_SHIFT; | |
c7909509 | 665 | unsigned long pfn = dma_to_pfn(dev, dma_addr); |
50262a4b MS |
666 | unsigned long off = vma->vm_pgoff; |
667 | ||
f99d6034 MS |
668 | vma->vm_page_prot = __get_dma_pgprot(attrs, vma->vm_page_prot); |
669 | ||
47142f07 MS |
670 | if (dma_mmap_from_coherent(dev, vma, cpu_addr, size, &ret)) |
671 | return ret; | |
672 | ||
50262a4b MS |
673 | if (off < nr_pages && nr_vma_pages <= (nr_pages - off)) { |
674 | ret = remap_pfn_range(vma, vma->vm_start, | |
675 | pfn + off, | |
676 | vma->vm_end - vma->vm_start, | |
677 | vma->vm_page_prot); | |
678 | } | |
ab6494f0 | 679 | #endif /* CONFIG_MMU */ |
1da177e4 LT |
680 | |
681 | return ret; | |
682 | } | |
683 | ||
1da177e4 | 684 | /* |
c7909509 | 685 | * Free a buffer as defined by the above mapping. |
1da177e4 | 686 | */ |
f99d6034 MS |
687 | void arm_dma_free(struct device *dev, size_t size, void *cpu_addr, |
688 | dma_addr_t handle, struct dma_attrs *attrs) | |
1da177e4 | 689 | { |
c7909509 | 690 | struct page *page = pfn_to_page(dma_to_pfn(dev, handle)); |
5edf71ae | 691 | |
1fe53268 DB |
692 | if (dma_release_from_coherent(dev, get_order(size), cpu_addr)) |
693 | return; | |
694 | ||
3e82d012 RK |
695 | size = PAGE_ALIGN(size); |
696 | ||
c7909509 MS |
697 | if (arch_is_coherent() || nommu()) { |
698 | __dma_free_buffer(page, size); | |
d9e0d149 AK |
699 | } else if (__free_from_pool(cpu_addr, size)) { |
700 | return; | |
f1ae98da | 701 | } else if (!IS_ENABLED(CONFIG_CMA)) { |
695ae0af | 702 | __dma_free_remap(cpu_addr, size); |
c7909509 MS |
703 | __dma_free_buffer(page, size); |
704 | } else { | |
c7909509 MS |
705 | /* |
706 | * Non-atomic allocations cannot be freed with IRQs disabled | |
707 | */ | |
708 | WARN_ON(irqs_disabled()); | |
709 | __free_from_contiguous(dev, page, size); | |
710 | } | |
1da177e4 | 711 | } |
afd1a321 | 712 | |
dc2832e1 MS |
713 | int arm_dma_get_sgtable(struct device *dev, struct sg_table *sgt, |
714 | void *cpu_addr, dma_addr_t handle, size_t size, | |
715 | struct dma_attrs *attrs) | |
716 | { | |
717 | struct page *page = pfn_to_page(dma_to_pfn(dev, handle)); | |
718 | int ret; | |
719 | ||
720 | ret = sg_alloc_table(sgt, 1, GFP_KERNEL); | |
721 | if (unlikely(ret)) | |
722 | return ret; | |
723 | ||
724 | sg_set_page(sgt->sgl, page, PAGE_ALIGN(size), 0); | |
725 | return 0; | |
726 | } | |
727 | ||
4ea0d737 | 728 | static void dma_cache_maint_page(struct page *page, unsigned long offset, |
a9c9147e RK |
729 | size_t size, enum dma_data_direction dir, |
730 | void (*op)(const void *, size_t, int)) | |
43377453 NP |
731 | { |
732 | /* | |
733 | * A single sg entry may refer to multiple physically contiguous | |
734 | * pages. But we still need to process highmem pages individually. | |
735 | * If highmem is not configured then the bulk of this loop gets | |
736 | * optimized out. | |
737 | */ | |
738 | size_t left = size; | |
739 | do { | |
740 | size_t len = left; | |
93f1d629 RK |
741 | void *vaddr; |
742 | ||
743 | if (PageHighMem(page)) { | |
744 | if (len + offset > PAGE_SIZE) { | |
745 | if (offset >= PAGE_SIZE) { | |
746 | page += offset / PAGE_SIZE; | |
747 | offset %= PAGE_SIZE; | |
748 | } | |
749 | len = PAGE_SIZE - offset; | |
750 | } | |
751 | vaddr = kmap_high_get(page); | |
752 | if (vaddr) { | |
753 | vaddr += offset; | |
a9c9147e | 754 | op(vaddr, len, dir); |
93f1d629 | 755 | kunmap_high(page); |
7e5a69e8 | 756 | } else if (cache_is_vipt()) { |
39af22a7 NP |
757 | /* unmapped pages might still be cached */ |
758 | vaddr = kmap_atomic(page); | |
7e5a69e8 | 759 | op(vaddr + offset, len, dir); |
39af22a7 | 760 | kunmap_atomic(vaddr); |
43377453 | 761 | } |
93f1d629 RK |
762 | } else { |
763 | vaddr = page_address(page) + offset; | |
a9c9147e | 764 | op(vaddr, len, dir); |
43377453 | 765 | } |
43377453 NP |
766 | offset = 0; |
767 | page++; | |
768 | left -= len; | |
769 | } while (left); | |
770 | } | |
4ea0d737 | 771 | |
51fde349 MS |
772 | /* |
773 | * Make an area consistent for devices. | |
774 | * Note: Drivers should NOT use this function directly, as it will break | |
775 | * platforms with CONFIG_DMABOUNCE. | |
776 | * Use the driver DMA support - see dma-mapping.h (dma_sync_*) | |
777 | */ | |
778 | static void __dma_page_cpu_to_dev(struct page *page, unsigned long off, | |
4ea0d737 RK |
779 | size_t size, enum dma_data_direction dir) |
780 | { | |
65af191a | 781 | unsigned long paddr; |
65af191a | 782 | |
a9c9147e | 783 | dma_cache_maint_page(page, off, size, dir, dmac_map_area); |
65af191a RK |
784 | |
785 | paddr = page_to_phys(page) + off; | |
2ffe2da3 RK |
786 | if (dir == DMA_FROM_DEVICE) { |
787 | outer_inv_range(paddr, paddr + size); | |
788 | } else { | |
789 | outer_clean_range(paddr, paddr + size); | |
790 | } | |
791 | /* FIXME: non-speculating: flush on bidirectional mappings? */ | |
4ea0d737 | 792 | } |
4ea0d737 | 793 | |
51fde349 | 794 | static void __dma_page_dev_to_cpu(struct page *page, unsigned long off, |
4ea0d737 RK |
795 | size_t size, enum dma_data_direction dir) |
796 | { | |
2ffe2da3 RK |
797 | unsigned long paddr = page_to_phys(page) + off; |
798 | ||
799 | /* FIXME: non-speculating: not required */ | |
800 | /* don't bother invalidating if DMA to device */ | |
801 | if (dir != DMA_TO_DEVICE) | |
802 | outer_inv_range(paddr, paddr + size); | |
803 | ||
a9c9147e | 804 | dma_cache_maint_page(page, off, size, dir, dmac_unmap_area); |
c0177800 CM |
805 | |
806 | /* | |
807 | * Mark the D-cache clean for this page to avoid extra flushing. | |
808 | */ | |
809 | if (dir != DMA_TO_DEVICE && off == 0 && size >= PAGE_SIZE) | |
810 | set_bit(PG_dcache_clean, &page->flags); | |
4ea0d737 | 811 | } |
43377453 | 812 | |
afd1a321 | 813 | /** |
2a550e73 | 814 | * arm_dma_map_sg - map a set of SG buffers for streaming mode DMA |
afd1a321 RK |
815 | * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices |
816 | * @sg: list of buffers | |
817 | * @nents: number of buffers to map | |
818 | * @dir: DMA transfer direction | |
819 | * | |
820 | * Map a set of buffers described by scatterlist in streaming mode for DMA. | |
821 | * This is the scatter-gather version of the dma_map_single interface. | |
822 | * Here the scatter gather list elements are each tagged with the | |
823 | * appropriate dma address and length. They are obtained via | |
824 | * sg_dma_{address,length}. | |
825 | * | |
826 | * Device ownership issues as mentioned for dma_map_single are the same | |
827 | * here. | |
828 | */ | |
2dc6a016 MS |
829 | int arm_dma_map_sg(struct device *dev, struct scatterlist *sg, int nents, |
830 | enum dma_data_direction dir, struct dma_attrs *attrs) | |
afd1a321 | 831 | { |
2a550e73 | 832 | struct dma_map_ops *ops = get_dma_ops(dev); |
afd1a321 | 833 | struct scatterlist *s; |
01135d92 | 834 | int i, j; |
afd1a321 RK |
835 | |
836 | for_each_sg(sg, s, nents, i) { | |
4ce63fcd MS |
837 | #ifdef CONFIG_NEED_SG_DMA_LENGTH |
838 | s->dma_length = s->length; | |
839 | #endif | |
2a550e73 MS |
840 | s->dma_address = ops->map_page(dev, sg_page(s), s->offset, |
841 | s->length, dir, attrs); | |
01135d92 RK |
842 | if (dma_mapping_error(dev, s->dma_address)) |
843 | goto bad_mapping; | |
afd1a321 | 844 | } |
afd1a321 | 845 | return nents; |
01135d92 RK |
846 | |
847 | bad_mapping: | |
848 | for_each_sg(sg, s, i, j) | |
2a550e73 | 849 | ops->unmap_page(dev, sg_dma_address(s), sg_dma_len(s), dir, attrs); |
01135d92 | 850 | return 0; |
afd1a321 | 851 | } |
afd1a321 RK |
852 | |
853 | /** | |
2a550e73 | 854 | * arm_dma_unmap_sg - unmap a set of SG buffers mapped by dma_map_sg |
afd1a321 RK |
855 | * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices |
856 | * @sg: list of buffers | |
0adfca6f | 857 | * @nents: number of buffers to unmap (same as was passed to dma_map_sg) |
afd1a321 RK |
858 | * @dir: DMA transfer direction (same as was passed to dma_map_sg) |
859 | * | |
860 | * Unmap a set of streaming mode DMA translations. Again, CPU access | |
861 | * rules concerning calls here are the same as for dma_unmap_single(). | |
862 | */ | |
2dc6a016 MS |
863 | void arm_dma_unmap_sg(struct device *dev, struct scatterlist *sg, int nents, |
864 | enum dma_data_direction dir, struct dma_attrs *attrs) | |
afd1a321 | 865 | { |
2a550e73 | 866 | struct dma_map_ops *ops = get_dma_ops(dev); |
01135d92 | 867 | struct scatterlist *s; |
01135d92 | 868 | |
01135d92 | 869 | int i; |
24056f52 | 870 | |
01135d92 | 871 | for_each_sg(sg, s, nents, i) |
2a550e73 | 872 | ops->unmap_page(dev, sg_dma_address(s), sg_dma_len(s), dir, attrs); |
afd1a321 | 873 | } |
afd1a321 RK |
874 | |
875 | /** | |
2a550e73 | 876 | * arm_dma_sync_sg_for_cpu |
afd1a321 RK |
877 | * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices |
878 | * @sg: list of buffers | |
879 | * @nents: number of buffers to map (returned from dma_map_sg) | |
880 | * @dir: DMA transfer direction (same as was passed to dma_map_sg) | |
881 | */ | |
2dc6a016 | 882 | void arm_dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg, |
afd1a321 RK |
883 | int nents, enum dma_data_direction dir) |
884 | { | |
2a550e73 | 885 | struct dma_map_ops *ops = get_dma_ops(dev); |
afd1a321 RK |
886 | struct scatterlist *s; |
887 | int i; | |
888 | ||
2a550e73 MS |
889 | for_each_sg(sg, s, nents, i) |
890 | ops->sync_single_for_cpu(dev, sg_dma_address(s), s->length, | |
891 | dir); | |
afd1a321 | 892 | } |
afd1a321 RK |
893 | |
894 | /** | |
2a550e73 | 895 | * arm_dma_sync_sg_for_device |
afd1a321 RK |
896 | * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices |
897 | * @sg: list of buffers | |
898 | * @nents: number of buffers to map (returned from dma_map_sg) | |
899 | * @dir: DMA transfer direction (same as was passed to dma_map_sg) | |
900 | */ | |
2dc6a016 | 901 | void arm_dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg, |
afd1a321 RK |
902 | int nents, enum dma_data_direction dir) |
903 | { | |
2a550e73 | 904 | struct dma_map_ops *ops = get_dma_ops(dev); |
afd1a321 RK |
905 | struct scatterlist *s; |
906 | int i; | |
907 | ||
2a550e73 MS |
908 | for_each_sg(sg, s, nents, i) |
909 | ops->sync_single_for_device(dev, sg_dma_address(s), s->length, | |
910 | dir); | |
afd1a321 | 911 | } |
24056f52 | 912 | |
022ae537 RK |
913 | /* |
914 | * Return whether the given device DMA address mask can be supported | |
915 | * properly. For example, if your device can only drive the low 24-bits | |
916 | * during bus mastering, then you would pass 0x00ffffff as the mask | |
917 | * to this function. | |
918 | */ | |
919 | int dma_supported(struct device *dev, u64 mask) | |
920 | { | |
921 | if (mask < (u64)arm_dma_limit) | |
922 | return 0; | |
923 | return 1; | |
924 | } | |
925 | EXPORT_SYMBOL(dma_supported); | |
926 | ||
2dc6a016 | 927 | static int arm_dma_set_mask(struct device *dev, u64 dma_mask) |
022ae537 RK |
928 | { |
929 | if (!dev->dma_mask || !dma_supported(dev, dma_mask)) | |
930 | return -EIO; | |
931 | ||
022ae537 | 932 | *dev->dma_mask = dma_mask; |
022ae537 RK |
933 | |
934 | return 0; | |
935 | } | |
022ae537 | 936 | |
24056f52 RK |
937 | #define PREALLOC_DMA_DEBUG_ENTRIES 4096 |
938 | ||
939 | static int __init dma_debug_do_init(void) | |
940 | { | |
941 | dma_debug_init(PREALLOC_DMA_DEBUG_ENTRIES); | |
942 | return 0; | |
943 | } | |
944 | fs_initcall(dma_debug_do_init); | |
4ce63fcd MS |
945 | |
946 | #ifdef CONFIG_ARM_DMA_USE_IOMMU | |
947 | ||
948 | /* IOMMU */ | |
949 | ||
950 | static inline dma_addr_t __alloc_iova(struct dma_iommu_mapping *mapping, | |
951 | size_t size) | |
952 | { | |
953 | unsigned int order = get_order(size); | |
954 | unsigned int align = 0; | |
955 | unsigned int count, start; | |
956 | unsigned long flags; | |
957 | ||
958 | count = ((PAGE_ALIGN(size) >> PAGE_SHIFT) + | |
959 | (1 << mapping->order) - 1) >> mapping->order; | |
960 | ||
961 | if (order > mapping->order) | |
962 | align = (1 << (order - mapping->order)) - 1; | |
963 | ||
964 | spin_lock_irqsave(&mapping->lock, flags); | |
965 | start = bitmap_find_next_zero_area(mapping->bitmap, mapping->bits, 0, | |
966 | count, align); | |
967 | if (start > mapping->bits) { | |
968 | spin_unlock_irqrestore(&mapping->lock, flags); | |
969 | return DMA_ERROR_CODE; | |
970 | } | |
971 | ||
972 | bitmap_set(mapping->bitmap, start, count); | |
973 | spin_unlock_irqrestore(&mapping->lock, flags); | |
974 | ||
975 | return mapping->base + (start << (mapping->order + PAGE_SHIFT)); | |
976 | } | |
977 | ||
978 | static inline void __free_iova(struct dma_iommu_mapping *mapping, | |
979 | dma_addr_t addr, size_t size) | |
980 | { | |
981 | unsigned int start = (addr - mapping->base) >> | |
982 | (mapping->order + PAGE_SHIFT); | |
983 | unsigned int count = ((size >> PAGE_SHIFT) + | |
984 | (1 << mapping->order) - 1) >> mapping->order; | |
985 | unsigned long flags; | |
986 | ||
987 | spin_lock_irqsave(&mapping->lock, flags); | |
988 | bitmap_clear(mapping->bitmap, start, count); | |
989 | spin_unlock_irqrestore(&mapping->lock, flags); | |
990 | } | |
991 | ||
992 | static struct page **__iommu_alloc_buffer(struct device *dev, size_t size, gfp_t gfp) | |
993 | { | |
994 | struct page **pages; | |
995 | int count = size >> PAGE_SHIFT; | |
996 | int array_size = count * sizeof(struct page *); | |
997 | int i = 0; | |
998 | ||
999 | if (array_size <= PAGE_SIZE) | |
1000 | pages = kzalloc(array_size, gfp); | |
1001 | else | |
1002 | pages = vzalloc(array_size); | |
1003 | if (!pages) | |
1004 | return NULL; | |
1005 | ||
1006 | while (count) { | |
593f4735 | 1007 | int j, order = __fls(count); |
4ce63fcd MS |
1008 | |
1009 | pages[i] = alloc_pages(gfp | __GFP_NOWARN, order); | |
1010 | while (!pages[i] && order) | |
1011 | pages[i] = alloc_pages(gfp | __GFP_NOWARN, --order); | |
1012 | if (!pages[i]) | |
1013 | goto error; | |
1014 | ||
5a796eeb | 1015 | if (order) { |
4ce63fcd | 1016 | split_page(pages[i], order); |
5a796eeb HD |
1017 | j = 1 << order; |
1018 | while (--j) | |
1019 | pages[i + j] = pages[i] + j; | |
1020 | } | |
4ce63fcd MS |
1021 | |
1022 | __dma_clear_buffer(pages[i], PAGE_SIZE << order); | |
1023 | i += 1 << order; | |
1024 | count -= 1 << order; | |
1025 | } | |
1026 | ||
1027 | return pages; | |
1028 | error: | |
9fa8af91 | 1029 | while (i--) |
4ce63fcd MS |
1030 | if (pages[i]) |
1031 | __free_pages(pages[i], 0); | |
46c87852 | 1032 | if (array_size <= PAGE_SIZE) |
4ce63fcd MS |
1033 | kfree(pages); |
1034 | else | |
1035 | vfree(pages); | |
1036 | return NULL; | |
1037 | } | |
1038 | ||
1039 | static int __iommu_free_buffer(struct device *dev, struct page **pages, size_t size) | |
1040 | { | |
1041 | int count = size >> PAGE_SHIFT; | |
1042 | int array_size = count * sizeof(struct page *); | |
1043 | int i; | |
1044 | for (i = 0; i < count; i++) | |
1045 | if (pages[i]) | |
1046 | __free_pages(pages[i], 0); | |
46c87852 | 1047 | if (array_size <= PAGE_SIZE) |
4ce63fcd MS |
1048 | kfree(pages); |
1049 | else | |
1050 | vfree(pages); | |
1051 | return 0; | |
1052 | } | |
1053 | ||
1054 | /* | |
1055 | * Create a CPU mapping for a specified pages | |
1056 | */ | |
1057 | static void * | |
e9da6e99 MS |
1058 | __iommu_alloc_remap(struct page **pages, size_t size, gfp_t gfp, pgprot_t prot, |
1059 | const void *caller) | |
4ce63fcd | 1060 | { |
e9da6e99 MS |
1061 | unsigned int i, nr_pages = PAGE_ALIGN(size) >> PAGE_SHIFT; |
1062 | struct vm_struct *area; | |
1063 | unsigned long p; | |
4ce63fcd | 1064 | |
e9da6e99 MS |
1065 | area = get_vm_area_caller(size, VM_ARM_DMA_CONSISTENT | VM_USERMAP, |
1066 | caller); | |
1067 | if (!area) | |
4ce63fcd | 1068 | return NULL; |
4ce63fcd | 1069 | |
e9da6e99 MS |
1070 | area->pages = pages; |
1071 | area->nr_pages = nr_pages; | |
1072 | p = (unsigned long)area->addr; | |
4ce63fcd | 1073 | |
e9da6e99 MS |
1074 | for (i = 0; i < nr_pages; i++) { |
1075 | phys_addr_t phys = __pfn_to_phys(page_to_pfn(pages[i])); | |
1076 | if (ioremap_page_range(p, p + PAGE_SIZE, phys, prot)) | |
1077 | goto err; | |
1078 | p += PAGE_SIZE; | |
4ce63fcd | 1079 | } |
e9da6e99 MS |
1080 | return area->addr; |
1081 | err: | |
1082 | unmap_kernel_range((unsigned long)area->addr, size); | |
1083 | vunmap(area->addr); | |
4ce63fcd MS |
1084 | return NULL; |
1085 | } | |
1086 | ||
1087 | /* | |
1088 | * Create a mapping in device IO address space for specified pages | |
1089 | */ | |
1090 | static dma_addr_t | |
1091 | __iommu_create_mapping(struct device *dev, struct page **pages, size_t size) | |
1092 | { | |
1093 | struct dma_iommu_mapping *mapping = dev->archdata.mapping; | |
1094 | unsigned int count = PAGE_ALIGN(size) >> PAGE_SHIFT; | |
1095 | dma_addr_t dma_addr, iova; | |
1096 | int i, ret = DMA_ERROR_CODE; | |
1097 | ||
1098 | dma_addr = __alloc_iova(mapping, size); | |
1099 | if (dma_addr == DMA_ERROR_CODE) | |
1100 | return dma_addr; | |
1101 | ||
1102 | iova = dma_addr; | |
1103 | for (i = 0; i < count; ) { | |
1104 | unsigned int next_pfn = page_to_pfn(pages[i]) + 1; | |
1105 | phys_addr_t phys = page_to_phys(pages[i]); | |
1106 | unsigned int len, j; | |
1107 | ||
1108 | for (j = i + 1; j < count; j++, next_pfn++) | |
1109 | if (page_to_pfn(pages[j]) != next_pfn) | |
1110 | break; | |
1111 | ||
1112 | len = (j - i) << PAGE_SHIFT; | |
1113 | ret = iommu_map(mapping->domain, iova, phys, len, 0); | |
1114 | if (ret < 0) | |
1115 | goto fail; | |
1116 | iova += len; | |
1117 | i = j; | |
1118 | } | |
1119 | return dma_addr; | |
1120 | fail: | |
1121 | iommu_unmap(mapping->domain, dma_addr, iova-dma_addr); | |
1122 | __free_iova(mapping, dma_addr, size); | |
1123 | return DMA_ERROR_CODE; | |
1124 | } | |
1125 | ||
1126 | static int __iommu_remove_mapping(struct device *dev, dma_addr_t iova, size_t size) | |
1127 | { | |
1128 | struct dma_iommu_mapping *mapping = dev->archdata.mapping; | |
1129 | ||
1130 | /* | |
1131 | * add optional in-page offset from iova to size and align | |
1132 | * result to page size | |
1133 | */ | |
1134 | size = PAGE_ALIGN((iova & ~PAGE_MASK) + size); | |
1135 | iova &= PAGE_MASK; | |
1136 | ||
1137 | iommu_unmap(mapping->domain, iova, size); | |
1138 | __free_iova(mapping, iova, size); | |
1139 | return 0; | |
1140 | } | |
1141 | ||
665bad7b HD |
1142 | static struct page **__atomic_get_pages(void *addr) |
1143 | { | |
1144 | struct dma_pool *pool = &atomic_pool; | |
1145 | struct page **pages = pool->pages; | |
1146 | int offs = (addr - pool->vaddr) >> PAGE_SHIFT; | |
1147 | ||
1148 | return pages + offs; | |
1149 | } | |
1150 | ||
955c757e | 1151 | static struct page **__iommu_get_pages(void *cpu_addr, struct dma_attrs *attrs) |
e9da6e99 MS |
1152 | { |
1153 | struct vm_struct *area; | |
1154 | ||
665bad7b HD |
1155 | if (__in_atomic_pool(cpu_addr, PAGE_SIZE)) |
1156 | return __atomic_get_pages(cpu_addr); | |
1157 | ||
955c757e MS |
1158 | if (dma_get_attr(DMA_ATTR_NO_KERNEL_MAPPING, attrs)) |
1159 | return cpu_addr; | |
1160 | ||
e9da6e99 MS |
1161 | area = find_vm_area(cpu_addr); |
1162 | if (area && (area->flags & VM_ARM_DMA_CONSISTENT)) | |
1163 | return area->pages; | |
1164 | return NULL; | |
1165 | } | |
1166 | ||
479ed93a HD |
1167 | static void *__iommu_alloc_atomic(struct device *dev, size_t size, |
1168 | dma_addr_t *handle) | |
1169 | { | |
1170 | struct page *page; | |
1171 | void *addr; | |
1172 | ||
1173 | addr = __alloc_from_pool(size, &page); | |
1174 | if (!addr) | |
1175 | return NULL; | |
1176 | ||
1177 | *handle = __iommu_create_mapping(dev, &page, size); | |
1178 | if (*handle == DMA_ERROR_CODE) | |
1179 | goto err_mapping; | |
1180 | ||
1181 | return addr; | |
1182 | ||
1183 | err_mapping: | |
1184 | __free_from_pool(addr, size); | |
1185 | return NULL; | |
1186 | } | |
1187 | ||
1188 | static void __iommu_free_atomic(struct device *dev, struct page **pages, | |
1189 | dma_addr_t handle, size_t size) | |
1190 | { | |
1191 | __iommu_remove_mapping(dev, handle, size); | |
1192 | __free_from_pool(page_address(pages[0]), size); | |
1193 | } | |
1194 | ||
4ce63fcd MS |
1195 | static void *arm_iommu_alloc_attrs(struct device *dev, size_t size, |
1196 | dma_addr_t *handle, gfp_t gfp, struct dma_attrs *attrs) | |
1197 | { | |
1198 | pgprot_t prot = __get_dma_pgprot(attrs, pgprot_kernel); | |
1199 | struct page **pages; | |
1200 | void *addr = NULL; | |
1201 | ||
1202 | *handle = DMA_ERROR_CODE; | |
1203 | size = PAGE_ALIGN(size); | |
1204 | ||
479ed93a HD |
1205 | if (gfp & GFP_ATOMIC) |
1206 | return __iommu_alloc_atomic(dev, size, handle); | |
1207 | ||
4ce63fcd MS |
1208 | pages = __iommu_alloc_buffer(dev, size, gfp); |
1209 | if (!pages) | |
1210 | return NULL; | |
1211 | ||
1212 | *handle = __iommu_create_mapping(dev, pages, size); | |
1213 | if (*handle == DMA_ERROR_CODE) | |
1214 | goto err_buffer; | |
1215 | ||
955c757e MS |
1216 | if (dma_get_attr(DMA_ATTR_NO_KERNEL_MAPPING, attrs)) |
1217 | return pages; | |
1218 | ||
e9da6e99 MS |
1219 | addr = __iommu_alloc_remap(pages, size, gfp, prot, |
1220 | __builtin_return_address(0)); | |
4ce63fcd MS |
1221 | if (!addr) |
1222 | goto err_mapping; | |
1223 | ||
1224 | return addr; | |
1225 | ||
1226 | err_mapping: | |
1227 | __iommu_remove_mapping(dev, *handle, size); | |
1228 | err_buffer: | |
1229 | __iommu_free_buffer(dev, pages, size); | |
1230 | return NULL; | |
1231 | } | |
1232 | ||
1233 | static int arm_iommu_mmap_attrs(struct device *dev, struct vm_area_struct *vma, | |
1234 | void *cpu_addr, dma_addr_t dma_addr, size_t size, | |
1235 | struct dma_attrs *attrs) | |
1236 | { | |
e9da6e99 MS |
1237 | unsigned long uaddr = vma->vm_start; |
1238 | unsigned long usize = vma->vm_end - vma->vm_start; | |
955c757e | 1239 | struct page **pages = __iommu_get_pages(cpu_addr, attrs); |
4ce63fcd MS |
1240 | |
1241 | vma->vm_page_prot = __get_dma_pgprot(attrs, vma->vm_page_prot); | |
4ce63fcd | 1242 | |
e9da6e99 MS |
1243 | if (!pages) |
1244 | return -ENXIO; | |
4ce63fcd | 1245 | |
e9da6e99 MS |
1246 | do { |
1247 | int ret = vm_insert_page(vma, uaddr, *pages++); | |
1248 | if (ret) { | |
1249 | pr_err("Remapping memory failed: %d\n", ret); | |
1250 | return ret; | |
1251 | } | |
1252 | uaddr += PAGE_SIZE; | |
1253 | usize -= PAGE_SIZE; | |
1254 | } while (usize > 0); | |
4ce63fcd | 1255 | |
4ce63fcd MS |
1256 | return 0; |
1257 | } | |
1258 | ||
1259 | /* | |
1260 | * free a page as defined by the above mapping. | |
1261 | * Must not be called with IRQs disabled. | |
1262 | */ | |
1263 | void arm_iommu_free_attrs(struct device *dev, size_t size, void *cpu_addr, | |
1264 | dma_addr_t handle, struct dma_attrs *attrs) | |
1265 | { | |
955c757e | 1266 | struct page **pages = __iommu_get_pages(cpu_addr, attrs); |
4ce63fcd MS |
1267 | size = PAGE_ALIGN(size); |
1268 | ||
e9da6e99 MS |
1269 | if (!pages) { |
1270 | WARN(1, "trying to free invalid coherent area: %p\n", cpu_addr); | |
1271 | return; | |
4ce63fcd | 1272 | } |
e9da6e99 | 1273 | |
479ed93a HD |
1274 | if (__in_atomic_pool(cpu_addr, size)) { |
1275 | __iommu_free_atomic(dev, pages, handle, size); | |
1276 | return; | |
1277 | } | |
1278 | ||
955c757e MS |
1279 | if (!dma_get_attr(DMA_ATTR_NO_KERNEL_MAPPING, attrs)) { |
1280 | unmap_kernel_range((unsigned long)cpu_addr, size); | |
1281 | vunmap(cpu_addr); | |
1282 | } | |
e9da6e99 MS |
1283 | |
1284 | __iommu_remove_mapping(dev, handle, size); | |
1285 | __iommu_free_buffer(dev, pages, size); | |
4ce63fcd MS |
1286 | } |
1287 | ||
dc2832e1 MS |
1288 | static int arm_iommu_get_sgtable(struct device *dev, struct sg_table *sgt, |
1289 | void *cpu_addr, dma_addr_t dma_addr, | |
1290 | size_t size, struct dma_attrs *attrs) | |
1291 | { | |
1292 | unsigned int count = PAGE_ALIGN(size) >> PAGE_SHIFT; | |
1293 | struct page **pages = __iommu_get_pages(cpu_addr, attrs); | |
1294 | ||
1295 | if (!pages) | |
1296 | return -ENXIO; | |
1297 | ||
1298 | return sg_alloc_table_from_pages(sgt, pages, count, 0, size, | |
1299 | GFP_KERNEL); | |
4ce63fcd MS |
1300 | } |
1301 | ||
1302 | /* | |
1303 | * Map a part of the scatter-gather list into contiguous io address space | |
1304 | */ | |
1305 | static int __map_sg_chunk(struct device *dev, struct scatterlist *sg, | |
1306 | size_t size, dma_addr_t *handle, | |
97ef952a | 1307 | enum dma_data_direction dir, struct dma_attrs *attrs) |
4ce63fcd MS |
1308 | { |
1309 | struct dma_iommu_mapping *mapping = dev->archdata.mapping; | |
1310 | dma_addr_t iova, iova_base; | |
1311 | int ret = 0; | |
1312 | unsigned int count; | |
1313 | struct scatterlist *s; | |
1314 | ||
1315 | size = PAGE_ALIGN(size); | |
1316 | *handle = DMA_ERROR_CODE; | |
1317 | ||
1318 | iova_base = iova = __alloc_iova(mapping, size); | |
1319 | if (iova == DMA_ERROR_CODE) | |
1320 | return -ENOMEM; | |
1321 | ||
1322 | for (count = 0, s = sg; count < (size >> PAGE_SHIFT); s = sg_next(s)) { | |
1323 | phys_addr_t phys = page_to_phys(sg_page(s)); | |
1324 | unsigned int len = PAGE_ALIGN(s->offset + s->length); | |
1325 | ||
97ef952a MS |
1326 | if (!arch_is_coherent() && |
1327 | !dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs)) | |
4ce63fcd MS |
1328 | __dma_page_cpu_to_dev(sg_page(s), s->offset, s->length, dir); |
1329 | ||
1330 | ret = iommu_map(mapping->domain, iova, phys, len, 0); | |
1331 | if (ret < 0) | |
1332 | goto fail; | |
1333 | count += len >> PAGE_SHIFT; | |
1334 | iova += len; | |
1335 | } | |
1336 | *handle = iova_base; | |
1337 | ||
1338 | return 0; | |
1339 | fail: | |
1340 | iommu_unmap(mapping->domain, iova_base, count * PAGE_SIZE); | |
1341 | __free_iova(mapping, iova_base, size); | |
1342 | return ret; | |
1343 | } | |
1344 | ||
1345 | /** | |
1346 | * arm_iommu_map_sg - map a set of SG buffers for streaming mode DMA | |
1347 | * @dev: valid struct device pointer | |
1348 | * @sg: list of buffers | |
1349 | * @nents: number of buffers to map | |
1350 | * @dir: DMA transfer direction | |
1351 | * | |
1352 | * Map a set of buffers described by scatterlist in streaming mode for DMA. | |
1353 | * The scatter gather list elements are merged together (if possible) and | |
1354 | * tagged with the appropriate dma address and length. They are obtained via | |
1355 | * sg_dma_{address,length}. | |
1356 | */ | |
1357 | int arm_iommu_map_sg(struct device *dev, struct scatterlist *sg, int nents, | |
1358 | enum dma_data_direction dir, struct dma_attrs *attrs) | |
1359 | { | |
1360 | struct scatterlist *s = sg, *dma = sg, *start = sg; | |
1361 | int i, count = 0; | |
1362 | unsigned int offset = s->offset; | |
1363 | unsigned int size = s->offset + s->length; | |
1364 | unsigned int max = dma_get_max_seg_size(dev); | |
1365 | ||
1366 | for (i = 1; i < nents; i++) { | |
1367 | s = sg_next(s); | |
1368 | ||
1369 | s->dma_address = DMA_ERROR_CODE; | |
1370 | s->dma_length = 0; | |
1371 | ||
1372 | if (s->offset || (size & ~PAGE_MASK) || size + s->length > max) { | |
1373 | if (__map_sg_chunk(dev, start, size, &dma->dma_address, | |
97ef952a | 1374 | dir, attrs) < 0) |
4ce63fcd MS |
1375 | goto bad_mapping; |
1376 | ||
1377 | dma->dma_address += offset; | |
1378 | dma->dma_length = size - offset; | |
1379 | ||
1380 | size = offset = s->offset; | |
1381 | start = s; | |
1382 | dma = sg_next(dma); | |
1383 | count += 1; | |
1384 | } | |
1385 | size += s->length; | |
1386 | } | |
97ef952a | 1387 | if (__map_sg_chunk(dev, start, size, &dma->dma_address, dir, attrs) < 0) |
4ce63fcd MS |
1388 | goto bad_mapping; |
1389 | ||
1390 | dma->dma_address += offset; | |
1391 | dma->dma_length = size - offset; | |
1392 | ||
1393 | return count+1; | |
1394 | ||
1395 | bad_mapping: | |
1396 | for_each_sg(sg, s, count, i) | |
1397 | __iommu_remove_mapping(dev, sg_dma_address(s), sg_dma_len(s)); | |
1398 | return 0; | |
1399 | } | |
1400 | ||
1401 | /** | |
1402 | * arm_iommu_unmap_sg - unmap a set of SG buffers mapped by dma_map_sg | |
1403 | * @dev: valid struct device pointer | |
1404 | * @sg: list of buffers | |
1405 | * @nents: number of buffers to unmap (same as was passed to dma_map_sg) | |
1406 | * @dir: DMA transfer direction (same as was passed to dma_map_sg) | |
1407 | * | |
1408 | * Unmap a set of streaming mode DMA translations. Again, CPU access | |
1409 | * rules concerning calls here are the same as for dma_unmap_single(). | |
1410 | */ | |
1411 | void arm_iommu_unmap_sg(struct device *dev, struct scatterlist *sg, int nents, | |
1412 | enum dma_data_direction dir, struct dma_attrs *attrs) | |
1413 | { | |
1414 | struct scatterlist *s; | |
1415 | int i; | |
1416 | ||
1417 | for_each_sg(sg, s, nents, i) { | |
1418 | if (sg_dma_len(s)) | |
1419 | __iommu_remove_mapping(dev, sg_dma_address(s), | |
1420 | sg_dma_len(s)); | |
97ef952a MS |
1421 | if (!arch_is_coherent() && |
1422 | !dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs)) | |
4ce63fcd MS |
1423 | __dma_page_dev_to_cpu(sg_page(s), s->offset, |
1424 | s->length, dir); | |
1425 | } | |
1426 | } | |
1427 | ||
1428 | /** | |
1429 | * arm_iommu_sync_sg_for_cpu | |
1430 | * @dev: valid struct device pointer | |
1431 | * @sg: list of buffers | |
1432 | * @nents: number of buffers to map (returned from dma_map_sg) | |
1433 | * @dir: DMA transfer direction (same as was passed to dma_map_sg) | |
1434 | */ | |
1435 | void arm_iommu_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg, | |
1436 | int nents, enum dma_data_direction dir) | |
1437 | { | |
1438 | struct scatterlist *s; | |
1439 | int i; | |
1440 | ||
1441 | for_each_sg(sg, s, nents, i) | |
1442 | if (!arch_is_coherent()) | |
1443 | __dma_page_dev_to_cpu(sg_page(s), s->offset, s->length, dir); | |
1444 | ||
1445 | } | |
1446 | ||
1447 | /** | |
1448 | * arm_iommu_sync_sg_for_device | |
1449 | * @dev: valid struct device pointer | |
1450 | * @sg: list of buffers | |
1451 | * @nents: number of buffers to map (returned from dma_map_sg) | |
1452 | * @dir: DMA transfer direction (same as was passed to dma_map_sg) | |
1453 | */ | |
1454 | void arm_iommu_sync_sg_for_device(struct device *dev, struct scatterlist *sg, | |
1455 | int nents, enum dma_data_direction dir) | |
1456 | { | |
1457 | struct scatterlist *s; | |
1458 | int i; | |
1459 | ||
1460 | for_each_sg(sg, s, nents, i) | |
1461 | if (!arch_is_coherent()) | |
1462 | __dma_page_cpu_to_dev(sg_page(s), s->offset, s->length, dir); | |
1463 | } | |
1464 | ||
1465 | ||
1466 | /** | |
1467 | * arm_iommu_map_page | |
1468 | * @dev: valid struct device pointer | |
1469 | * @page: page that buffer resides in | |
1470 | * @offset: offset into page for start of buffer | |
1471 | * @size: size of buffer to map | |
1472 | * @dir: DMA transfer direction | |
1473 | * | |
1474 | * IOMMU aware version of arm_dma_map_page() | |
1475 | */ | |
1476 | static dma_addr_t arm_iommu_map_page(struct device *dev, struct page *page, | |
1477 | unsigned long offset, size_t size, enum dma_data_direction dir, | |
1478 | struct dma_attrs *attrs) | |
1479 | { | |
1480 | struct dma_iommu_mapping *mapping = dev->archdata.mapping; | |
1481 | dma_addr_t dma_addr; | |
1482 | int ret, len = PAGE_ALIGN(size + offset); | |
1483 | ||
97ef952a | 1484 | if (!arch_is_coherent() && !dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs)) |
4ce63fcd MS |
1485 | __dma_page_cpu_to_dev(page, offset, size, dir); |
1486 | ||
1487 | dma_addr = __alloc_iova(mapping, len); | |
1488 | if (dma_addr == DMA_ERROR_CODE) | |
1489 | return dma_addr; | |
1490 | ||
1491 | ret = iommu_map(mapping->domain, dma_addr, page_to_phys(page), len, 0); | |
1492 | if (ret < 0) | |
1493 | goto fail; | |
1494 | ||
1495 | return dma_addr + offset; | |
1496 | fail: | |
1497 | __free_iova(mapping, dma_addr, len); | |
1498 | return DMA_ERROR_CODE; | |
1499 | } | |
1500 | ||
1501 | /** | |
1502 | * arm_iommu_unmap_page | |
1503 | * @dev: valid struct device pointer | |
1504 | * @handle: DMA address of buffer | |
1505 | * @size: size of buffer (same as passed to dma_map_page) | |
1506 | * @dir: DMA transfer direction (same as passed to dma_map_page) | |
1507 | * | |
1508 | * IOMMU aware version of arm_dma_unmap_page() | |
1509 | */ | |
1510 | static void arm_iommu_unmap_page(struct device *dev, dma_addr_t handle, | |
1511 | size_t size, enum dma_data_direction dir, | |
1512 | struct dma_attrs *attrs) | |
1513 | { | |
1514 | struct dma_iommu_mapping *mapping = dev->archdata.mapping; | |
1515 | dma_addr_t iova = handle & PAGE_MASK; | |
1516 | struct page *page = phys_to_page(iommu_iova_to_phys(mapping->domain, iova)); | |
1517 | int offset = handle & ~PAGE_MASK; | |
1518 | int len = PAGE_ALIGN(size + offset); | |
1519 | ||
1520 | if (!iova) | |
1521 | return; | |
1522 | ||
97ef952a | 1523 | if (!arch_is_coherent() && !dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs)) |
4ce63fcd MS |
1524 | __dma_page_dev_to_cpu(page, offset, size, dir); |
1525 | ||
1526 | iommu_unmap(mapping->domain, iova, len); | |
1527 | __free_iova(mapping, iova, len); | |
1528 | } | |
1529 | ||
1530 | static void arm_iommu_sync_single_for_cpu(struct device *dev, | |
1531 | dma_addr_t handle, size_t size, enum dma_data_direction dir) | |
1532 | { | |
1533 | struct dma_iommu_mapping *mapping = dev->archdata.mapping; | |
1534 | dma_addr_t iova = handle & PAGE_MASK; | |
1535 | struct page *page = phys_to_page(iommu_iova_to_phys(mapping->domain, iova)); | |
1536 | unsigned int offset = handle & ~PAGE_MASK; | |
1537 | ||
1538 | if (!iova) | |
1539 | return; | |
1540 | ||
1541 | if (!arch_is_coherent()) | |
1542 | __dma_page_dev_to_cpu(page, offset, size, dir); | |
1543 | } | |
1544 | ||
1545 | static void arm_iommu_sync_single_for_device(struct device *dev, | |
1546 | dma_addr_t handle, size_t size, enum dma_data_direction dir) | |
1547 | { | |
1548 | struct dma_iommu_mapping *mapping = dev->archdata.mapping; | |
1549 | dma_addr_t iova = handle & PAGE_MASK; | |
1550 | struct page *page = phys_to_page(iommu_iova_to_phys(mapping->domain, iova)); | |
1551 | unsigned int offset = handle & ~PAGE_MASK; | |
1552 | ||
1553 | if (!iova) | |
1554 | return; | |
1555 | ||
1556 | __dma_page_cpu_to_dev(page, offset, size, dir); | |
1557 | } | |
1558 | ||
1559 | struct dma_map_ops iommu_ops = { | |
1560 | .alloc = arm_iommu_alloc_attrs, | |
1561 | .free = arm_iommu_free_attrs, | |
1562 | .mmap = arm_iommu_mmap_attrs, | |
dc2832e1 | 1563 | .get_sgtable = arm_iommu_get_sgtable, |
4ce63fcd MS |
1564 | |
1565 | .map_page = arm_iommu_map_page, | |
1566 | .unmap_page = arm_iommu_unmap_page, | |
1567 | .sync_single_for_cpu = arm_iommu_sync_single_for_cpu, | |
1568 | .sync_single_for_device = arm_iommu_sync_single_for_device, | |
1569 | ||
1570 | .map_sg = arm_iommu_map_sg, | |
1571 | .unmap_sg = arm_iommu_unmap_sg, | |
1572 | .sync_sg_for_cpu = arm_iommu_sync_sg_for_cpu, | |
1573 | .sync_sg_for_device = arm_iommu_sync_sg_for_device, | |
1574 | }; | |
1575 | ||
1576 | /** | |
1577 | * arm_iommu_create_mapping | |
1578 | * @bus: pointer to the bus holding the client device (for IOMMU calls) | |
1579 | * @base: start address of the valid IO address space | |
1580 | * @size: size of the valid IO address space | |
1581 | * @order: accuracy of the IO addresses allocations | |
1582 | * | |
1583 | * Creates a mapping structure which holds information about used/unused | |
1584 | * IO address ranges, which is required to perform memory allocation and | |
1585 | * mapping with IOMMU aware functions. | |
1586 | * | |
1587 | * The client device need to be attached to the mapping with | |
1588 | * arm_iommu_attach_device function. | |
1589 | */ | |
1590 | struct dma_iommu_mapping * | |
1591 | arm_iommu_create_mapping(struct bus_type *bus, dma_addr_t base, size_t size, | |
1592 | int order) | |
1593 | { | |
1594 | unsigned int count = size >> (PAGE_SHIFT + order); | |
1595 | unsigned int bitmap_size = BITS_TO_LONGS(count) * sizeof(long); | |
1596 | struct dma_iommu_mapping *mapping; | |
1597 | int err = -ENOMEM; | |
1598 | ||
1599 | if (!count) | |
1600 | return ERR_PTR(-EINVAL); | |
1601 | ||
1602 | mapping = kzalloc(sizeof(struct dma_iommu_mapping), GFP_KERNEL); | |
1603 | if (!mapping) | |
1604 | goto err; | |
1605 | ||
1606 | mapping->bitmap = kzalloc(bitmap_size, GFP_KERNEL); | |
1607 | if (!mapping->bitmap) | |
1608 | goto err2; | |
1609 | ||
1610 | mapping->base = base; | |
1611 | mapping->bits = BITS_PER_BYTE * bitmap_size; | |
1612 | mapping->order = order; | |
1613 | spin_lock_init(&mapping->lock); | |
1614 | ||
1615 | mapping->domain = iommu_domain_alloc(bus); | |
1616 | if (!mapping->domain) | |
1617 | goto err3; | |
1618 | ||
1619 | kref_init(&mapping->kref); | |
1620 | return mapping; | |
1621 | err3: | |
1622 | kfree(mapping->bitmap); | |
1623 | err2: | |
1624 | kfree(mapping); | |
1625 | err: | |
1626 | return ERR_PTR(err); | |
1627 | } | |
1628 | ||
1629 | static void release_iommu_mapping(struct kref *kref) | |
1630 | { | |
1631 | struct dma_iommu_mapping *mapping = | |
1632 | container_of(kref, struct dma_iommu_mapping, kref); | |
1633 | ||
1634 | iommu_domain_free(mapping->domain); | |
1635 | kfree(mapping->bitmap); | |
1636 | kfree(mapping); | |
1637 | } | |
1638 | ||
1639 | void arm_iommu_release_mapping(struct dma_iommu_mapping *mapping) | |
1640 | { | |
1641 | if (mapping) | |
1642 | kref_put(&mapping->kref, release_iommu_mapping); | |
1643 | } | |
1644 | ||
1645 | /** | |
1646 | * arm_iommu_attach_device | |
1647 | * @dev: valid struct device pointer | |
1648 | * @mapping: io address space mapping structure (returned from | |
1649 | * arm_iommu_create_mapping) | |
1650 | * | |
1651 | * Attaches specified io address space mapping to the provided device, | |
1652 | * this replaces the dma operations (dma_map_ops pointer) with the | |
1653 | * IOMMU aware version. More than one client might be attached to | |
1654 | * the same io address space mapping. | |
1655 | */ | |
1656 | int arm_iommu_attach_device(struct device *dev, | |
1657 | struct dma_iommu_mapping *mapping) | |
1658 | { | |
1659 | int err; | |
1660 | ||
1661 | err = iommu_attach_device(mapping->domain, dev); | |
1662 | if (err) | |
1663 | return err; | |
1664 | ||
1665 | kref_get(&mapping->kref); | |
1666 | dev->archdata.mapping = mapping; | |
1667 | set_dma_ops(dev, &iommu_ops); | |
1668 | ||
1669 | pr_info("Attached IOMMU controller to %s device.\n", dev_name(dev)); | |
1670 | return 0; | |
1671 | } | |
1672 | ||
1673 | #endif |