[deliverable/linux.git] / arch / arm / mm / l2c-l2x0-resume.S

/*
 * L2C-310 early resume code.  This can be used by platforms to restore
 * the settings of their L2 cache controller before restoring the
 * processor state.
 *
 * This code can only be used to if you are running in the secure world.
 */
#include <linux/linkage.h>
#include <asm/hardware/cache-l2x0.h>

	.text

ENTRY(l2c310_early_resume)
	adr	r0, 1f
	ldr	r2, [r0]
	add	r0, r2, r0

	ldmia	r0, {r1, r2, r3, r4, r5, r6, r7, r8}
	@ r1 = phys address of L2C-310 controller
	@ r2 = aux_ctrl
	@ r3 = tag_latency
	@ r4 = data_latency
	@ r5 = filter_start
	@ r6 = filter_end
	@ r7 = prefetch_ctrl
	@ r8 = pwr_ctrl

	@ Check that the address has been initialised
	teq	r1, #0
	moveq	pc, lr

	@ The prefetch and power control registers are revision dependent
	@ and can be written whether or not the L2 cache is enabled
	ldr	r0, [r1, #L2X0_CACHE_ID]
	and	r0, r0, #L2X0_CACHE_ID_RTL_MASK
	cmp	r0, #L310_CACHE_ID_RTL_R2P0
	strcs	r7, [r1, #L310_PREFETCH_CTRL]
	cmp	r0, #L310_CACHE_ID_RTL_R3P0
	strcs	r8, [r1, #L310_POWER_CTRL]

	@ Don't setup the L2 cache if it is already enabled
	ldr	r0, [r1, #L2X0_CTRL]
	tst	r0, #L2X0_CTRL_EN
	movne	pc, lr

	str	r3, [r1, #L310_TAG_LATENCY_CTRL]
	str	r4, [r1, #L310_DATA_LATENCY_CTRL]
	str	r6, [r1, #L310_ADDR_FILTER_END]
	str	r5, [r1, #L310_ADDR_FILTER_START]

	str	r2, [r1, #L2X0_AUX_CTRL]
	mov	r9, #L2X0_CTRL_EN
	str	r9, [r1, #L2X0_CTRL]
	mov	pc, lr
ENDPROC(l2c310_early_resume)

	.align
1:	.long	l2x0_saved_regs - .
Commit	Line	Data
de7e7532 RK	1	/*
	2	* L2C-310 early resume code. This can be used by platforms to restore
	3	* the settings of their L2 cache controller before restoring the
	4	* processor state.
	5	*
	6	* This code can only be used to if you are running in the secure world.
	7	*/
	8	#include <linux/linkage.h>
	9	#include <asm/hardware/cache-l2x0.h>
	10
	11	.text
	12
	13	ENTRY(l2c310_early_resume)
	14	adr r0, 1f
	15	ldr r2, [r0]
	16	add r0, r2, r0
	17
	18	ldmia r0, {r1, r2, r3, r4, r5, r6, r7, r8}
	19	@ r1 = phys address of L2C-310 controller
	20	@ r2 = aux_ctrl
	21	@ r3 = tag_latency
	22	@ r4 = data_latency
	23	@ r5 = filter_start
	24	@ r6 = filter_end
	25	@ r7 = prefetch_ctrl
	26	@ r8 = pwr_ctrl
	27
	28	@ Check that the address has been initialised
	29	teq r1, #0
	30	moveq pc, lr
	31
	32	@ The prefetch and power control registers are revision dependent
	33	@ and can be written whether or not the L2 cache is enabled
	34	ldr r0, [r1, #L2X0_CACHE_ID]
	35	and r0, r0, #L2X0_CACHE_ID_RTL_MASK
	36	cmp r0, #L310_CACHE_ID_RTL_R2P0
	37	strcs r7, [r1, #L310_PREFETCH_CTRL]
	38	cmp r0, #L310_CACHE_ID_RTL_R3P0
	39	strcs r8, [r1, #L310_POWER_CTRL]
	40
	41	@ Don't setup the L2 cache if it is already enabled
	42	ldr r0, [r1, #L2X0_CTRL]
	43	tst r0, #L2X0_CTRL_EN
	44	movne pc, lr
	45
	46	str r3, [r1, #L310_TAG_LATENCY_CTRL]
	47	str r4, [r1, #L310_DATA_LATENCY_CTRL]
	48	str r6, [r1, #L310_ADDR_FILTER_END]
	49	str r5, [r1, #L310_ADDR_FILTER_START]
	50
	51	str r2, [r1, #L2X0_AUX_CTRL]
	52	mov r9, #L2X0_CTRL_EN
	53	str r9, [r1, #L2X0_CTRL]
	54	mov pc, lr
	55	ENDPROC(l2c310_early_resume)
	56
	57	.align
	58	1: .long l2x0_saved_regs - .