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d111e8f9 RK |
1 | /* |
2 | * linux/arch/arm/mm/mmu.c | |
3 | * | |
4 | * Copyright (C) 1995-2005 Russell King | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | */ | |
ae8f1541 | 10 | #include <linux/module.h> |
d111e8f9 RK |
11 | #include <linux/kernel.h> |
12 | #include <linux/errno.h> | |
13 | #include <linux/init.h> | |
d111e8f9 RK |
14 | #include <linux/mman.h> |
15 | #include <linux/nodemask.h> | |
2778f620 | 16 | #include <linux/memblock.h> |
d907387c | 17 | #include <linux/fs.h> |
0536bdf3 | 18 | #include <linux/vmalloc.h> |
d111e8f9 | 19 | |
15d07dc9 | 20 | #include <asm/cp15.h> |
0ba8b9b2 | 21 | #include <asm/cputype.h> |
37efe642 | 22 | #include <asm/sections.h> |
3f973e22 | 23 | #include <asm/cachetype.h> |
d111e8f9 RK |
24 | #include <asm/setup.h> |
25 | #include <asm/sizes.h> | |
e616c591 | 26 | #include <asm/smp_plat.h> |
d111e8f9 | 27 | #include <asm/tlb.h> |
d73cd428 | 28 | #include <asm/highmem.h> |
9f97da78 | 29 | #include <asm/system_info.h> |
247055aa | 30 | #include <asm/traps.h> |
d111e8f9 RK |
31 | |
32 | #include <asm/mach/arch.h> | |
33 | #include <asm/mach/map.h> | |
c2794437 | 34 | #include <asm/mach/pci.h> |
d111e8f9 RK |
35 | |
36 | #include "mm.h" | |
37 | ||
d111e8f9 RK |
38 | /* |
39 | * empty_zero_page is a special page that is used for | |
40 | * zero-initialized data and COW. | |
41 | */ | |
42 | struct page *empty_zero_page; | |
3653f3ab | 43 | EXPORT_SYMBOL(empty_zero_page); |
d111e8f9 RK |
44 | |
45 | /* | |
46 | * The pmd table for the upper-most set of pages. | |
47 | */ | |
48 | pmd_t *top_pmd; | |
49 | ||
ae8f1541 RK |
50 | #define CPOLICY_UNCACHED 0 |
51 | #define CPOLICY_BUFFERED 1 | |
52 | #define CPOLICY_WRITETHROUGH 2 | |
53 | #define CPOLICY_WRITEBACK 3 | |
54 | #define CPOLICY_WRITEALLOC 4 | |
55 | ||
56 | static unsigned int cachepolicy __initdata = CPOLICY_WRITEBACK; | |
57 | static unsigned int ecc_mask __initdata = 0; | |
44b18693 | 58 | pgprot_t pgprot_user; |
ae8f1541 RK |
59 | pgprot_t pgprot_kernel; |
60 | ||
44b18693 | 61 | EXPORT_SYMBOL(pgprot_user); |
ae8f1541 RK |
62 | EXPORT_SYMBOL(pgprot_kernel); |
63 | ||
64 | struct cachepolicy { | |
65 | const char policy[16]; | |
66 | unsigned int cr_mask; | |
442e70c0 | 67 | pmdval_t pmd; |
f6e3354d | 68 | pteval_t pte; |
ae8f1541 RK |
69 | }; |
70 | ||
71 | static struct cachepolicy cache_policies[] __initdata = { | |
72 | { | |
73 | .policy = "uncached", | |
74 | .cr_mask = CR_W|CR_C, | |
75 | .pmd = PMD_SECT_UNCACHED, | |
bb30f36f | 76 | .pte = L_PTE_MT_UNCACHED, |
ae8f1541 RK |
77 | }, { |
78 | .policy = "buffered", | |
79 | .cr_mask = CR_C, | |
80 | .pmd = PMD_SECT_BUFFERED, | |
bb30f36f | 81 | .pte = L_PTE_MT_BUFFERABLE, |
ae8f1541 RK |
82 | }, { |
83 | .policy = "writethrough", | |
84 | .cr_mask = 0, | |
85 | .pmd = PMD_SECT_WT, | |
bb30f36f | 86 | .pte = L_PTE_MT_WRITETHROUGH, |
ae8f1541 RK |
87 | }, { |
88 | .policy = "writeback", | |
89 | .cr_mask = 0, | |
90 | .pmd = PMD_SECT_WB, | |
bb30f36f | 91 | .pte = L_PTE_MT_WRITEBACK, |
ae8f1541 RK |
92 | }, { |
93 | .policy = "writealloc", | |
94 | .cr_mask = 0, | |
95 | .pmd = PMD_SECT_WBWA, | |
bb30f36f | 96 | .pte = L_PTE_MT_WRITEALLOC, |
ae8f1541 RK |
97 | } |
98 | }; | |
99 | ||
100 | /* | |
6cbdc8c5 | 101 | * These are useful for identifying cache coherency |
ae8f1541 RK |
102 | * problems by allowing the cache or the cache and |
103 | * writebuffer to be turned off. (Note: the write | |
104 | * buffer should not be on and the cache off). | |
105 | */ | |
2b0d8c25 | 106 | static int __init early_cachepolicy(char *p) |
ae8f1541 RK |
107 | { |
108 | int i; | |
109 | ||
110 | for (i = 0; i < ARRAY_SIZE(cache_policies); i++) { | |
111 | int len = strlen(cache_policies[i].policy); | |
112 | ||
2b0d8c25 | 113 | if (memcmp(p, cache_policies[i].policy, len) == 0) { |
ae8f1541 RK |
114 | cachepolicy = i; |
115 | cr_alignment &= ~cache_policies[i].cr_mask; | |
116 | cr_no_alignment &= ~cache_policies[i].cr_mask; | |
ae8f1541 RK |
117 | break; |
118 | } | |
119 | } | |
120 | if (i == ARRAY_SIZE(cache_policies)) | |
121 | printk(KERN_ERR "ERROR: unknown or unsupported cache policy\n"); | |
4b46d641 RK |
122 | /* |
123 | * This restriction is partly to do with the way we boot; it is | |
124 | * unpredictable to have memory mapped using two different sets of | |
125 | * memory attributes (shared, type, and cache attribs). We can not | |
126 | * change these attributes once the initial assembly has setup the | |
127 | * page tables. | |
128 | */ | |
11179d8c CM |
129 | if (cpu_architecture() >= CPU_ARCH_ARMv6) { |
130 | printk(KERN_WARNING "Only cachepolicy=writeback supported on ARMv6 and later\n"); | |
131 | cachepolicy = CPOLICY_WRITEBACK; | |
132 | } | |
ae8f1541 RK |
133 | flush_cache_all(); |
134 | set_cr(cr_alignment); | |
2b0d8c25 | 135 | return 0; |
ae8f1541 | 136 | } |
2b0d8c25 | 137 | early_param("cachepolicy", early_cachepolicy); |
ae8f1541 | 138 | |
2b0d8c25 | 139 | static int __init early_nocache(char *__unused) |
ae8f1541 RK |
140 | { |
141 | char *p = "buffered"; | |
142 | printk(KERN_WARNING "nocache is deprecated; use cachepolicy=%s\n", p); | |
2b0d8c25 JK |
143 | early_cachepolicy(p); |
144 | return 0; | |
ae8f1541 | 145 | } |
2b0d8c25 | 146 | early_param("nocache", early_nocache); |
ae8f1541 | 147 | |
2b0d8c25 | 148 | static int __init early_nowrite(char *__unused) |
ae8f1541 RK |
149 | { |
150 | char *p = "uncached"; | |
151 | printk(KERN_WARNING "nowb is deprecated; use cachepolicy=%s\n", p); | |
2b0d8c25 JK |
152 | early_cachepolicy(p); |
153 | return 0; | |
ae8f1541 | 154 | } |
2b0d8c25 | 155 | early_param("nowb", early_nowrite); |
ae8f1541 | 156 | |
1b6ba46b | 157 | #ifndef CONFIG_ARM_LPAE |
2b0d8c25 | 158 | static int __init early_ecc(char *p) |
ae8f1541 | 159 | { |
2b0d8c25 | 160 | if (memcmp(p, "on", 2) == 0) |
ae8f1541 | 161 | ecc_mask = PMD_PROTECTION; |
2b0d8c25 | 162 | else if (memcmp(p, "off", 3) == 0) |
ae8f1541 | 163 | ecc_mask = 0; |
2b0d8c25 | 164 | return 0; |
ae8f1541 | 165 | } |
2b0d8c25 | 166 | early_param("ecc", early_ecc); |
1b6ba46b | 167 | #endif |
ae8f1541 RK |
168 | |
169 | static int __init noalign_setup(char *__unused) | |
170 | { | |
171 | cr_alignment &= ~CR_A; | |
172 | cr_no_alignment &= ~CR_A; | |
173 | set_cr(cr_alignment); | |
174 | return 1; | |
175 | } | |
176 | __setup("noalign", noalign_setup); | |
177 | ||
255d1f86 RK |
178 | #ifndef CONFIG_SMP |
179 | void adjust_cr(unsigned long mask, unsigned long set) | |
180 | { | |
181 | unsigned long flags; | |
182 | ||
183 | mask &= ~CR_A; | |
184 | ||
185 | set &= mask; | |
186 | ||
187 | local_irq_save(flags); | |
188 | ||
189 | cr_no_alignment = (cr_no_alignment & ~mask) | set; | |
190 | cr_alignment = (cr_alignment & ~mask) | set; | |
191 | ||
192 | set_cr((get_cr() & ~mask) | set); | |
193 | ||
194 | local_irq_restore(flags); | |
195 | } | |
196 | #endif | |
197 | ||
36bb94ba | 198 | #define PROT_PTE_DEVICE L_PTE_PRESENT|L_PTE_YOUNG|L_PTE_DIRTY|L_PTE_XN |
b1cce6b1 | 199 | #define PROT_SECT_DEVICE PMD_TYPE_SECT|PMD_SECT_AP_WRITE |
0af92bef | 200 | |
b29e9f5e | 201 | static struct mem_type mem_types[] = { |
0af92bef | 202 | [MT_DEVICE] = { /* Strongly ordered / ARMv6 shared device */ |
bb30f36f RK |
203 | .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_SHARED | |
204 | L_PTE_SHARED, | |
0af92bef | 205 | .prot_l1 = PMD_TYPE_TABLE, |
b1cce6b1 | 206 | .prot_sect = PROT_SECT_DEVICE | PMD_SECT_S, |
0af92bef RK |
207 | .domain = DOMAIN_IO, |
208 | }, | |
209 | [MT_DEVICE_NONSHARED] = { /* ARMv6 non-shared device */ | |
bb30f36f | 210 | .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_NONSHARED, |
0af92bef | 211 | .prot_l1 = PMD_TYPE_TABLE, |
b1cce6b1 | 212 | .prot_sect = PROT_SECT_DEVICE, |
0af92bef RK |
213 | .domain = DOMAIN_IO, |
214 | }, | |
215 | [MT_DEVICE_CACHED] = { /* ioremap_cached */ | |
bb30f36f | 216 | .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_CACHED, |
0af92bef RK |
217 | .prot_l1 = PMD_TYPE_TABLE, |
218 | .prot_sect = PROT_SECT_DEVICE | PMD_SECT_WB, | |
219 | .domain = DOMAIN_IO, | |
c2794437 | 220 | }, |
1ad77a87 | 221 | [MT_DEVICE_WC] = { /* ioremap_wc */ |
bb30f36f | 222 | .prot_pte = PROT_PTE_DEVICE | L_PTE_MT_DEV_WC, |
0af92bef | 223 | .prot_l1 = PMD_TYPE_TABLE, |
b1cce6b1 | 224 | .prot_sect = PROT_SECT_DEVICE, |
0af92bef | 225 | .domain = DOMAIN_IO, |
ae8f1541 | 226 | }, |
ebb4c658 RK |
227 | [MT_UNCACHED] = { |
228 | .prot_pte = PROT_PTE_DEVICE, | |
229 | .prot_l1 = PMD_TYPE_TABLE, | |
230 | .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN, | |
231 | .domain = DOMAIN_IO, | |
232 | }, | |
ae8f1541 | 233 | [MT_CACHECLEAN] = { |
9ef79635 | 234 | .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN, |
ae8f1541 RK |
235 | .domain = DOMAIN_KERNEL, |
236 | }, | |
1b6ba46b | 237 | #ifndef CONFIG_ARM_LPAE |
ae8f1541 | 238 | [MT_MINICLEAN] = { |
9ef79635 | 239 | .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN | PMD_SECT_MINICACHE, |
ae8f1541 RK |
240 | .domain = DOMAIN_KERNEL, |
241 | }, | |
1b6ba46b | 242 | #endif |
ae8f1541 RK |
243 | [MT_LOW_VECTORS] = { |
244 | .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY | | |
36bb94ba | 245 | L_PTE_RDONLY, |
ae8f1541 RK |
246 | .prot_l1 = PMD_TYPE_TABLE, |
247 | .domain = DOMAIN_USER, | |
248 | }, | |
249 | [MT_HIGH_VECTORS] = { | |
250 | .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY | | |
36bb94ba | 251 | L_PTE_USER | L_PTE_RDONLY, |
ae8f1541 RK |
252 | .prot_l1 = PMD_TYPE_TABLE, |
253 | .domain = DOMAIN_USER, | |
254 | }, | |
255 | [MT_MEMORY] = { | |
36bb94ba | 256 | .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY, |
f1a2481c | 257 | .prot_l1 = PMD_TYPE_TABLE, |
9ef79635 | 258 | .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE, |
ae8f1541 RK |
259 | .domain = DOMAIN_KERNEL, |
260 | }, | |
261 | [MT_ROM] = { | |
9ef79635 | 262 | .prot_sect = PMD_TYPE_SECT, |
ae8f1541 RK |
263 | .domain = DOMAIN_KERNEL, |
264 | }, | |
e4707dd3 | 265 | [MT_MEMORY_NONCACHED] = { |
f1a2481c | 266 | .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY | |
36bb94ba | 267 | L_PTE_MT_BUFFERABLE, |
f1a2481c | 268 | .prot_l1 = PMD_TYPE_TABLE, |
e4707dd3 PW |
269 | .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE, |
270 | .domain = DOMAIN_KERNEL, | |
271 | }, | |
cb9d7707 | 272 | [MT_MEMORY_DTCM] = { |
f444fce3 | 273 | .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY | |
36bb94ba | 274 | L_PTE_XN, |
f444fce3 LW |
275 | .prot_l1 = PMD_TYPE_TABLE, |
276 | .prot_sect = PMD_TYPE_SECT | PMD_SECT_XN, | |
277 | .domain = DOMAIN_KERNEL, | |
cb9d7707 LW |
278 | }, |
279 | [MT_MEMORY_ITCM] = { | |
36bb94ba | 280 | .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY, |
cb9d7707 | 281 | .prot_l1 = PMD_TYPE_TABLE, |
f444fce3 | 282 | .domain = DOMAIN_KERNEL, |
cb9d7707 | 283 | }, |
8fb54284 SS |
284 | [MT_MEMORY_SO] = { |
285 | .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY | | |
286 | L_PTE_MT_UNCACHED, | |
287 | .prot_l1 = PMD_TYPE_TABLE, | |
288 | .prot_sect = PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_SECT_S | | |
289 | PMD_SECT_UNCACHED | PMD_SECT_XN, | |
290 | .domain = DOMAIN_KERNEL, | |
291 | }, | |
c7909509 MS |
292 | [MT_MEMORY_DMA_READY] = { |
293 | .prot_pte = L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_DIRTY, | |
294 | .prot_l1 = PMD_TYPE_TABLE, | |
295 | .domain = DOMAIN_KERNEL, | |
296 | }, | |
ae8f1541 RK |
297 | }; |
298 | ||
b29e9f5e RK |
299 | const struct mem_type *get_mem_type(unsigned int type) |
300 | { | |
301 | return type < ARRAY_SIZE(mem_types) ? &mem_types[type] : NULL; | |
302 | } | |
69d3a84a | 303 | EXPORT_SYMBOL(get_mem_type); |
b29e9f5e | 304 | |
ae8f1541 RK |
305 | /* |
306 | * Adjust the PMD section entries according to the CPU in use. | |
307 | */ | |
308 | static void __init build_mem_type_table(void) | |
309 | { | |
310 | struct cachepolicy *cp; | |
311 | unsigned int cr = get_cr(); | |
442e70c0 | 312 | pteval_t user_pgprot, kern_pgprot, vecs_pgprot; |
ae8f1541 RK |
313 | int cpu_arch = cpu_architecture(); |
314 | int i; | |
315 | ||
11179d8c | 316 | if (cpu_arch < CPU_ARCH_ARMv6) { |
ae8f1541 | 317 | #if defined(CONFIG_CPU_DCACHE_DISABLE) |
11179d8c CM |
318 | if (cachepolicy > CPOLICY_BUFFERED) |
319 | cachepolicy = CPOLICY_BUFFERED; | |
ae8f1541 | 320 | #elif defined(CONFIG_CPU_DCACHE_WRITETHROUGH) |
11179d8c CM |
321 | if (cachepolicy > CPOLICY_WRITETHROUGH) |
322 | cachepolicy = CPOLICY_WRITETHROUGH; | |
ae8f1541 | 323 | #endif |
11179d8c | 324 | } |
ae8f1541 RK |
325 | if (cpu_arch < CPU_ARCH_ARMv5) { |
326 | if (cachepolicy >= CPOLICY_WRITEALLOC) | |
327 | cachepolicy = CPOLICY_WRITEBACK; | |
328 | ecc_mask = 0; | |
329 | } | |
f00ec48f RK |
330 | if (is_smp()) |
331 | cachepolicy = CPOLICY_WRITEALLOC; | |
ae8f1541 | 332 | |
1ad77a87 | 333 | /* |
b1cce6b1 RK |
334 | * Strip out features not present on earlier architectures. |
335 | * Pre-ARMv5 CPUs don't have TEX bits. Pre-ARMv6 CPUs or those | |
336 | * without extended page tables don't have the 'Shared' bit. | |
1ad77a87 | 337 | */ |
b1cce6b1 RK |
338 | if (cpu_arch < CPU_ARCH_ARMv5) |
339 | for (i = 0; i < ARRAY_SIZE(mem_types); i++) | |
340 | mem_types[i].prot_sect &= ~PMD_SECT_TEX(7); | |
341 | if ((cpu_arch < CPU_ARCH_ARMv6 || !(cr & CR_XP)) && !cpu_is_xsc3()) | |
342 | for (i = 0; i < ARRAY_SIZE(mem_types); i++) | |
343 | mem_types[i].prot_sect &= ~PMD_SECT_S; | |
ae8f1541 RK |
344 | |
345 | /* | |
b1cce6b1 RK |
346 | * ARMv5 and lower, bit 4 must be set for page tables (was: cache |
347 | * "update-able on write" bit on ARM610). However, Xscale and | |
348 | * Xscale3 require this bit to be cleared. | |
ae8f1541 | 349 | */ |
b1cce6b1 | 350 | if (cpu_is_xscale() || cpu_is_xsc3()) { |
9ef79635 | 351 | for (i = 0; i < ARRAY_SIZE(mem_types); i++) { |
ae8f1541 | 352 | mem_types[i].prot_sect &= ~PMD_BIT4; |
9ef79635 RK |
353 | mem_types[i].prot_l1 &= ~PMD_BIT4; |
354 | } | |
355 | } else if (cpu_arch < CPU_ARCH_ARMv6) { | |
356 | for (i = 0; i < ARRAY_SIZE(mem_types); i++) { | |
ae8f1541 RK |
357 | if (mem_types[i].prot_l1) |
358 | mem_types[i].prot_l1 |= PMD_BIT4; | |
9ef79635 RK |
359 | if (mem_types[i].prot_sect) |
360 | mem_types[i].prot_sect |= PMD_BIT4; | |
361 | } | |
362 | } | |
ae8f1541 | 363 | |
b1cce6b1 RK |
364 | /* |
365 | * Mark the device areas according to the CPU/architecture. | |
366 | */ | |
367 | if (cpu_is_xsc3() || (cpu_arch >= CPU_ARCH_ARMv6 && (cr & CR_XP))) { | |
368 | if (!cpu_is_xsc3()) { | |
369 | /* | |
370 | * Mark device regions on ARMv6+ as execute-never | |
371 | * to prevent speculative instruction fetches. | |
372 | */ | |
373 | mem_types[MT_DEVICE].prot_sect |= PMD_SECT_XN; | |
374 | mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_XN; | |
375 | mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_XN; | |
376 | mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_XN; | |
377 | } | |
378 | if (cpu_arch >= CPU_ARCH_ARMv7 && (cr & CR_TRE)) { | |
379 | /* | |
380 | * For ARMv7 with TEX remapping, | |
381 | * - shared device is SXCB=1100 | |
382 | * - nonshared device is SXCB=0100 | |
383 | * - write combine device mem is SXCB=0001 | |
384 | * (Uncached Normal memory) | |
385 | */ | |
386 | mem_types[MT_DEVICE].prot_sect |= PMD_SECT_TEX(1); | |
387 | mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(1); | |
388 | mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_BUFFERABLE; | |
389 | } else if (cpu_is_xsc3()) { | |
390 | /* | |
391 | * For Xscale3, | |
392 | * - shared device is TEXCB=00101 | |
393 | * - nonshared device is TEXCB=01000 | |
394 | * - write combine device mem is TEXCB=00100 | |
395 | * (Inner/Outer Uncacheable in xsc3 parlance) | |
396 | */ | |
397 | mem_types[MT_DEVICE].prot_sect |= PMD_SECT_TEX(1) | PMD_SECT_BUFFERED; | |
398 | mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(2); | |
399 | mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_TEX(1); | |
400 | } else { | |
401 | /* | |
402 | * For ARMv6 and ARMv7 without TEX remapping, | |
403 | * - shared device is TEXCB=00001 | |
404 | * - nonshared device is TEXCB=01000 | |
405 | * - write combine device mem is TEXCB=00100 | |
406 | * (Uncached Normal in ARMv6 parlance). | |
407 | */ | |
408 | mem_types[MT_DEVICE].prot_sect |= PMD_SECT_BUFFERED; | |
409 | mem_types[MT_DEVICE_NONSHARED].prot_sect |= PMD_SECT_TEX(2); | |
410 | mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_TEX(1); | |
411 | } | |
412 | } else { | |
413 | /* | |
414 | * On others, write combining is "Uncached/Buffered" | |
415 | */ | |
416 | mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_BUFFERABLE; | |
417 | } | |
418 | ||
419 | /* | |
420 | * Now deal with the memory-type mappings | |
421 | */ | |
ae8f1541 | 422 | cp = &cache_policies[cachepolicy]; |
bb30f36f RK |
423 | vecs_pgprot = kern_pgprot = user_pgprot = cp->pte; |
424 | ||
bb30f36f RK |
425 | /* |
426 | * Only use write-through for non-SMP systems | |
427 | */ | |
f00ec48f | 428 | if (!is_smp() && cpu_arch >= CPU_ARCH_ARMv5 && cachepolicy > CPOLICY_WRITETHROUGH) |
bb30f36f | 429 | vecs_pgprot = cache_policies[CPOLICY_WRITETHROUGH].pte; |
ae8f1541 RK |
430 | |
431 | /* | |
432 | * Enable CPU-specific coherency if supported. | |
433 | * (Only available on XSC3 at the moment.) | |
434 | */ | |
f1a2481c | 435 | if (arch_is_coherent() && cpu_is_xsc3()) { |
b1cce6b1 | 436 | mem_types[MT_MEMORY].prot_sect |= PMD_SECT_S; |
f1a2481c | 437 | mem_types[MT_MEMORY].prot_pte |= L_PTE_SHARED; |
c7909509 | 438 | mem_types[MT_MEMORY_DMA_READY].prot_pte |= L_PTE_SHARED; |
f1a2481c SS |
439 | mem_types[MT_MEMORY_NONCACHED].prot_sect |= PMD_SECT_S; |
440 | mem_types[MT_MEMORY_NONCACHED].prot_pte |= L_PTE_SHARED; | |
441 | } | |
ae8f1541 RK |
442 | /* |
443 | * ARMv6 and above have extended page tables. | |
444 | */ | |
445 | if (cpu_arch >= CPU_ARCH_ARMv6 && (cr & CR_XP)) { | |
1b6ba46b | 446 | #ifndef CONFIG_ARM_LPAE |
ae8f1541 RK |
447 | /* |
448 | * Mark cache clean areas and XIP ROM read only | |
449 | * from SVC mode and no access from userspace. | |
450 | */ | |
451 | mem_types[MT_ROM].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE; | |
452 | mem_types[MT_MINICLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE; | |
453 | mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_APX|PMD_SECT_AP_WRITE; | |
1b6ba46b | 454 | #endif |
ae8f1541 | 455 | |
f00ec48f RK |
456 | if (is_smp()) { |
457 | /* | |
458 | * Mark memory with the "shared" attribute | |
459 | * for SMP systems | |
460 | */ | |
461 | user_pgprot |= L_PTE_SHARED; | |
462 | kern_pgprot |= L_PTE_SHARED; | |
463 | vecs_pgprot |= L_PTE_SHARED; | |
464 | mem_types[MT_DEVICE_WC].prot_sect |= PMD_SECT_S; | |
465 | mem_types[MT_DEVICE_WC].prot_pte |= L_PTE_SHARED; | |
466 | mem_types[MT_DEVICE_CACHED].prot_sect |= PMD_SECT_S; | |
467 | mem_types[MT_DEVICE_CACHED].prot_pte |= L_PTE_SHARED; | |
468 | mem_types[MT_MEMORY].prot_sect |= PMD_SECT_S; | |
469 | mem_types[MT_MEMORY].prot_pte |= L_PTE_SHARED; | |
c7909509 | 470 | mem_types[MT_MEMORY_DMA_READY].prot_pte |= L_PTE_SHARED; |
f00ec48f RK |
471 | mem_types[MT_MEMORY_NONCACHED].prot_sect |= PMD_SECT_S; |
472 | mem_types[MT_MEMORY_NONCACHED].prot_pte |= L_PTE_SHARED; | |
473 | } | |
ae8f1541 RK |
474 | } |
475 | ||
e4707dd3 PW |
476 | /* |
477 | * Non-cacheable Normal - intended for memory areas that must | |
478 | * not cause dirty cache line writebacks when used | |
479 | */ | |
480 | if (cpu_arch >= CPU_ARCH_ARMv6) { | |
481 | if (cpu_arch >= CPU_ARCH_ARMv7 && (cr & CR_TRE)) { | |
482 | /* Non-cacheable Normal is XCB = 001 */ | |
483 | mem_types[MT_MEMORY_NONCACHED].prot_sect |= | |
484 | PMD_SECT_BUFFERED; | |
485 | } else { | |
486 | /* For both ARMv6 and non-TEX-remapping ARMv7 */ | |
487 | mem_types[MT_MEMORY_NONCACHED].prot_sect |= | |
488 | PMD_SECT_TEX(1); | |
489 | } | |
490 | } else { | |
491 | mem_types[MT_MEMORY_NONCACHED].prot_sect |= PMD_SECT_BUFFERABLE; | |
492 | } | |
493 | ||
1b6ba46b CM |
494 | #ifdef CONFIG_ARM_LPAE |
495 | /* | |
496 | * Do not generate access flag faults for the kernel mappings. | |
497 | */ | |
498 | for (i = 0; i < ARRAY_SIZE(mem_types); i++) { | |
499 | mem_types[i].prot_pte |= PTE_EXT_AF; | |
1a3abcf4 VA |
500 | if (mem_types[i].prot_sect) |
501 | mem_types[i].prot_sect |= PMD_SECT_AF; | |
1b6ba46b CM |
502 | } |
503 | kern_pgprot |= PTE_EXT_AF; | |
504 | vecs_pgprot |= PTE_EXT_AF; | |
505 | #endif | |
506 | ||
ae8f1541 RK |
507 | for (i = 0; i < 16; i++) { |
508 | unsigned long v = pgprot_val(protection_map[i]); | |
bb30f36f | 509 | protection_map[i] = __pgprot(v | user_pgprot); |
ae8f1541 RK |
510 | } |
511 | ||
bb30f36f RK |
512 | mem_types[MT_LOW_VECTORS].prot_pte |= vecs_pgprot; |
513 | mem_types[MT_HIGH_VECTORS].prot_pte |= vecs_pgprot; | |
ae8f1541 | 514 | |
44b18693 | 515 | pgprot_user = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | user_pgprot); |
ae8f1541 | 516 | pgprot_kernel = __pgprot(L_PTE_PRESENT | L_PTE_YOUNG | |
36bb94ba | 517 | L_PTE_DIRTY | kern_pgprot); |
ae8f1541 RK |
518 | |
519 | mem_types[MT_LOW_VECTORS].prot_l1 |= ecc_mask; | |
520 | mem_types[MT_HIGH_VECTORS].prot_l1 |= ecc_mask; | |
521 | mem_types[MT_MEMORY].prot_sect |= ecc_mask | cp->pmd; | |
f1a2481c | 522 | mem_types[MT_MEMORY].prot_pte |= kern_pgprot; |
c7909509 | 523 | mem_types[MT_MEMORY_DMA_READY].prot_pte |= kern_pgprot; |
f1a2481c | 524 | mem_types[MT_MEMORY_NONCACHED].prot_sect |= ecc_mask; |
ae8f1541 RK |
525 | mem_types[MT_ROM].prot_sect |= cp->pmd; |
526 | ||
527 | switch (cp->pmd) { | |
528 | case PMD_SECT_WT: | |
529 | mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WT; | |
530 | break; | |
531 | case PMD_SECT_WB: | |
532 | case PMD_SECT_WBWA: | |
533 | mem_types[MT_CACHECLEAN].prot_sect |= PMD_SECT_WB; | |
534 | break; | |
535 | } | |
536 | printk("Memory policy: ECC %sabled, Data cache %s\n", | |
537 | ecc_mask ? "en" : "dis", cp->policy); | |
2497f0a8 RK |
538 | |
539 | for (i = 0; i < ARRAY_SIZE(mem_types); i++) { | |
540 | struct mem_type *t = &mem_types[i]; | |
541 | if (t->prot_l1) | |
542 | t->prot_l1 |= PMD_DOMAIN(t->domain); | |
543 | if (t->prot_sect) | |
544 | t->prot_sect |= PMD_DOMAIN(t->domain); | |
545 | } | |
ae8f1541 RK |
546 | } |
547 | ||
d907387c CM |
548 | #ifdef CONFIG_ARM_DMA_MEM_BUFFERABLE |
549 | pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn, | |
550 | unsigned long size, pgprot_t vma_prot) | |
551 | { | |
552 | if (!pfn_valid(pfn)) | |
553 | return pgprot_noncached(vma_prot); | |
554 | else if (file->f_flags & O_SYNC) | |
555 | return pgprot_writecombine(vma_prot); | |
556 | return vma_prot; | |
557 | } | |
558 | EXPORT_SYMBOL(phys_mem_access_prot); | |
559 | #endif | |
560 | ||
ae8f1541 RK |
561 | #define vectors_base() (vectors_high() ? 0xffff0000 : 0) |
562 | ||
0536bdf3 | 563 | static void __init *early_alloc_aligned(unsigned long sz, unsigned long align) |
3abe9d33 | 564 | { |
0536bdf3 | 565 | void *ptr = __va(memblock_alloc(sz, align)); |
2778f620 RK |
566 | memset(ptr, 0, sz); |
567 | return ptr; | |
3abe9d33 RK |
568 | } |
569 | ||
0536bdf3 NP |
570 | static void __init *early_alloc(unsigned long sz) |
571 | { | |
572 | return early_alloc_aligned(sz, sz); | |
573 | } | |
574 | ||
4bb2e27d | 575 | static pte_t * __init early_pte_alloc(pmd_t *pmd, unsigned long addr, unsigned long prot) |
ae8f1541 | 576 | { |
24e6c699 | 577 | if (pmd_none(*pmd)) { |
410f1483 | 578 | pte_t *pte = early_alloc(PTE_HWTABLE_OFF + PTE_HWTABLE_SIZE); |
97092e0c | 579 | __pmd_populate(pmd, __pa(pte), prot); |
24e6c699 | 580 | } |
4bb2e27d RK |
581 | BUG_ON(pmd_bad(*pmd)); |
582 | return pte_offset_kernel(pmd, addr); | |
583 | } | |
ae8f1541 | 584 | |
4bb2e27d RK |
585 | static void __init alloc_init_pte(pmd_t *pmd, unsigned long addr, |
586 | unsigned long end, unsigned long pfn, | |
587 | const struct mem_type *type) | |
588 | { | |
589 | pte_t *pte = early_pte_alloc(pmd, addr, type->prot_l1); | |
24e6c699 | 590 | do { |
40d192b6 | 591 | set_pte_ext(pte, pfn_pte(pfn, __pgprot(type->prot_pte)), 0); |
24e6c699 RK |
592 | pfn++; |
593 | } while (pte++, addr += PAGE_SIZE, addr != end); | |
ae8f1541 RK |
594 | } |
595 | ||
516295e5 | 596 | static void __init alloc_init_section(pud_t *pud, unsigned long addr, |
97092e0c | 597 | unsigned long end, phys_addr_t phys, |
24e6c699 | 598 | const struct mem_type *type) |
ae8f1541 | 599 | { |
516295e5 | 600 | pmd_t *pmd = pmd_offset(pud, addr); |
ae8f1541 | 601 | |
24e6c699 RK |
602 | /* |
603 | * Try a section mapping - end, addr and phys must all be aligned | |
604 | * to a section boundary. Note that PMDs refer to the individual | |
605 | * L1 entries, whereas PGDs refer to a group of L1 entries making | |
606 | * up one logical pointer to an L2 table. | |
607 | */ | |
c7909509 | 608 | if (type->prot_sect && ((addr | end | phys) & ~SECTION_MASK) == 0) { |
24e6c699 | 609 | pmd_t *p = pmd; |
ae8f1541 | 610 | |
1b6ba46b | 611 | #ifndef CONFIG_ARM_LPAE |
24e6c699 RK |
612 | if (addr & SECTION_SIZE) |
613 | pmd++; | |
1b6ba46b | 614 | #endif |
24e6c699 RK |
615 | |
616 | do { | |
617 | *pmd = __pmd(phys | type->prot_sect); | |
618 | phys += SECTION_SIZE; | |
619 | } while (pmd++, addr += SECTION_SIZE, addr != end); | |
ae8f1541 | 620 | |
24e6c699 RK |
621 | flush_pmd_entry(p); |
622 | } else { | |
623 | /* | |
624 | * No need to loop; pte's aren't interested in the | |
625 | * individual L1 entries. | |
626 | */ | |
627 | alloc_init_pte(pmd, addr, end, __phys_to_pfn(phys), type); | |
628 | } | |
ae8f1541 RK |
629 | } |
630 | ||
14904927 SB |
631 | static void __init alloc_init_pud(pgd_t *pgd, unsigned long addr, |
632 | unsigned long end, unsigned long phys, const struct mem_type *type) | |
516295e5 RK |
633 | { |
634 | pud_t *pud = pud_offset(pgd, addr); | |
635 | unsigned long next; | |
636 | ||
637 | do { | |
638 | next = pud_addr_end(addr, end); | |
639 | alloc_init_section(pud, addr, next, phys, type); | |
640 | phys += next - addr; | |
641 | } while (pud++, addr = next, addr != end); | |
642 | } | |
643 | ||
1b6ba46b | 644 | #ifndef CONFIG_ARM_LPAE |
4a56c1e4 RK |
645 | static void __init create_36bit_mapping(struct map_desc *md, |
646 | const struct mem_type *type) | |
647 | { | |
97092e0c RK |
648 | unsigned long addr, length, end; |
649 | phys_addr_t phys; | |
4a56c1e4 RK |
650 | pgd_t *pgd; |
651 | ||
652 | addr = md->virtual; | |
cae6292b | 653 | phys = __pfn_to_phys(md->pfn); |
4a56c1e4 RK |
654 | length = PAGE_ALIGN(md->length); |
655 | ||
656 | if (!(cpu_architecture() >= CPU_ARCH_ARMv6 || cpu_is_xsc3())) { | |
657 | printk(KERN_ERR "MM: CPU does not support supersection " | |
658 | "mapping for 0x%08llx at 0x%08lx\n", | |
29a38193 | 659 | (long long)__pfn_to_phys((u64)md->pfn), addr); |
4a56c1e4 RK |
660 | return; |
661 | } | |
662 | ||
663 | /* N.B. ARMv6 supersections are only defined to work with domain 0. | |
664 | * Since domain assignments can in fact be arbitrary, the | |
665 | * 'domain == 0' check below is required to insure that ARMv6 | |
666 | * supersections are only allocated for domain 0 regardless | |
667 | * of the actual domain assignments in use. | |
668 | */ | |
669 | if (type->domain) { | |
670 | printk(KERN_ERR "MM: invalid domain in supersection " | |
671 | "mapping for 0x%08llx at 0x%08lx\n", | |
29a38193 | 672 | (long long)__pfn_to_phys((u64)md->pfn), addr); |
4a56c1e4 RK |
673 | return; |
674 | } | |
675 | ||
676 | if ((addr | length | __pfn_to_phys(md->pfn)) & ~SUPERSECTION_MASK) { | |
29a38193 WD |
677 | printk(KERN_ERR "MM: cannot create mapping for 0x%08llx" |
678 | " at 0x%08lx invalid alignment\n", | |
679 | (long long)__pfn_to_phys((u64)md->pfn), addr); | |
4a56c1e4 RK |
680 | return; |
681 | } | |
682 | ||
683 | /* | |
684 | * Shift bits [35:32] of address into bits [23:20] of PMD | |
685 | * (See ARMv6 spec). | |
686 | */ | |
687 | phys |= (((md->pfn >> (32 - PAGE_SHIFT)) & 0xF) << 20); | |
688 | ||
689 | pgd = pgd_offset_k(addr); | |
690 | end = addr + length; | |
691 | do { | |
516295e5 RK |
692 | pud_t *pud = pud_offset(pgd, addr); |
693 | pmd_t *pmd = pmd_offset(pud, addr); | |
4a56c1e4 RK |
694 | int i; |
695 | ||
696 | for (i = 0; i < 16; i++) | |
697 | *pmd++ = __pmd(phys | type->prot_sect | PMD_SECT_SUPER); | |
698 | ||
699 | addr += SUPERSECTION_SIZE; | |
700 | phys += SUPERSECTION_SIZE; | |
701 | pgd += SUPERSECTION_SIZE >> PGDIR_SHIFT; | |
702 | } while (addr != end); | |
703 | } | |
1b6ba46b | 704 | #endif /* !CONFIG_ARM_LPAE */ |
4a56c1e4 | 705 | |
ae8f1541 RK |
706 | /* |
707 | * Create the page directory entries and any necessary | |
708 | * page tables for the mapping specified by `md'. We | |
709 | * are able to cope here with varying sizes and address | |
710 | * offsets, and we take full advantage of sections and | |
711 | * supersections. | |
712 | */ | |
a2227120 | 713 | static void __init create_mapping(struct map_desc *md) |
ae8f1541 | 714 | { |
cae6292b WD |
715 | unsigned long addr, length, end; |
716 | phys_addr_t phys; | |
d5c98176 | 717 | const struct mem_type *type; |
24e6c699 | 718 | pgd_t *pgd; |
ae8f1541 RK |
719 | |
720 | if (md->virtual != vectors_base() && md->virtual < TASK_SIZE) { | |
29a38193 WD |
721 | printk(KERN_WARNING "BUG: not creating mapping for 0x%08llx" |
722 | " at 0x%08lx in user region\n", | |
723 | (long long)__pfn_to_phys((u64)md->pfn), md->virtual); | |
ae8f1541 RK |
724 | return; |
725 | } | |
726 | ||
727 | if ((md->type == MT_DEVICE || md->type == MT_ROM) && | |
0536bdf3 NP |
728 | md->virtual >= PAGE_OFFSET && |
729 | (md->virtual < VMALLOC_START || md->virtual >= VMALLOC_END)) { | |
29a38193 | 730 | printk(KERN_WARNING "BUG: mapping for 0x%08llx" |
0536bdf3 | 731 | " at 0x%08lx out of vmalloc space\n", |
29a38193 | 732 | (long long)__pfn_to_phys((u64)md->pfn), md->virtual); |
ae8f1541 RK |
733 | } |
734 | ||
d5c98176 | 735 | type = &mem_types[md->type]; |
ae8f1541 | 736 | |
1b6ba46b | 737 | #ifndef CONFIG_ARM_LPAE |
ae8f1541 RK |
738 | /* |
739 | * Catch 36-bit addresses | |
740 | */ | |
4a56c1e4 RK |
741 | if (md->pfn >= 0x100000) { |
742 | create_36bit_mapping(md, type); | |
743 | return; | |
ae8f1541 | 744 | } |
1b6ba46b | 745 | #endif |
ae8f1541 | 746 | |
7b9c7b4d | 747 | addr = md->virtual & PAGE_MASK; |
cae6292b | 748 | phys = __pfn_to_phys(md->pfn); |
7b9c7b4d | 749 | length = PAGE_ALIGN(md->length + (md->virtual & ~PAGE_MASK)); |
ae8f1541 | 750 | |
24e6c699 | 751 | if (type->prot_l1 == 0 && ((addr | phys | length) & ~SECTION_MASK)) { |
29a38193 | 752 | printk(KERN_WARNING "BUG: map for 0x%08llx at 0x%08lx can not " |
ae8f1541 | 753 | "be mapped using pages, ignoring.\n", |
29a38193 | 754 | (long long)__pfn_to_phys(md->pfn), addr); |
ae8f1541 RK |
755 | return; |
756 | } | |
757 | ||
24e6c699 RK |
758 | pgd = pgd_offset_k(addr); |
759 | end = addr + length; | |
760 | do { | |
761 | unsigned long next = pgd_addr_end(addr, end); | |
ae8f1541 | 762 | |
516295e5 | 763 | alloc_init_pud(pgd, addr, next, phys, type); |
ae8f1541 | 764 | |
24e6c699 RK |
765 | phys += next - addr; |
766 | addr = next; | |
767 | } while (pgd++, addr != end); | |
ae8f1541 RK |
768 | } |
769 | ||
770 | /* | |
771 | * Create the architecture specific mappings | |
772 | */ | |
773 | void __init iotable_init(struct map_desc *io_desc, int nr) | |
774 | { | |
0536bdf3 NP |
775 | struct map_desc *md; |
776 | struct vm_struct *vm; | |
777 | ||
778 | if (!nr) | |
779 | return; | |
ae8f1541 | 780 | |
0536bdf3 NP |
781 | vm = early_alloc_aligned(sizeof(*vm) * nr, __alignof__(*vm)); |
782 | ||
783 | for (md = io_desc; nr; md++, nr--) { | |
784 | create_mapping(md); | |
785 | vm->addr = (void *)(md->virtual & PAGE_MASK); | |
786 | vm->size = PAGE_ALIGN(md->length + (md->virtual & ~PAGE_MASK)); | |
c2794437 RH |
787 | vm->phys_addr = __pfn_to_phys(md->pfn); |
788 | vm->flags = VM_IOREMAP | VM_ARM_STATIC_MAPPING; | |
576d2f25 | 789 | vm->flags |= VM_ARM_MTYPE(md->type); |
0536bdf3 NP |
790 | vm->caller = iotable_init; |
791 | vm_area_add_early(vm++); | |
792 | } | |
ae8f1541 RK |
793 | } |
794 | ||
c2794437 RH |
795 | void __init vm_reserve_area_early(unsigned long addr, unsigned long size, |
796 | void *caller) | |
797 | { | |
798 | struct vm_struct *vm; | |
799 | ||
800 | vm = early_alloc_aligned(sizeof(*vm), __alignof__(*vm)); | |
801 | vm->addr = (void *)addr; | |
802 | vm->size = size; | |
803 | vm->flags = VM_IOREMAP | VM_ARM_STATIC_MAPPING; | |
804 | vm->caller = caller; | |
805 | vm_area_add_early(vm); | |
806 | } | |
807 | ||
19b52abe NP |
808 | #ifndef CONFIG_ARM_LPAE |
809 | ||
810 | /* | |
811 | * The Linux PMD is made of two consecutive section entries covering 2MB | |
812 | * (see definition in include/asm/pgtable-2level.h). However a call to | |
813 | * create_mapping() may optimize static mappings by using individual | |
814 | * 1MB section mappings. This leaves the actual PMD potentially half | |
815 | * initialized if the top or bottom section entry isn't used, leaving it | |
816 | * open to problems if a subsequent ioremap() or vmalloc() tries to use | |
817 | * the virtual space left free by that unused section entry. | |
818 | * | |
819 | * Let's avoid the issue by inserting dummy vm entries covering the unused | |
820 | * PMD halves once the static mappings are in place. | |
821 | */ | |
822 | ||
823 | static void __init pmd_empty_section_gap(unsigned long addr) | |
824 | { | |
c2794437 | 825 | vm_reserve_area_early(addr, SECTION_SIZE, pmd_empty_section_gap); |
19b52abe NP |
826 | } |
827 | ||
828 | static void __init fill_pmd_gaps(void) | |
829 | { | |
830 | struct vm_struct *vm; | |
831 | unsigned long addr, next = 0; | |
832 | pmd_t *pmd; | |
833 | ||
834 | /* we're still single threaded hence no lock needed here */ | |
835 | for (vm = vmlist; vm; vm = vm->next) { | |
836 | if (!(vm->flags & VM_ARM_STATIC_MAPPING)) | |
837 | continue; | |
838 | addr = (unsigned long)vm->addr; | |
839 | if (addr < next) | |
840 | continue; | |
841 | ||
842 | /* | |
843 | * Check if this vm starts on an odd section boundary. | |
844 | * If so and the first section entry for this PMD is free | |
845 | * then we block the corresponding virtual address. | |
846 | */ | |
847 | if ((addr & ~PMD_MASK) == SECTION_SIZE) { | |
848 | pmd = pmd_off_k(addr); | |
849 | if (pmd_none(*pmd)) | |
850 | pmd_empty_section_gap(addr & PMD_MASK); | |
851 | } | |
852 | ||
853 | /* | |
854 | * Then check if this vm ends on an odd section boundary. | |
855 | * If so and the second section entry for this PMD is empty | |
856 | * then we block the corresponding virtual address. | |
857 | */ | |
858 | addr += vm->size; | |
859 | if ((addr & ~PMD_MASK) == SECTION_SIZE) { | |
860 | pmd = pmd_off_k(addr) + 1; | |
861 | if (pmd_none(*pmd)) | |
862 | pmd_empty_section_gap(addr); | |
863 | } | |
864 | ||
865 | /* no need to look at any vm entry until we hit the next PMD */ | |
866 | next = (addr + PMD_SIZE - 1) & PMD_MASK; | |
867 | } | |
868 | } | |
869 | ||
870 | #else | |
871 | #define fill_pmd_gaps() do { } while (0) | |
872 | #endif | |
873 | ||
c2794437 RH |
874 | #if defined(CONFIG_PCI) && !defined(CONFIG_NEED_MACH_IO_H) |
875 | static void __init pci_reserve_io(void) | |
876 | { | |
877 | struct vm_struct *vm; | |
878 | unsigned long addr; | |
879 | ||
880 | /* we're still single threaded hence no lock needed here */ | |
881 | for (vm = vmlist; vm; vm = vm->next) { | |
882 | if (!(vm->flags & VM_ARM_STATIC_MAPPING)) | |
883 | continue; | |
884 | addr = (unsigned long)vm->addr; | |
885 | addr &= ~(SZ_2M - 1); | |
886 | if (addr == PCI_IO_VIRT_BASE) | |
887 | return; | |
888 | ||
889 | } | |
890 | vm_reserve_area_early(PCI_IO_VIRT_BASE, SZ_2M, pci_reserve_io); | |
891 | } | |
892 | #else | |
893 | #define pci_reserve_io() do { } while (0) | |
894 | #endif | |
895 | ||
0536bdf3 NP |
896 | static void * __initdata vmalloc_min = |
897 | (void *)(VMALLOC_END - (240 << 20) - VMALLOC_OFFSET); | |
6c5da7ac RK |
898 | |
899 | /* | |
900 | * vmalloc=size forces the vmalloc area to be exactly 'size' | |
901 | * bytes. This can be used to increase (or decrease) the vmalloc | |
0536bdf3 | 902 | * area - the default is 240m. |
6c5da7ac | 903 | */ |
2b0d8c25 | 904 | static int __init early_vmalloc(char *arg) |
6c5da7ac | 905 | { |
79612395 | 906 | unsigned long vmalloc_reserve = memparse(arg, NULL); |
6c5da7ac RK |
907 | |
908 | if (vmalloc_reserve < SZ_16M) { | |
909 | vmalloc_reserve = SZ_16M; | |
910 | printk(KERN_WARNING | |
911 | "vmalloc area too small, limiting to %luMB\n", | |
912 | vmalloc_reserve >> 20); | |
913 | } | |
9210807c NP |
914 | |
915 | if (vmalloc_reserve > VMALLOC_END - (PAGE_OFFSET + SZ_32M)) { | |
916 | vmalloc_reserve = VMALLOC_END - (PAGE_OFFSET + SZ_32M); | |
917 | printk(KERN_WARNING | |
918 | "vmalloc area is too big, limiting to %luMB\n", | |
919 | vmalloc_reserve >> 20); | |
920 | } | |
79612395 RK |
921 | |
922 | vmalloc_min = (void *)(VMALLOC_END - vmalloc_reserve); | |
2b0d8c25 | 923 | return 0; |
6c5da7ac | 924 | } |
2b0d8c25 | 925 | early_param("vmalloc", early_vmalloc); |
6c5da7ac | 926 | |
c7909509 | 927 | phys_addr_t arm_lowmem_limit __initdata = 0; |
8df65168 | 928 | |
0371d3f7 | 929 | void __init sanity_check_meminfo(void) |
60296c71 | 930 | { |
dde5828f | 931 | int i, j, highmem = 0; |
60296c71 | 932 | |
4b5f32ce | 933 | for (i = 0, j = 0; i < meminfo.nr_banks; i++) { |
a1bbaec0 NP |
934 | struct membank *bank = &meminfo.bank[j]; |
935 | *bank = meminfo.bank[i]; | |
60296c71 | 936 | |
77f73a2c WD |
937 | if (bank->start > ULONG_MAX) |
938 | highmem = 1; | |
939 | ||
a1bbaec0 | 940 | #ifdef CONFIG_HIGHMEM |
40f7bfe4 | 941 | if (__va(bank->start) >= vmalloc_min || |
dde5828f RK |
942 | __va(bank->start) < (void *)PAGE_OFFSET) |
943 | highmem = 1; | |
944 | ||
945 | bank->highmem = highmem; | |
946 | ||
a1bbaec0 NP |
947 | /* |
948 | * Split those memory banks which are partially overlapping | |
949 | * the vmalloc area greatly simplifying things later. | |
950 | */ | |
77f73a2c | 951 | if (!highmem && __va(bank->start) < vmalloc_min && |
79612395 | 952 | bank->size > vmalloc_min - __va(bank->start)) { |
a1bbaec0 NP |
953 | if (meminfo.nr_banks >= NR_BANKS) { |
954 | printk(KERN_CRIT "NR_BANKS too low, " | |
955 | "ignoring high memory\n"); | |
956 | } else { | |
957 | memmove(bank + 1, bank, | |
958 | (meminfo.nr_banks - i) * sizeof(*bank)); | |
959 | meminfo.nr_banks++; | |
960 | i++; | |
79612395 RK |
961 | bank[1].size -= vmalloc_min - __va(bank->start); |
962 | bank[1].start = __pa(vmalloc_min - 1) + 1; | |
dde5828f | 963 | bank[1].highmem = highmem = 1; |
a1bbaec0 NP |
964 | j++; |
965 | } | |
79612395 | 966 | bank->size = vmalloc_min - __va(bank->start); |
a1bbaec0 NP |
967 | } |
968 | #else | |
041d785f RK |
969 | bank->highmem = highmem; |
970 | ||
77f73a2c WD |
971 | /* |
972 | * Highmem banks not allowed with !CONFIG_HIGHMEM. | |
973 | */ | |
974 | if (highmem) { | |
975 | printk(KERN_NOTICE "Ignoring RAM at %.8llx-%.8llx " | |
976 | "(!CONFIG_HIGHMEM).\n", | |
977 | (unsigned long long)bank->start, | |
978 | (unsigned long long)bank->start + bank->size - 1); | |
979 | continue; | |
980 | } | |
981 | ||
a1bbaec0 NP |
982 | /* |
983 | * Check whether this memory bank would entirely overlap | |
984 | * the vmalloc area. | |
985 | */ | |
79612395 | 986 | if (__va(bank->start) >= vmalloc_min || |
f0bba9f9 | 987 | __va(bank->start) < (void *)PAGE_OFFSET) { |
e33b9d08 | 988 | printk(KERN_NOTICE "Ignoring RAM at %.8llx-%.8llx " |
a1bbaec0 | 989 | "(vmalloc region overlap).\n", |
e33b9d08 RK |
990 | (unsigned long long)bank->start, |
991 | (unsigned long long)bank->start + bank->size - 1); | |
a1bbaec0 NP |
992 | continue; |
993 | } | |
60296c71 | 994 | |
a1bbaec0 NP |
995 | /* |
996 | * Check whether this memory bank would partially overlap | |
997 | * the vmalloc area. | |
998 | */ | |
79612395 | 999 | if (__va(bank->start + bank->size) > vmalloc_min || |
a1bbaec0 | 1000 | __va(bank->start + bank->size) < __va(bank->start)) { |
79612395 | 1001 | unsigned long newsize = vmalloc_min - __va(bank->start); |
e33b9d08 RK |
1002 | printk(KERN_NOTICE "Truncating RAM at %.8llx-%.8llx " |
1003 | "to -%.8llx (vmalloc region overlap).\n", | |
1004 | (unsigned long long)bank->start, | |
1005 | (unsigned long long)bank->start + bank->size - 1, | |
1006 | (unsigned long long)bank->start + newsize - 1); | |
a1bbaec0 NP |
1007 | bank->size = newsize; |
1008 | } | |
1009 | #endif | |
c7909509 MS |
1010 | if (!bank->highmem && bank->start + bank->size > arm_lowmem_limit) |
1011 | arm_lowmem_limit = bank->start + bank->size; | |
40f7bfe4 | 1012 | |
a1bbaec0 | 1013 | j++; |
60296c71 | 1014 | } |
e616c591 RK |
1015 | #ifdef CONFIG_HIGHMEM |
1016 | if (highmem) { | |
1017 | const char *reason = NULL; | |
1018 | ||
1019 | if (cache_is_vipt_aliasing()) { | |
1020 | /* | |
1021 | * Interactions between kmap and other mappings | |
1022 | * make highmem support with aliasing VIPT caches | |
1023 | * rather difficult. | |
1024 | */ | |
1025 | reason = "with VIPT aliasing cache"; | |
e616c591 RK |
1026 | } |
1027 | if (reason) { | |
1028 | printk(KERN_CRIT "HIGHMEM is not supported %s, ignoring high memory\n", | |
1029 | reason); | |
1030 | while (j > 0 && meminfo.bank[j - 1].highmem) | |
1031 | j--; | |
1032 | } | |
1033 | } | |
1034 | #endif | |
4b5f32ce | 1035 | meminfo.nr_banks = j; |
c7909509 MS |
1036 | high_memory = __va(arm_lowmem_limit - 1) + 1; |
1037 | memblock_set_current_limit(arm_lowmem_limit); | |
60296c71 LB |
1038 | } |
1039 | ||
4b5f32ce | 1040 | static inline void prepare_page_table(void) |
d111e8f9 RK |
1041 | { |
1042 | unsigned long addr; | |
8df65168 | 1043 | phys_addr_t end; |
d111e8f9 RK |
1044 | |
1045 | /* | |
1046 | * Clear out all the mappings below the kernel image. | |
1047 | */ | |
e73fc88e | 1048 | for (addr = 0; addr < MODULES_VADDR; addr += PMD_SIZE) |
d111e8f9 RK |
1049 | pmd_clear(pmd_off_k(addr)); |
1050 | ||
1051 | #ifdef CONFIG_XIP_KERNEL | |
1052 | /* The XIP kernel is mapped in the module area -- skip over it */ | |
e73fc88e | 1053 | addr = ((unsigned long)_etext + PMD_SIZE - 1) & PMD_MASK; |
d111e8f9 | 1054 | #endif |
e73fc88e | 1055 | for ( ; addr < PAGE_OFFSET; addr += PMD_SIZE) |
d111e8f9 RK |
1056 | pmd_clear(pmd_off_k(addr)); |
1057 | ||
8df65168 RK |
1058 | /* |
1059 | * Find the end of the first block of lowmem. | |
1060 | */ | |
1061 | end = memblock.memory.regions[0].base + memblock.memory.regions[0].size; | |
c7909509 MS |
1062 | if (end >= arm_lowmem_limit) |
1063 | end = arm_lowmem_limit; | |
8df65168 | 1064 | |
d111e8f9 RK |
1065 | /* |
1066 | * Clear out all the kernel space mappings, except for the first | |
0536bdf3 | 1067 | * memory bank, up to the vmalloc region. |
d111e8f9 | 1068 | */ |
8df65168 | 1069 | for (addr = __phys_to_virt(end); |
0536bdf3 | 1070 | addr < VMALLOC_START; addr += PMD_SIZE) |
d111e8f9 RK |
1071 | pmd_clear(pmd_off_k(addr)); |
1072 | } | |
1073 | ||
1b6ba46b CM |
1074 | #ifdef CONFIG_ARM_LPAE |
1075 | /* the first page is reserved for pgd */ | |
1076 | #define SWAPPER_PG_DIR_SIZE (PAGE_SIZE + \ | |
1077 | PTRS_PER_PGD * PTRS_PER_PMD * sizeof(pmd_t)) | |
1078 | #else | |
e73fc88e | 1079 | #define SWAPPER_PG_DIR_SIZE (PTRS_PER_PGD * sizeof(pgd_t)) |
1b6ba46b | 1080 | #endif |
e73fc88e | 1081 | |
d111e8f9 | 1082 | /* |
2778f620 | 1083 | * Reserve the special regions of memory |
d111e8f9 | 1084 | */ |
2778f620 | 1085 | void __init arm_mm_memblock_reserve(void) |
d111e8f9 | 1086 | { |
d111e8f9 RK |
1087 | /* |
1088 | * Reserve the page tables. These are already in use, | |
1089 | * and can only be in node 0. | |
1090 | */ | |
e73fc88e | 1091 | memblock_reserve(__pa(swapper_pg_dir), SWAPPER_PG_DIR_SIZE); |
d111e8f9 | 1092 | |
d111e8f9 RK |
1093 | #ifdef CONFIG_SA1111 |
1094 | /* | |
1095 | * Because of the SA1111 DMA bug, we want to preserve our | |
1096 | * precious DMA-able memory... | |
1097 | */ | |
2778f620 | 1098 | memblock_reserve(PHYS_OFFSET, __pa(swapper_pg_dir) - PHYS_OFFSET); |
d111e8f9 | 1099 | #endif |
d111e8f9 RK |
1100 | } |
1101 | ||
1102 | /* | |
0536bdf3 NP |
1103 | * Set up the device mappings. Since we clear out the page tables for all |
1104 | * mappings above VMALLOC_START, we will remove any debug device mappings. | |
d111e8f9 RK |
1105 | * This means you have to be careful how you debug this function, or any |
1106 | * called function. This means you can't use any function or debugging | |
1107 | * method which may touch any device, otherwise the kernel _will_ crash. | |
1108 | */ | |
1109 | static void __init devicemaps_init(struct machine_desc *mdesc) | |
1110 | { | |
1111 | struct map_desc map; | |
1112 | unsigned long addr; | |
94e5a85b | 1113 | void *vectors; |
d111e8f9 RK |
1114 | |
1115 | /* | |
1116 | * Allocate the vector page early. | |
1117 | */ | |
94e5a85b RK |
1118 | vectors = early_alloc(PAGE_SIZE); |
1119 | ||
1120 | early_trap_init(vectors); | |
d111e8f9 | 1121 | |
0536bdf3 | 1122 | for (addr = VMALLOC_START; addr; addr += PMD_SIZE) |
d111e8f9 RK |
1123 | pmd_clear(pmd_off_k(addr)); |
1124 | ||
1125 | /* | |
1126 | * Map the kernel if it is XIP. | |
1127 | * It is always first in the modulearea. | |
1128 | */ | |
1129 | #ifdef CONFIG_XIP_KERNEL | |
1130 | map.pfn = __phys_to_pfn(CONFIG_XIP_PHYS_ADDR & SECTION_MASK); | |
ab4f2ee1 | 1131 | map.virtual = MODULES_VADDR; |
37efe642 | 1132 | map.length = ((unsigned long)_etext - map.virtual + ~SECTION_MASK) & SECTION_MASK; |
d111e8f9 RK |
1133 | map.type = MT_ROM; |
1134 | create_mapping(&map); | |
1135 | #endif | |
1136 | ||
1137 | /* | |
1138 | * Map the cache flushing regions. | |
1139 | */ | |
1140 | #ifdef FLUSH_BASE | |
1141 | map.pfn = __phys_to_pfn(FLUSH_BASE_PHYS); | |
1142 | map.virtual = FLUSH_BASE; | |
1143 | map.length = SZ_1M; | |
1144 | map.type = MT_CACHECLEAN; | |
1145 | create_mapping(&map); | |
1146 | #endif | |
1147 | #ifdef FLUSH_BASE_MINICACHE | |
1148 | map.pfn = __phys_to_pfn(FLUSH_BASE_PHYS + SZ_1M); | |
1149 | map.virtual = FLUSH_BASE_MINICACHE; | |
1150 | map.length = SZ_1M; | |
1151 | map.type = MT_MINICLEAN; | |
1152 | create_mapping(&map); | |
1153 | #endif | |
1154 | ||
1155 | /* | |
1156 | * Create a mapping for the machine vectors at the high-vectors | |
1157 | * location (0xffff0000). If we aren't using high-vectors, also | |
1158 | * create a mapping at the low-vectors virtual address. | |
1159 | */ | |
94e5a85b | 1160 | map.pfn = __phys_to_pfn(virt_to_phys(vectors)); |
d111e8f9 RK |
1161 | map.virtual = 0xffff0000; |
1162 | map.length = PAGE_SIZE; | |
1163 | map.type = MT_HIGH_VECTORS; | |
1164 | create_mapping(&map); | |
1165 | ||
1166 | if (!vectors_high()) { | |
1167 | map.virtual = 0; | |
1168 | map.type = MT_LOW_VECTORS; | |
1169 | create_mapping(&map); | |
1170 | } | |
1171 | ||
1172 | /* | |
1173 | * Ask the machine support to map in the statically mapped devices. | |
1174 | */ | |
1175 | if (mdesc->map_io) | |
1176 | mdesc->map_io(); | |
19b52abe | 1177 | fill_pmd_gaps(); |
d111e8f9 | 1178 | |
c2794437 RH |
1179 | /* Reserve fixed i/o space in VMALLOC region */ |
1180 | pci_reserve_io(); | |
1181 | ||
d111e8f9 RK |
1182 | /* |
1183 | * Finally flush the caches and tlb to ensure that we're in a | |
1184 | * consistent state wrt the writebuffer. This also ensures that | |
1185 | * any write-allocated cache lines in the vector page are written | |
1186 | * back. After this point, we can start to touch devices again. | |
1187 | */ | |
1188 | local_flush_tlb_all(); | |
1189 | flush_cache_all(); | |
1190 | } | |
1191 | ||
d73cd428 NP |
1192 | static void __init kmap_init(void) |
1193 | { | |
1194 | #ifdef CONFIG_HIGHMEM | |
4bb2e27d RK |
1195 | pkmap_page_table = early_pte_alloc(pmd_off_k(PKMAP_BASE), |
1196 | PKMAP_BASE, _PAGE_KERNEL_TABLE); | |
d73cd428 NP |
1197 | #endif |
1198 | } | |
1199 | ||
a2227120 RK |
1200 | static void __init map_lowmem(void) |
1201 | { | |
8df65168 | 1202 | struct memblock_region *reg; |
a2227120 RK |
1203 | |
1204 | /* Map all the lowmem memory banks. */ | |
8df65168 RK |
1205 | for_each_memblock(memory, reg) { |
1206 | phys_addr_t start = reg->base; | |
1207 | phys_addr_t end = start + reg->size; | |
1208 | struct map_desc map; | |
1209 | ||
c7909509 MS |
1210 | if (end > arm_lowmem_limit) |
1211 | end = arm_lowmem_limit; | |
8df65168 RK |
1212 | if (start >= end) |
1213 | break; | |
1214 | ||
1215 | map.pfn = __phys_to_pfn(start); | |
1216 | map.virtual = __phys_to_virt(start); | |
1217 | map.length = end - start; | |
1218 | map.type = MT_MEMORY; | |
a2227120 | 1219 | |
8df65168 | 1220 | create_mapping(&map); |
a2227120 RK |
1221 | } |
1222 | } | |
1223 | ||
d111e8f9 RK |
1224 | /* |
1225 | * paging_init() sets up the page tables, initialises the zone memory | |
1226 | * maps, and sets up the zero page, bad page and bad page tables. | |
1227 | */ | |
4b5f32ce | 1228 | void __init paging_init(struct machine_desc *mdesc) |
d111e8f9 RK |
1229 | { |
1230 | void *zero_page; | |
1231 | ||
c7909509 | 1232 | memblock_set_current_limit(arm_lowmem_limit); |
0371d3f7 | 1233 | |
d111e8f9 | 1234 | build_mem_type_table(); |
4b5f32ce | 1235 | prepare_page_table(); |
a2227120 | 1236 | map_lowmem(); |
c7909509 | 1237 | dma_contiguous_remap(); |
d111e8f9 | 1238 | devicemaps_init(mdesc); |
d73cd428 | 1239 | kmap_init(); |
d111e8f9 RK |
1240 | |
1241 | top_pmd = pmd_off_k(0xffff0000); | |
1242 | ||
3abe9d33 RK |
1243 | /* allocate the zero page. */ |
1244 | zero_page = early_alloc(PAGE_SIZE); | |
2778f620 | 1245 | |
8d717a52 | 1246 | bootmem_init(); |
2778f620 | 1247 | |
d111e8f9 | 1248 | empty_zero_page = virt_to_page(zero_page); |
421fe93c | 1249 | __flush_dcache_page(NULL, empty_zero_page); |
d111e8f9 | 1250 | } |