[deliverable/linux.git] / arch / arm / mm / proc-arm1020.S

/*
 *  linux/arch/arm/mm/proc-arm1020.S: MMU functions for ARM1020
 *
 *  Copyright (C) 2000 ARM Limited
 *  Copyright (C) 2000 Deep Blue Solutions Ltd.
 *  hacked for non-paged-MM by Hyok S. Choi, 2003.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 *
 *
 * These are the low level assembler for performing cache and TLB
 * functions on the arm1020.
 *
 *  CONFIG_CPU_ARM1020_CPU_IDLE -> nohlt
 */
#include <linux/linkage.h>
#include <linux/init.h>
#include <asm/assembler.h>
#include <asm/asm-offsets.h>
#include <asm/hwcap.h>
#include <asm/pgtable-hwdef.h>
#include <asm/pgtable.h>
#include <asm/ptrace.h>

#include "proc-macros.S"

/*
 * This is the maximum size of an area which will be invalidated
 * using the single invalidate entry instructions.  Anything larger
 * than this, and we go for the whole cache.
 *
 * This value should be chosen such that we choose the cheapest
 * alternative.
 */
#define MAX_AREA_SIZE	32768

/*
 * The size of one data cache line.
 */
#define CACHE_DLINESIZE	32

/*
 * The number of data cache segments.
 */
#define CACHE_DSEGMENTS	16

/*
 * The number of lines in a cache segment.
 */
#define CACHE_DENTRIES	64

/*
 * This is the size at which it becomes more efficient to
 * clean the whole cache, rather than using the individual
 * cache line maintenance instructions.
 */
#define CACHE_DLIMIT	32768

	.text
/*
 * cpu_arm1020_proc_init()
 */
ENTRY(cpu_arm1020_proc_init)
	mov	pc, lr

/*
 * cpu_arm1020_proc_fin()
 */
ENTRY(cpu_arm1020_proc_fin)
	mrc	p15, 0, r0, c1, c0, 0		@ ctrl register
	bic	r0, r0, #0x1000 		@ ...i............
	bic	r0, r0, #0x000e 		@ ............wca.
	mcr	p15, 0, r0, c1, c0, 0		@ disable caches
	mov	pc, lr

/*
 * cpu_arm1020_reset(loc)
 *
 * Perform a soft reset of the system.	Put the CPU into the
 * same state as it would be if it had been reset, and branch
 * to what would be the reset vector.
 *
 * loc: location to jump to for soft reset
 */
	.align	5
ENTRY(cpu_arm1020_reset)
	mov	ip, #0
	mcr	p15, 0, ip, c7, c7, 0		@ invalidate I,D caches
	mcr	p15, 0, ip, c7, c10, 4		@ drain WB
#ifdef CONFIG_MMU
	mcr	p15, 0, ip, c8, c7, 0		@ invalidate I & D TLBs
#endif
	mrc	p15, 0, ip, c1, c0, 0		@ ctrl register
	bic	ip, ip, #0x000f 		@ ............wcam
	bic	ip, ip, #0x1100 		@ ...i...s........
	mcr	p15, 0, ip, c1, c0, 0		@ ctrl register
	mov	pc, r0

/*
 * cpu_arm1020_do_idle()
 */
	.align	5
ENTRY(cpu_arm1020_do_idle)
	mcr	p15, 0, r0, c7, c0, 4		@ Wait for interrupt
	mov	pc, lr

/* ================================= CACHE ================================ */

	.align	5

/*
 *	flush_icache_all()
 *
 *	Unconditionally clean and invalidate the entire icache.
 */
ENTRY(arm1020_flush_icache_all)
#ifndef CONFIG_CPU_ICACHE_DISABLE
	mov	r0, #0
	mcr	p15, 0, r0, c7, c5, 0		@ invalidate I cache
#endif
	mov	pc, lr
ENDPROC(arm1020_flush_icache_all)

/*
 *	flush_user_cache_all()
 *
 *	Invalidate all cache entries in a particular address
 *	space.
 */
ENTRY(arm1020_flush_user_cache_all)
	/* FALLTHROUGH */
/*
 *	flush_kern_cache_all()
 *
 *	Clean and invalidate the entire cache.
 */
ENTRY(arm1020_flush_kern_cache_all)
	mov	r2, #VM_EXEC
	mov	ip, #0
__flush_whole_cache:
#ifndef CONFIG_CPU_DCACHE_DISABLE
	mcr	p15, 0, ip, c7, c10, 4		@ drain WB
	mov	r1, #(CACHE_DSEGMENTS - 1) << 5	@ 16 segments
1:	orr	r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries
2:	mcr	p15, 0, r3, c7, c14, 2		@ clean+invalidate D index
	mcr	p15, 0, ip, c7, c10, 4		@ drain WB
	subs	r3, r3, #1 << 26
	bcs	2b				@ entries 63 to 0
	subs	r1, r1, #1 << 5
	bcs	1b				@ segments 15 to 0
#endif
	tst	r2, #VM_EXEC
#ifndef CONFIG_CPU_ICACHE_DISABLE
	mcrne	p15, 0, ip, c7, c5, 0		@ invalidate I cache
#endif
	mcrne	p15, 0, ip, c7, c10, 4		@ drain WB
	mov	pc, lr

/*
 *	flush_user_cache_range(start, end, flags)
 *
 *	Invalidate a range of cache entries in the specified
 *	address space.
 *
 *	- start	- start address (inclusive)
 *	- end	- end address (exclusive)
 *	- flags	- vm_flags for this space
 */
ENTRY(arm1020_flush_user_cache_range)
	mov	ip, #0
	sub	r3, r1, r0			@ calculate total size
	cmp	r3, #CACHE_DLIMIT
	bhs	__flush_whole_cache

#ifndef CONFIG_CPU_DCACHE_DISABLE
	mcr	p15, 0, ip, c7, c10, 4
1:	mcr	p15, 0, r0, c7, c14, 1		@ clean+invalidate D entry
	mcr	p15, 0, ip, c7, c10, 4		@ drain WB
	add	r0, r0, #CACHE_DLINESIZE
	cmp	r0, r1
	blo	1b
#endif
	tst	r2, #VM_EXEC
#ifndef CONFIG_CPU_ICACHE_DISABLE
	mcrne	p15, 0, ip, c7, c5, 0		@ invalidate I cache
#endif
	mcrne	p15, 0, ip, c7, c10, 4		@ drain WB
	mov	pc, lr

/*
 *	coherent_kern_range(start, end)
 *
 *	Ensure coherency between the Icache and the Dcache in the
 *	region described by start.  If you have non-snooping
 *	Harvard caches, you need to implement this function.
 *
 *	- start	- virtual start address
 *	- end	- virtual end address
 */
ENTRY(arm1020_coherent_kern_range)
	/* FALLTRHOUGH */

/*
 *	coherent_user_range(start, end)
 *
 *	Ensure coherency between the Icache and the Dcache in the
 *	region described by start.  If you have non-snooping
 *	Harvard caches, you need to implement this function.
 *
 *	- start	- virtual start address
 *	- end	- virtual end address
 */
ENTRY(arm1020_coherent_user_range)
	mov	ip, #0
	bic	r0, r0, #CACHE_DLINESIZE - 1
	mcr	p15, 0, ip, c7, c10, 4
1:
#ifndef CONFIG_CPU_DCACHE_DISABLE
	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
	mcr	p15, 0, ip, c7, c10, 4		@ drain WB
#endif
#ifndef CONFIG_CPU_ICACHE_DISABLE
	mcr	p15, 0, r0, c7, c5, 1		@ invalidate I entry
#endif
	add	r0, r0, #CACHE_DLINESIZE
	cmp	r0, r1
	blo	1b
	mcr	p15, 0, ip, c7, c10, 4		@ drain WB
	mov	pc, lr

/*
 *	flush_kern_dcache_area(void *addr, size_t size)
 *
 *	Ensure no D cache aliasing occurs, either with itself or
 *	the I cache
 *
 *	- addr	- kernel address
 *	- size	- region size
 */
ENTRY(arm1020_flush_kern_dcache_area)
	mov	ip, #0
#ifndef CONFIG_CPU_DCACHE_DISABLE
	add	r1, r0, r1
1:	mcr	p15, 0, r0, c7, c14, 1		@ clean+invalidate D entry
	mcr	p15, 0, ip, c7, c10, 4		@ drain WB
	add	r0, r0, #CACHE_DLINESIZE
	cmp	r0, r1
	blo	1b
#endif
	mcr	p15, 0, ip, c7, c10, 4		@ drain WB
	mov	pc, lr

/*
 *	dma_inv_range(start, end)
 *
 *	Invalidate (discard) the specified virtual address range.
 *	May not write back any entries.  If 'start' or 'end'
 *	are not cache line aligned, those lines must be written
 *	back.
 *
 *	- start	- virtual start address
 *	- end	- virtual end address
 *
 * (same as v4wb)
 */
arm1020_dma_inv_range:
	mov	ip, #0
#ifndef CONFIG_CPU_DCACHE_DISABLE
	tst	r0, #CACHE_DLINESIZE - 1
	bic	r0, r0, #CACHE_DLINESIZE - 1
	mcrne	p15, 0, ip, c7, c10, 4
	mcrne	p15, 0, r0, c7, c10, 1		@ clean D entry
	mcrne	p15, 0, ip, c7, c10, 4		@ drain WB
	tst	r1, #CACHE_DLINESIZE - 1
	mcrne	p15, 0, ip, c7, c10, 4
	mcrne	p15, 0, r1, c7, c10, 1		@ clean D entry
	mcrne	p15, 0, ip, c7, c10, 4		@ drain WB
1:	mcr	p15, 0, r0, c7, c6, 1		@ invalidate D entry
	add	r0, r0, #CACHE_DLINESIZE
	cmp	r0, r1
	blo	1b
#endif
	mcr	p15, 0, ip, c7, c10, 4		@ drain WB
	mov	pc, lr

/*
 *	dma_clean_range(start, end)
 *
 *	Clean the specified virtual address range.
 *
 *	- start	- virtual start address
 *	- end	- virtual end address
 *
 * (same as v4wb)
 */
arm1020_dma_clean_range:
	mov	ip, #0
#ifndef CONFIG_CPU_DCACHE_DISABLE
	bic	r0, r0, #CACHE_DLINESIZE - 1
1:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
	mcr	p15, 0, ip, c7, c10, 4		@ drain WB
	add	r0, r0, #CACHE_DLINESIZE
	cmp	r0, r1
	blo	1b
#endif
	mcr	p15, 0, ip, c7, c10, 4		@ drain WB
	mov	pc, lr

/*
 *	dma_flush_range(start, end)
 *
 *	Clean and invalidate the specified virtual address range.
 *
 *	- start	- virtual start address
 *	- end	- virtual end address
 */
ENTRY(arm1020_dma_flush_range)
	mov	ip, #0
#ifndef CONFIG_CPU_DCACHE_DISABLE
	bic	r0, r0, #CACHE_DLINESIZE - 1
	mcr	p15, 0, ip, c7, c10, 4
1:	mcr	p15, 0, r0, c7, c14, 1		@ clean+invalidate D entry
	mcr	p15, 0, ip, c7, c10, 4		@ drain WB
	add	r0, r0, #CACHE_DLINESIZE
	cmp	r0, r1
	blo	1b
#endif
	mcr	p15, 0, ip, c7, c10, 4		@ drain WB
	mov	pc, lr

/*
 *	dma_map_area(start, size, dir)
 *	- start	- kernel virtual start address
 *	- size	- size of region
 *	- dir	- DMA direction
 */
ENTRY(arm1020_dma_map_area)
	add	r1, r1, r0
	cmp	r2, #DMA_TO_DEVICE
	beq	arm1020_dma_clean_range
	bcs	arm1020_dma_inv_range
	b	arm1020_dma_flush_range
ENDPROC(arm1020_dma_map_area)

/*
 *	dma_unmap_area(start, size, dir)
 *	- start	- kernel virtual start address
 *	- size	- size of region
 *	- dir	- DMA direction
 */
ENTRY(arm1020_dma_unmap_area)
	mov	pc, lr
ENDPROC(arm1020_dma_unmap_area)

	@ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S)
	define_cache_functions arm1020

	.align	5
ENTRY(cpu_arm1020_dcache_clean_area)
#ifndef CONFIG_CPU_DCACHE_DISABLE
	mov	ip, #0
1:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
	mcr	p15, 0, ip, c7, c10, 4		@ drain WB
	add	r0, r0, #CACHE_DLINESIZE
	subs	r1, r1, #CACHE_DLINESIZE
	bhi	1b
#endif
	mov	pc, lr

/* =============================== PageTable ============================== */

/*
 * cpu_arm1020_switch_mm(pgd)
 *
 * Set the translation base pointer to be as described by pgd.
 *
 * pgd: new page tables
 */
	.align	5
ENTRY(cpu_arm1020_switch_mm)
#ifdef CONFIG_MMU
#ifndef CONFIG_CPU_DCACHE_DISABLE
	mcr	p15, 0, r3, c7, c10, 4
	mov	r1, #0xF			@ 16 segments
1:	mov	r3, #0x3F			@ 64 entries
2:	mov	ip, r3, LSL #26 		@ shift up entry
	orr	ip, ip, r1, LSL #5		@ shift in/up index
	mcr	p15, 0, ip, c7, c14, 2		@ Clean & Inval DCache entry
	mov	ip, #0
	mcr	p15, 0, ip, c7, c10, 4
	subs	r3, r3, #1
	cmp	r3, #0
	bge	2b				@ entries 3F to 0
	subs	r1, r1, #1
	cmp	r1, #0
	bge	1b				@ segments 15 to 0

#endif
	mov	r1, #0
#ifndef CONFIG_CPU_ICACHE_DISABLE
	mcr	p15, 0, r1, c7, c5, 0		@ invalidate I cache
#endif
	mcr	p15, 0, r1, c7, c10, 4		@ drain WB
	mcr	p15, 0, r0, c2, c0, 0		@ load page table pointer
	mcr	p15, 0, r1, c8, c7, 0		@ invalidate I & D TLBs
#endif /* CONFIG_MMU */
	mov	pc, lr
        
/*
 * cpu_arm1020_set_pte(ptep, pte)
 *
 * Set a PTE and flush it out
 */
	.align	5
ENTRY(cpu_arm1020_set_pte_ext)
#ifdef CONFIG_MMU
	armv3_set_pte_ext
	mov	r0, r0
#ifndef CONFIG_CPU_DCACHE_DISABLE
	mcr	p15, 0, r0, c7, c10, 4
	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
#endif
	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
#endif /* CONFIG_MMU */
	mov	pc, lr

	__CPUINIT

	.type	__arm1020_setup, #function
__arm1020_setup:
	mov	r0, #0
	mcr	p15, 0, r0, c7, c7		@ invalidate I,D caches on v4
	mcr	p15, 0, r0, c7, c10, 4		@ drain write buffer on v4
#ifdef CONFIG_MMU
	mcr	p15, 0, r0, c8, c7		@ invalidate I,D TLBs on v4
#endif

	adr	r5, arm1020_crval
	ldmia	r5, {r5, r6}
	mrc	p15, 0, r0, c1, c0		@ get control register v4
	bic	r0, r0, r5
	orr	r0, r0, r6
#ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
	orr	r0, r0, #0x4000 		@ .R.. .... .... ....
#endif
	mov	pc, lr
	.size	__arm1020_setup, . - __arm1020_setup

	/*
	 *  R
	 * .RVI ZFRS BLDP WCAM
	 * .011 1001 ..11 0101
	 */
	.type	arm1020_crval, #object
arm1020_crval:
	crval	clear=0x0000593f, mmuset=0x00003935, ucset=0x00001930

	__INITDATA
	@ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
	define_processor_functions arm1020, dabort=v4t_early_abort, pabort=legacy_pabort


	.section ".rodata"

	string	cpu_arch_name, "armv5t"
	string	cpu_elf_name, "v5"

	.type	cpu_arm1020_name, #object
cpu_arm1020_name:
	.ascii	"ARM1020"
#ifndef CONFIG_CPU_ICACHE_DISABLE
	.ascii	"i"
#endif
#ifndef CONFIG_CPU_DCACHE_DISABLE
	.ascii	"d"
#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
	.ascii	"(wt)"
#else
	.ascii	"(wb)"
#endif
#endif
#ifndef CONFIG_CPU_BPREDICT_DISABLE
	.ascii	"B"
#endif
#ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
	.ascii	"RR"
#endif
	.ascii	"\0"
	.size	cpu_arm1020_name, . - cpu_arm1020_name

	.align

	.section ".proc.info.init", #alloc, #execinstr

	.type	__arm1020_proc_info,#object
__arm1020_proc_info:
	.long	0x4104a200			@ ARM 1020T (Architecture v5T)
	.long	0xff0ffff0
	.long   PMD_TYPE_SECT | \
		PMD_SECT_AP_WRITE | \
		PMD_SECT_AP_READ
	.long   PMD_TYPE_SECT | \
		PMD_SECT_AP_WRITE | \
		PMD_SECT_AP_READ
	b	__arm1020_setup
	.long	cpu_arch_name
	.long	cpu_elf_name
	.long	HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB
	.long	cpu_arm1020_name
	.long	arm1020_processor_functions
	.long	v4wbi_tlb_fns
	.long	v4wb_user_fns
	.long	arm1020_cache_fns
	.size	__arm1020_proc_info, . - __arm1020_proc_info
Commit	Line	Data
1da177e4 LT	1	/*
	2	* linux/arch/arm/mm/proc-arm1020.S: MMU functions for ARM1020
	3	*
	4	* Copyright (C) 2000 ARM Limited
	5	* Copyright (C) 2000 Deep Blue Solutions Ltd.
d090ddda	6	* hacked for non-paged-MM by Hyok S. Choi, 2003.
1da177e4 LT	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License as published by
	10	* the Free Software Foundation; either version 2 of the License, or
	11	* (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	21	*
	22	*
	23	* These are the low level assembler for performing cache and TLB
	24	* functions on the arm1020.
	25	*
	26	* CONFIG_CPU_ARM1020_CPU_IDLE -> nohlt
	27	*/
	28	#include <linux/linkage.h>
1da177e4 LT	29	#include <linux/init.h>
1da177e4 LT	30	#include <asm/assembler.h>
e6ae744d	31	#include <asm/asm-offsets.h>
5ec9407d	32	#include <asm/hwcap.h>
74945c86	33	#include <asm/pgtable-hwdef.h>
1da177e4	34	#include <asm/pgtable.h>
1da177e4	35	#include <asm/ptrace.h>
1da177e4	36
00eb0f6b RK	37	#include "proc-macros.S"
00eb0f6b RK	38
1da177e4 LT	39	/*
	40	* This is the maximum size of an area which will be invalidated
	41	* using the single invalidate entry instructions. Anything larger
	42	* than this, and we go for the whole cache.
	43	*
	44	* This value should be chosen such that we choose the cheapest
	45	* alternative.
	46	*/
	47	#define MAX_AREA_SIZE 32768
	48
	49	/*
	50	* The size of one data cache line.
	51	*/
	52	#define CACHE_DLINESIZE 32
	53
	54	/*
	55	* The number of data cache segments.
	56	*/
	57	#define CACHE_DSEGMENTS 16
	58
	59	/*
	60	* The number of lines in a cache segment.
	61	*/
	62	#define CACHE_DENTRIES 64
	63
	64	/*
	65	* This is the size at which it becomes more efficient to
	66	* clean the whole cache, rather than using the individual
25985edc	67	* cache line maintenance instructions.
1da177e4 LT	68	*/
	69	#define CACHE_DLIMIT 32768
	70
	71	.text
	72	/*
	73	* cpu_arm1020_proc_init()
	74	*/
	75	ENTRY(cpu_arm1020_proc_init)
	76	mov pc, lr
	77
	78	/*
	79	* cpu_arm1020_proc_fin()
	80	*/
	81	ENTRY(cpu_arm1020_proc_fin)
1da177e4 LT	82	mrc p15, 0, r0, c1, c0, 0 @ ctrl register
	83	bic r0, r0, #0x1000 @ ...i............
	84	bic r0, r0, #0x000e @ ............wca.
	85	mcr p15, 0, r0, c1, c0, 0 @ disable caches
9ca03a21	86	mov pc, lr
1da177e4 LT	87
	88	/*
	89	* cpu_arm1020_reset(loc)
	90	*
	91	* Perform a soft reset of the system. Put the CPU into the
	92	* same state as it would be if it had been reset, and branch
	93	* to what would be the reset vector.
	94	*
	95	* loc: location to jump to for soft reset
	96	*/
	97	.align 5
	98	ENTRY(cpu_arm1020_reset)
	99	mov ip, #0
	100	mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
	101	mcr p15, 0, ip, c7, c10, 4 @ drain WB
d090ddda	102	#ifdef CONFIG_MMU
1da177e4	103	mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
d090ddda	104	#endif
1da177e4 LT	105	mrc p15, 0, ip, c1, c0, 0 @ ctrl register
	106	bic ip, ip, #0x000f @ ............wcam
	107	bic ip, ip, #0x1100 @ ...i...s........
	108	mcr p15, 0, ip, c1, c0, 0 @ ctrl register
	109	mov pc, r0
	110
	111	/*
	112	* cpu_arm1020_do_idle()
	113	*/
	114	.align 5
	115	ENTRY(cpu_arm1020_do_idle)
	116	mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
	117	mov pc, lr
	118
	119	/* ================================= CACHE ================================ */
	120
	121	.align 5
c8c90860 MW	122
	123	/*
	124	* flush_icache_all()
	125	*
	126	* Unconditionally clean and invalidate the entire icache.
	127	*/
	128	ENTRY(arm1020_flush_icache_all)
	129	#ifndef CONFIG_CPU_ICACHE_DISABLE
	130	mov r0, #0
	131	mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
	132	#endif
	133	mov pc, lr
	134	ENDPROC(arm1020_flush_icache_all)
	135
1da177e4 LT	136	/*
	137	* flush_user_cache_all()
	138	*
	139	* Invalidate all cache entries in a particular address
	140	* space.
	141	*/
	142	ENTRY(arm1020_flush_user_cache_all)
	143	/* FALLTHROUGH */
	144	/*
	145	* flush_kern_cache_all()
	146	*
	147	* Clean and invalidate the entire cache.
	148	*/
	149	ENTRY(arm1020_flush_kern_cache_all)
	150	mov r2, #VM_EXEC
	151	mov ip, #0
	152	__flush_whole_cache:
	153	#ifndef CONFIG_CPU_DCACHE_DISABLE
	154	mcr p15, 0, ip, c7, c10, 4 @ drain WB
	155	mov r1, #(CACHE_DSEGMENTS - 1) << 5 @ 16 segments
	156	1: orr r3, r1, #(CACHE_DENTRIES - 1) << 26 @ 64 entries
	157	2: mcr p15, 0, r3, c7, c14, 2 @ clean+invalidate D index
	158	mcr p15, 0, ip, c7, c10, 4 @ drain WB
	159	subs r3, r3, #1 << 26
	160	bcs 2b @ entries 63 to 0
	161	subs r1, r1, #1 << 5
	162	bcs 1b @ segments 15 to 0
	163	#endif
	164	tst r2, #VM_EXEC
	165	#ifndef CONFIG_CPU_ICACHE_DISABLE
	166	mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
	167	#endif
	168	mcrne p15, 0, ip, c7, c10, 4 @ drain WB
	169	mov pc, lr
	170
	171	/*
	172	* flush_user_cache_range(start, end, flags)
	173	*
	174	* Invalidate a range of cache entries in the specified
	175	* address space.
	176	*
	177	* - start - start address (inclusive)
	178	* - end - end address (exclusive)
	179	* - flags - vm_flags for this space
	180	*/
	181	ENTRY(arm1020_flush_user_cache_range)
	182	mov ip, #0
	183	sub r3, r1, r0 @ calculate total size
	184	cmp r3, #CACHE_DLIMIT
	185	bhs __flush_whole_cache
	186
	187	#ifndef CONFIG_CPU_DCACHE_DISABLE
	188	mcr p15, 0, ip, c7, c10, 4
	189	1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
	190	mcr p15, 0, ip, c7, c10, 4 @ drain WB
	191	add r0, r0, #CACHE_DLINESIZE
	192	cmp r0, r1
	193	blo 1b
	194	#endif
	195	tst r2, #VM_EXEC
	196	#ifndef CONFIG_CPU_ICACHE_DISABLE
	197	mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
	198	#endif
	199	mcrne p15, 0, ip, c7, c10, 4 @ drain WB
200	mov pc, lr
201
202	/*
203	* coherent_kern_range(start, end)
204	*
205	* Ensure coherency between the Icache and the Dcache in the
206	* region described by start. If you have non-snooping
207	* Harvard caches, you need to implement this function.
208	*
209	* - start - virtual start address
210	* - end - virtual end address
211	*/
212	ENTRY(arm1020_coherent_kern_range)
213	/* FALLTRHOUGH */
214
215	/*
216	* coherent_user_range(start, end)
217	*
218	* Ensure coherency between the Icache and the Dcache in the
219	* region described by start. If you have non-snooping
220	* Harvard caches, you need to implement this function.
221	*
222	* - start - virtual start address
223	* - end - virtual end address
224	*/
225	ENTRY(arm1020_coherent_user_range)
226	mov ip, #0
227	bic r0, r0, #CACHE_DLINESIZE - 1
228	mcr p15, 0, ip, c7, c10, 4
229	1:
230	#ifndef CONFIG_CPU_DCACHE_DISABLE
231	mcr p15, 0, r0, c7, c10, 1 @ clean D entry
232	mcr p15, 0, ip, c7, c10, 4 @ drain WB
233	#endif
234	#ifndef CONFIG_CPU_ICACHE_DISABLE
235	mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
236	#endif
237	add r0, r0, #CACHE_DLINESIZE
238	cmp r0, r1
239	blo 1b
240	mcr p15, 0, ip, c7, c10, 4 @ drain WB
241	mov pc, lr
242
243	/*
2c9b9c84	244	* flush_kern_dcache_area(void *addr, size_t size)
1da177e4 LT	245	*
	246	* Ensure no D cache aliasing occurs, either with itself or
	247	* the I cache
	248	*
2c9b9c84 RK	249	* - addr - kernel address
2c9b9c84 RK	250	* - size - region size
1da177e4	251	*/
2c9b9c84	252	ENTRY(arm1020_flush_kern_dcache_area)
1da177e4 LT	253	mov ip, #0
1da177e4 LT	254	#ifndef CONFIG_CPU_DCACHE_DISABLE
2c9b9c84	255	add r1, r0, r1
1da177e4 LT	256	1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
	257	mcr p15, 0, ip, c7, c10, 4 @ drain WB
	258	add r0, r0, #CACHE_DLINESIZE
	259	cmp r0, r1
	260	blo 1b
	261	#endif
	262	mcr p15, 0, ip, c7, c10, 4 @ drain WB
	263	mov pc, lr
	264
	265	/*
	266	* dma_inv_range(start, end)
	267	*
	268	* Invalidate (discard) the specified virtual address range.
	269	* May not write back any entries. If 'start' or 'end'
	270	* are not cache line aligned, those lines must be written
	271	* back.
	272	*
	273	* - start - virtual start address
	274	* - end - virtual end address
	275	*
	276	* (same as v4wb)
	277	*/
702b94bf	278	arm1020_dma_inv_range:
1da177e4 LT	279	mov ip, #0
	280	#ifndef CONFIG_CPU_DCACHE_DISABLE
	281	tst r0, #CACHE_DLINESIZE - 1
	282	bic r0, r0, #CACHE_DLINESIZE - 1
	283	mcrne p15, 0, ip, c7, c10, 4
	284	mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
	285	mcrne p15, 0, ip, c7, c10, 4 @ drain WB
	286	tst r1, #CACHE_DLINESIZE - 1
	287	mcrne p15, 0, ip, c7, c10, 4
	288	mcrne p15, 0, r1, c7, c10, 1 @ clean D entry
	289	mcrne p15, 0, ip, c7, c10, 4 @ drain WB
	290	1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
	291	add r0, r0, #CACHE_DLINESIZE
	292	cmp r0, r1
	293	blo 1b
	294	#endif
	295	mcr p15, 0, ip, c7, c10, 4 @ drain WB
	296	mov pc, lr
	297
	298	/*
	299	* dma_clean_range(start, end)
	300	*
	301	* Clean the specified virtual address range.
	302	*
	303	* - start - virtual start address
	304	* - end - virtual end address
	305	*
	306	* (same as v4wb)
	307	*/
702b94bf	308	arm1020_dma_clean_range:
1da177e4 LT	309	mov ip, #0
	310	#ifndef CONFIG_CPU_DCACHE_DISABLE
	311	bic r0, r0, #CACHE_DLINESIZE - 1
	312	1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
	313	mcr p15, 0, ip, c7, c10, 4 @ drain WB
	314	add r0, r0, #CACHE_DLINESIZE
	315	cmp r0, r1
	316	blo 1b
	317	#endif
	318	mcr p15, 0, ip, c7, c10, 4 @ drain WB
	319	mov pc, lr
	320
	321	/*
	322	* dma_flush_range(start, end)
	323	*
	324	* Clean and invalidate the specified virtual address range.
	325	*
	326	* - start - virtual start address
	327	* - end - virtual end address
	328	*/
	329	ENTRY(arm1020_dma_flush_range)
	330	mov ip, #0
	331	#ifndef CONFIG_CPU_DCACHE_DISABLE
	332	bic r0, r0, #CACHE_DLINESIZE - 1
	333	mcr p15, 0, ip, c7, c10, 4
	334	1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
	335	mcr p15, 0, ip, c7, c10, 4 @ drain WB
	336	add r0, r0, #CACHE_DLINESIZE
	337	cmp r0, r1
	338	blo 1b
	339	#endif
	340	mcr p15, 0, ip, c7, c10, 4 @ drain WB
	341	mov pc, lr
	342
a9c9147e RK	343	/*
	344	* dma_map_area(start, size, dir)
	345	* - start - kernel virtual start address
	346	* - size - size of region
	347	* - dir - DMA direction
	348	*/
	349	ENTRY(arm1020_dma_map_area)
	350	add r1, r1, r0
	351	cmp r2, #DMA_TO_DEVICE
	352	beq arm1020_dma_clean_range
	353	bcs arm1020_dma_inv_range
	354	b arm1020_dma_flush_range
	355	ENDPROC(arm1020_dma_map_area)
	356
	357	/*
	358	* dma_unmap_area(start, size, dir)
	359	* - start - kernel virtual start address
	360	* - size - size of region
	361	* - dir - DMA direction
	362	*/
	363	ENTRY(arm1020_dma_unmap_area)
	364	mov pc, lr
	365	ENDPROC(arm1020_dma_unmap_area)
	366
56d91650 DM	367	@ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S)
56d91650 DM	368	define_cache_functions arm1020
1da177e4 LT	369
	370	.align 5
	371	ENTRY(cpu_arm1020_dcache_clean_area)
	372	#ifndef CONFIG_CPU_DCACHE_DISABLE
	373	mov ip, #0
	374	1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
	375	mcr p15, 0, ip, c7, c10, 4 @ drain WB
	376	add r0, r0, #CACHE_DLINESIZE
	377	subs r1, r1, #CACHE_DLINESIZE
	378	bhi 1b
	379	#endif
	380	mov pc, lr
	381
	382	/* =============================== PageTable ============================== */
	383
	384	/*
	385	* cpu_arm1020_switch_mm(pgd)
	386	*
	387	* Set the translation base pointer to be as described by pgd.
	388	*
	389	* pgd: new page tables
	390	*/
	391	.align 5
	392	ENTRY(cpu_arm1020_switch_mm)
d090ddda	393	#ifdef CONFIG_MMU
1da177e4 LT	394	#ifndef CONFIG_CPU_DCACHE_DISABLE
	395	mcr p15, 0, r3, c7, c10, 4
	396	mov r1, #0xF @ 16 segments
	397	1: mov r3, #0x3F @ 64 entries
	398	2: mov ip, r3, LSL #26 @ shift up entry
	399	orr ip, ip, r1, LSL #5 @ shift in/up index
	400	mcr p15, 0, ip, c7, c14, 2 @ Clean & Inval DCache entry
	401	mov ip, #0
	402	mcr p15, 0, ip, c7, c10, 4
	403	subs r3, r3, #1
	404	cmp r3, #0
	405	bge 2b @ entries 3F to 0
	406	subs r1, r1, #1
	407	cmp r1, #0
	408	bge 1b @ segments 15 to 0
	409
	410	#endif
	411	mov r1, #0
	412	#ifndef CONFIG_CPU_ICACHE_DISABLE
	413	mcr p15, 0, r1, c7, c5, 0 @ invalidate I cache
	414	#endif
	415	mcr p15, 0, r1, c7, c10, 4 @ drain WB
	416	mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
	417	mcr p15, 0, r1, c8, c7, 0 @ invalidate I & D TLBs
d090ddda	418	#endif /* CONFIG_MMU */
1da177e4 LT	419	mov pc, lr
	420
	421	/*
	422	* cpu_arm1020_set_pte(ptep, pte)
	423	*
	424	* Set a PTE and flush it out
	425	*/
	426	.align 5
ad1ae2fe	427	ENTRY(cpu_arm1020_set_pte_ext)
d090ddda	428	#ifdef CONFIG_MMU
da091653	429	armv3_set_pte_ext
1da177e4 LT	430	mov r0, r0
	431	#ifndef CONFIG_CPU_DCACHE_DISABLE
	432	mcr p15, 0, r0, c7, c10, 4
	433	mcr p15, 0, r0, c7, c10, 1 @ clean D entry
	434	#endif
	435	mcr p15, 0, r0, c7, c10, 4 @ drain WB
d090ddda	436	#endif /* CONFIG_MMU */
1da177e4 LT	437	mov pc, lr
1da177e4 LT	438
5085f3ff	439	__CPUINIT
1da177e4 LT	440
	441	.type __arm1020_setup, #function
	442	__arm1020_setup:
	443	mov r0, #0
	444	mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
	445	mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
d090ddda	446	#ifdef CONFIG_MMU
1da177e4	447	mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
d090ddda	448	#endif
22b19086 RK	449
	450	adr r5, arm1020_crval
	451	ldmia r5, {r5, r6}
1da177e4	452	mrc p15, 0, r0, c1, c0 @ get control register v4
1da177e4	453	bic r0, r0, r5
22b19086	454	orr r0, r0, r6
1da177e4 LT	455	#ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
	456	orr r0, r0, #0x4000 @ .R.. .... .... ....
	457	#endif
	458	mov pc, lr
	459	.size __arm1020_setup, . - __arm1020_setup
	460
	461	/*
	462	* R
	463	* .RVI ZFRS BLDP WCAM
abaf48a0	464	* .011 1001 ..11 0101
1da177e4	465	*/
22b19086 RK	466	.type arm1020_crval, #object
	467	arm1020_crval:
	468	crval clear=0x0000593f, mmuset=0x00003935, ucset=0x00001930
1da177e4 LT	469
1da177e4 LT	470	__INITDATA
56d91650 DM	471	@ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
56d91650 DM	472	define_processor_functions arm1020, dabort=v4t_early_abort, pabort=legacy_pabort
1da177e4	473
1da177e4 LT	474
	475	.section ".rodata"
	476
56d91650 DM	477	string cpu_arch_name, "armv5t"
56d91650 DM	478	string cpu_elf_name, "v5"
1da177e4 LT	479
	480	.type cpu_arm1020_name, #object
	481	cpu_arm1020_name:
	482	.ascii "ARM1020"
	483	#ifndef CONFIG_CPU_ICACHE_DISABLE
	484	.ascii "i"
	485	#endif
	486	#ifndef CONFIG_CPU_DCACHE_DISABLE
	487	.ascii "d"
	488	#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
	489	.ascii "(wt)"
	490	#else
	491	.ascii "(wb)"
	492	#endif
	493	#endif
	494	#ifndef CONFIG_CPU_BPREDICT_DISABLE
	495	.ascii "B"
	496	#endif
	497	#ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
	498	.ascii "RR"
	499	#endif
	500	.ascii "\0"
	501	.size cpu_arm1020_name, . - cpu_arm1020_name
	502
	503	.align
	504
02b7dd12	505	.section ".proc.info.init", #alloc, #execinstr
1da177e4 LT	506
	507	.type __arm1020_proc_info,#object
	508	__arm1020_proc_info:
	509	.long 0x4104a200 @ ARM 1020T (Architecture v5T)
	510	.long 0xff0ffff0
8799ee9f RK	511	.long PMD_TYPE_SECT \| \
	512	PMD_SECT_AP_WRITE \| \
	513	PMD_SECT_AP_READ
1da177e4 LT	514	.long PMD_TYPE_SECT \| \
	515	PMD_SECT_AP_WRITE \| \
	516	PMD_SECT_AP_READ
	517	b __arm1020_setup
	518	.long cpu_arch_name
	519	.long cpu_elf_name
	520	.long HWCAP_SWP \| HWCAP_HALF \| HWCAP_THUMB
	521	.long cpu_arm1020_name
	522	.long arm1020_processor_functions
	523	.long v4wbi_tlb_fns
	524	.long v4wb_user_fns
	525	.long arm1020_cache_fns
	526	.size __arm1020_proc_info, . - __arm1020_proc_info