[deliverable/linux.git] / arch / arm / mm / proc-arm926.S

/*
 *  linux/arch/arm/mm/proc-arm926.S: MMU functions for ARM926EJ-S
 *
 *  Copyright (C) 1999-2001 ARM Limited
 *  Copyright (C) 2000 Deep Blue Solutions Ltd.
 *  hacked for non-paged-MM by Hyok S. Choi, 2003.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 *
 *
 * These are the low level assembler for performing cache and TLB
 * functions on the arm926.
 *
 *  CONFIG_CPU_ARM926_CPU_IDLE -> nohlt
 */
#include <linux/linkage.h>
#include <linux/init.h>
#include <asm/assembler.h>
#include <asm/hwcap.h>
#include <asm/pgtable-hwdef.h>
#include <asm/pgtable.h>
#include <asm/page.h>
#include <asm/ptrace.h>
#include "proc-macros.S"

/*
 * This is the maximum size of an area which will be invalidated
 * using the single invalidate entry instructions.  Anything larger
 * than this, and we go for the whole cache.
 *
 * This value should be chosen such that we choose the cheapest
 * alternative.
 */
#define CACHE_DLIMIT	16384

/*
 * the cache line size of the I and D cache
 */
#define CACHE_DLINESIZE	32

	.text
/*
 * cpu_arm926_proc_init()
 */
ENTRY(cpu_arm926_proc_init)
	ret	lr

/*
 * cpu_arm926_proc_fin()
 */
ENTRY(cpu_arm926_proc_fin)
	mrc	p15, 0, r0, c1, c0, 0		@ ctrl register
	bic	r0, r0, #0x1000			@ ...i............
	bic	r0, r0, #0x000e			@ ............wca.
	mcr	p15, 0, r0, c1, c0, 0		@ disable caches
	ret	lr

/*
 * cpu_arm926_reset(loc)
 *
 * Perform a soft reset of the system.  Put the CPU into the
 * same state as it would be if it had been reset, and branch
 * to what would be the reset vector.
 *
 * loc: location to jump to for soft reset
 */
	.align	5
	.pushsection	.idmap.text, "ax"
ENTRY(cpu_arm926_reset)
	mov	ip, #0
	mcr	p15, 0, ip, c7, c7, 0		@ invalidate I,D caches
	mcr	p15, 0, ip, c7, c10, 4		@ drain WB
#ifdef CONFIG_MMU
	mcr	p15, 0, ip, c8, c7, 0		@ invalidate I & D TLBs
#endif
	mrc	p15, 0, ip, c1, c0, 0		@ ctrl register
	bic	ip, ip, #0x000f			@ ............wcam
	bic	ip, ip, #0x1100			@ ...i...s........
	mcr	p15, 0, ip, c1, c0, 0		@ ctrl register
	ret	r0
ENDPROC(cpu_arm926_reset)
	.popsection

/*
 * cpu_arm926_do_idle()
 *
 * Called with IRQs disabled
 */
	.align	10
ENTRY(cpu_arm926_do_idle)
	mov	r0, #0
	mrc	p15, 0, r1, c1, c0, 0		@ Read control register
	mcr	p15, 0, r0, c7, c10, 4		@ Drain write buffer
	bic	r2, r1, #1 << 12
	mrs	r3, cpsr			@ Disable FIQs while Icache
	orr	ip, r3, #PSR_F_BIT		@ is disabled
	msr	cpsr_c, ip
	mcr	p15, 0, r2, c1, c0, 0		@ Disable I cache
	mcr	p15, 0, r0, c7, c0, 4		@ Wait for interrupt
	mcr	p15, 0, r1, c1, c0, 0		@ Restore ICache enable
	msr	cpsr_c, r3			@ Restore FIQ state
	ret	lr

/*
 *	flush_icache_all()
 *
 *	Unconditionally clean and invalidate the entire icache.
 */
ENTRY(arm926_flush_icache_all)
	mov	r0, #0
	mcr	p15, 0, r0, c7, c5, 0		@ invalidate I cache
	ret	lr
ENDPROC(arm926_flush_icache_all)

/*
 *	flush_user_cache_all()
 *
 *	Clean and invalidate all cache entries in a particular
 *	address space.
 */
ENTRY(arm926_flush_user_cache_all)
	/* FALLTHROUGH */

/*
 *	flush_kern_cache_all()
 *
 *	Clean and invalidate the entire cache.
 */
ENTRY(arm926_flush_kern_cache_all)
	mov	r2, #VM_EXEC
	mov	ip, #0
__flush_whole_cache:
#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
	mcr	p15, 0, ip, c7, c6, 0		@ invalidate D cache
#else
1:	mrc	p15, 0, r15, c7, c14, 3 	@ test,clean,invalidate
	bne	1b
#endif
	tst	r2, #VM_EXEC
	mcrne	p15, 0, ip, c7, c5, 0		@ invalidate I cache
	mcrne	p15, 0, ip, c7, c10, 4		@ drain WB
	ret	lr

/*
 *	flush_user_cache_range(start, end, flags)
 *
 *	Clean and invalidate a range of cache entries in the
 *	specified address range.
 *
 *	- start	- start address (inclusive)
 *	- end	- end address (exclusive)
 *	- flags	- vm_flags describing address space
 */
ENTRY(arm926_flush_user_cache_range)
	mov	ip, #0
	sub	r3, r1, r0			@ calculate total size
	cmp	r3, #CACHE_DLIMIT
	bgt	__flush_whole_cache
1:	tst	r2, #VM_EXEC
#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
	mcr	p15, 0, r0, c7, c6, 1		@ invalidate D entry
	mcrne	p15, 0, r0, c7, c5, 1		@ invalidate I entry
	add	r0, r0, #CACHE_DLINESIZE
	mcr	p15, 0, r0, c7, c6, 1		@ invalidate D entry
	mcrne	p15, 0, r0, c7, c5, 1		@ invalidate I entry
	add	r0, r0, #CACHE_DLINESIZE
#else
	mcr	p15, 0, r0, c7, c14, 1		@ clean and invalidate D entry
	mcrne	p15, 0, r0, c7, c5, 1		@ invalidate I entry
	add	r0, r0, #CACHE_DLINESIZE
	mcr	p15, 0, r0, c7, c14, 1		@ clean and invalidate D entry
	mcrne	p15, 0, r0, c7, c5, 1		@ invalidate I entry
	add	r0, r0, #CACHE_DLINESIZE
#endif
	cmp	r0, r1
	blo	1b
	tst	r2, #VM_EXEC
	mcrne	p15, 0, ip, c7, c10, 4		@ drain WB
	ret	lr

/*
 *	coherent_kern_range(start, end)
 *
 *	Ensure coherency between the Icache and the Dcache in the
 *	region described by start, end.  If you have non-snooping
 *	Harvard caches, you need to implement this function.
 *
 *	- start	- virtual start address
 *	- end	- virtual end address
 */
ENTRY(arm926_coherent_kern_range)
	/* FALLTHROUGH */

/*
 *	coherent_user_range(start, end)
 *
 *	Ensure coherency between the Icache and the Dcache in the
 *	region described by start, end.  If you have non-snooping
 *	Harvard caches, you need to implement this function.
 *
 *	- start	- virtual start address
 *	- end	- virtual end address
 */
ENTRY(arm926_coherent_user_range)
	bic	r0, r0, #CACHE_DLINESIZE - 1
1:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
	mcr	p15, 0, r0, c7, c5, 1		@ invalidate I entry
	add	r0, r0, #CACHE_DLINESIZE
	cmp	r0, r1
	blo	1b
	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
	mov	r0, #0
	ret	lr

/*
 *	flush_kern_dcache_area(void *addr, size_t size)
 *
 *	Ensure no D cache aliasing occurs, either with itself or
 *	the I cache
 *
 *	- addr	- kernel address
 *	- size	- region size
 */
ENTRY(arm926_flush_kern_dcache_area)
	add	r1, r0, r1
1:	mcr	p15, 0, r0, c7, c14, 1		@ clean+invalidate D entry
	add	r0, r0, #CACHE_DLINESIZE
	cmp	r0, r1
	blo	1b
	mov	r0, #0
	mcr	p15, 0, r0, c7, c5, 0		@ invalidate I cache
	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
	ret	lr

/*
 *	dma_inv_range(start, end)
 *
 *	Invalidate (discard) the specified virtual address range.
 *	May not write back any entries.  If 'start' or 'end'
 *	are not cache line aligned, those lines must be written
 *	back.
 *
 *	- start	- virtual start address
 *	- end	- virtual end address
 *
 * (same as v4wb)
 */
arm926_dma_inv_range:
#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
	tst	r0, #CACHE_DLINESIZE - 1
	mcrne	p15, 0, r0, c7, c10, 1		@ clean D entry
	tst	r1, #CACHE_DLINESIZE - 1
	mcrne	p15, 0, r1, c7, c10, 1		@ clean D entry
#endif
	bic	r0, r0, #CACHE_DLINESIZE - 1
1:	mcr	p15, 0, r0, c7, c6, 1		@ invalidate D entry
	add	r0, r0, #CACHE_DLINESIZE
	cmp	r0, r1
	blo	1b
	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
	ret	lr

/*
 *	dma_clean_range(start, end)
 *
 *	Clean the specified virtual address range.
 *
 *	- start	- virtual start address
 *	- end	- virtual end address
 *
 * (same as v4wb)
 */
arm926_dma_clean_range:
#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
	bic	r0, r0, #CACHE_DLINESIZE - 1
1:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
	add	r0, r0, #CACHE_DLINESIZE
	cmp	r0, r1
	blo	1b
#endif
	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
	ret	lr

/*
 *	dma_flush_range(start, end)
 *
 *	Clean and invalidate the specified virtual address range.
 *
 *	- start	- virtual start address
 *	- end	- virtual end address
 */
ENTRY(arm926_dma_flush_range)
	bic	r0, r0, #CACHE_DLINESIZE - 1
1:
#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
	mcr	p15, 0, r0, c7, c14, 1		@ clean+invalidate D entry
#else
	mcr	p15, 0, r0, c7, c6, 1		@ invalidate D entry
#endif
	add	r0, r0, #CACHE_DLINESIZE
	cmp	r0, r1
	blo	1b
	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
	ret	lr

/*
 *	dma_map_area(start, size, dir)
 *	- start	- kernel virtual start address
 *	- size	- size of region
 *	- dir	- DMA direction
 */
ENTRY(arm926_dma_map_area)
	add	r1, r1, r0
	cmp	r2, #DMA_TO_DEVICE
	beq	arm926_dma_clean_range
	bcs	arm926_dma_inv_range
	b	arm926_dma_flush_range
ENDPROC(arm926_dma_map_area)

/*
 *	dma_unmap_area(start, size, dir)
 *	- start	- kernel virtual start address
 *	- size	- size of region
 *	- dir	- DMA direction
 */
ENTRY(arm926_dma_unmap_area)
	ret	lr
ENDPROC(arm926_dma_unmap_area)

	.globl	arm926_flush_kern_cache_louis
	.equ	arm926_flush_kern_cache_louis, arm926_flush_kern_cache_all

	@ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S)
	define_cache_functions arm926

ENTRY(cpu_arm926_dcache_clean_area)
#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
1:	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
	add	r0, r0, #CACHE_DLINESIZE
	subs	r1, r1, #CACHE_DLINESIZE
	bhi	1b
#endif
	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
	ret	lr

/* =============================== PageTable ============================== */

/*
 * cpu_arm926_switch_mm(pgd)
 *
 * Set the translation base pointer to be as described by pgd.
 *
 * pgd: new page tables
 */
	.align	5
ENTRY(cpu_arm926_switch_mm)
#ifdef CONFIG_MMU
	mov	ip, #0
#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
	mcr	p15, 0, ip, c7, c6, 0		@ invalidate D cache
#else
@ && 'Clean & Invalidate whole DCache'
1:	mrc	p15, 0, r15, c7, c14, 3 	@ test,clean,invalidate
	bne	1b
#endif
	mcr	p15, 0, ip, c7, c5, 0		@ invalidate I cache
	mcr	p15, 0, ip, c7, c10, 4		@ drain WB
	mcr	p15, 0, r0, c2, c0, 0		@ load page table pointer
	mcr	p15, 0, ip, c8, c7, 0		@ invalidate I & D TLBs
#endif
	ret	lr

/*
 * cpu_arm926_set_pte_ext(ptep, pte, ext)
 *
 * Set a PTE and flush it out
 */
	.align	5
ENTRY(cpu_arm926_set_pte_ext)
#ifdef CONFIG_MMU
	armv3_set_pte_ext
	mov	r0, r0
#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
	mcr	p15, 0, r0, c7, c10, 1		@ clean D entry
#endif
	mcr	p15, 0, r0, c7, c10, 4		@ drain WB
#endif
	ret	lr

/* Suspend/resume support: taken from arch/arm/plat-s3c24xx/sleep.S */
.globl	cpu_arm926_suspend_size
.equ	cpu_arm926_suspend_size, 4 * 3
#ifdef CONFIG_ARM_CPU_SUSPEND
ENTRY(cpu_arm926_do_suspend)
	stmfd	sp!, {r4 - r6, lr}
	mrc	p15, 0, r4, c13, c0, 0	@ PID
	mrc	p15, 0, r5, c3, c0, 0	@ Domain ID
	mrc	p15, 0, r6, c1, c0, 0	@ Control register
	stmia	r0, {r4 - r6}
	ldmfd	sp!, {r4 - r6, pc}
ENDPROC(cpu_arm926_do_suspend)

ENTRY(cpu_arm926_do_resume)
	mov	ip, #0
	mcr	p15, 0, ip, c8, c7, 0	@ invalidate I+D TLBs
	mcr	p15, 0, ip, c7, c7, 0	@ invalidate I+D caches
	ldmia	r0, {r4 - r6}
	mcr	p15, 0, r4, c13, c0, 0	@ PID
	mcr	p15, 0, r5, c3, c0, 0	@ Domain ID
	mcr	p15, 0, r1, c2, c0, 0	@ TTB address
	mov	r0, r6			@ control register
	b	cpu_resume_mmu
ENDPROC(cpu_arm926_do_resume)
#endif

	.type	__arm926_setup, #function
__arm926_setup:
	mov	r0, #0
	mcr	p15, 0, r0, c7, c7		@ invalidate I,D caches on v4
	mcr	p15, 0, r0, c7, c10, 4		@ drain write buffer on v4
#ifdef CONFIG_MMU
	mcr	p15, 0, r0, c8, c7		@ invalidate I,D TLBs on v4
#endif


#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
	mov	r0, #4				@ disable write-back on caches explicitly
	mcr	p15, 7, r0, c15, c0, 0
#endif 

	adr	r5, arm926_crval
	ldmia	r5, {r5, r6}
	mrc	p15, 0, r0, c1, c0		@ get control register v4
	bic	r0, r0, r5
	orr	r0, r0, r6
#ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
	orr	r0, r0, #0x4000			@ .1.. .... .... ....
#endif
	ret	lr
	.size	__arm926_setup, . - __arm926_setup

	/*
	 *  R
	 * .RVI ZFRS BLDP WCAM
	 * .011 0001 ..11 0101
	 * 
	 */
	.type	arm926_crval, #object
arm926_crval:
	crval	clear=0x00007f3f, mmuset=0x00003135, ucset=0x00001134

	__INITDATA

	@ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
	define_processor_functions arm926, dabort=v5tj_early_abort, pabort=legacy_pabort, suspend=1

	.section ".rodata"

	string	cpu_arch_name, "armv5tej"
	string	cpu_elf_name, "v5"
	string	cpu_arm926_name, "ARM926EJ-S"

	.align

	.section ".proc.info.init", #alloc

	.type	__arm926_proc_info,#object
__arm926_proc_info:
	.long	0x41069260			@ ARM926EJ-S (v5TEJ)
	.long	0xff0ffff0
	.long   PMD_TYPE_SECT | \
		PMD_SECT_BUFFERABLE | \
		PMD_SECT_CACHEABLE | \
		PMD_BIT4 | \
		PMD_SECT_AP_WRITE | \
		PMD_SECT_AP_READ
	.long   PMD_TYPE_SECT | \
		PMD_BIT4 | \
		PMD_SECT_AP_WRITE | \
		PMD_SECT_AP_READ
	initfn	__arm926_setup, __arm926_proc_info
	.long	cpu_arch_name
	.long	cpu_elf_name
	.long	HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP|HWCAP_JAVA
	.long	cpu_arm926_name
	.long	arm926_processor_functions
	.long	v4wbi_tlb_fns
	.long	v4wb_user_fns
	.long	arm926_cache_fns
	.size	__arm926_proc_info, . - __arm926_proc_info
Commit	Line	Data
1da177e4 LT	1	/*
	2	* linux/arch/arm/mm/proc-arm926.S: MMU functions for ARM926EJ-S
	3	*
	4	* Copyright (C) 1999-2001 ARM Limited
	5	* Copyright (C) 2000 Deep Blue Solutions Ltd.
d090ddda	6	* hacked for non-paged-MM by Hyok S. Choi, 2003.
1da177e4 LT	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License as published by
	10	* the Free Software Foundation; either version 2 of the License, or
	11	* (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	21	*
	22	*
	23	* These are the low level assembler for performing cache and TLB
	24	* functions on the arm926.
	25	*
	26	* CONFIG_CPU_ARM926_CPU_IDLE -> nohlt
	27	*/
	28	#include <linux/linkage.h>
1da177e4 LT	29	#include <linux/init.h>
1da177e4 LT	30	#include <asm/assembler.h>
5ec9407d	31	#include <asm/hwcap.h>
74945c86	32	#include <asm/pgtable-hwdef.h>
1da177e4	33	#include <asm/pgtable.h>
1da177e4 LT	34	#include <asm/page.h>
	35	#include <asm/ptrace.h>
	36	#include "proc-macros.S"
	37
	38	/*
	39	* This is the maximum size of an area which will be invalidated
	40	* using the single invalidate entry instructions. Anything larger
	41	* than this, and we go for the whole cache.
	42	*
	43	* This value should be chosen such that we choose the cheapest
	44	* alternative.
	45	*/
	46	#define CACHE_DLIMIT 16384
	47
	48	/*
	49	* the cache line size of the I and D cache
	50	*/
	51	#define CACHE_DLINESIZE 32
	52
	53	.text
	54	/*
	55	* cpu_arm926_proc_init()
	56	*/
	57	ENTRY(cpu_arm926_proc_init)
6ebbf2ce	58	ret lr
1da177e4 LT	59
	60	/*
	61	* cpu_arm926_proc_fin()
	62	*/
	63	ENTRY(cpu_arm926_proc_fin)
1da177e4 LT	64	mrc p15, 0, r0, c1, c0, 0 @ ctrl register
	65	bic r0, r0, #0x1000 @ ...i............
	66	bic r0, r0, #0x000e @ ............wca.
	67	mcr p15, 0, r0, c1, c0, 0 @ disable caches
6ebbf2ce	68	ret lr
1da177e4 LT	69
	70	/*
	71	* cpu_arm926_reset(loc)
	72	*
	73	* Perform a soft reset of the system. Put the CPU into the
	74	* same state as it would be if it had been reset, and branch
	75	* to what would be the reset vector.
	76	*
	77	* loc: location to jump to for soft reset
	78	*/
	79	.align 5
1a4baafa	80	.pushsection .idmap.text, "ax"
1da177e4 LT	81	ENTRY(cpu_arm926_reset)
	82	mov ip, #0
	83	mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches
	84	mcr p15, 0, ip, c7, c10, 4 @ drain WB
d090ddda	85	#ifdef CONFIG_MMU
1da177e4	86	mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
d090ddda	87	#endif
1da177e4 LT	88	mrc p15, 0, ip, c1, c0, 0 @ ctrl register
	89	bic ip, ip, #0x000f @ ............wcam
	90	bic ip, ip, #0x1100 @ ...i...s........
	91	mcr p15, 0, ip, c1, c0, 0 @ ctrl register
6ebbf2ce	92	ret r0
1a4baafa WD	93	ENDPROC(cpu_arm926_reset)
1a4baafa WD	94	.popsection
1da177e4 LT	95
	96	/*
	97	* cpu_arm926_do_idle()
	98	*
	99	* Called with IRQs disabled
	100	*/
	101	.align 10
	102	ENTRY(cpu_arm926_do_idle)
	103	mov r0, #0
	104	mrc p15, 0, r1, c1, c0, 0 @ Read control register
	105	mcr p15, 0, r0, c7, c10, 4 @ Drain write buffer
	106	bic r2, r1, #1 << 12
0214f922 RK	107	mrs r3, cpsr @ Disable FIQs while Icache
	108	orr ip, r3, #PSR_F_BIT @ is disabled
	109	msr cpsr_c, ip
1da177e4 LT	110	mcr p15, 0, r2, c1, c0, 0 @ Disable I cache
	111	mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt
	112	mcr p15, 0, r1, c1, c0, 0 @ Restore ICache enable
0214f922	113	msr cpsr_c, r3 @ Restore FIQ state
6ebbf2ce	114	ret lr
1da177e4	115
c8c90860 MW	116	/*
	117	* flush_icache_all()
	118	*
	119	* Unconditionally clean and invalidate the entire icache.
	120	*/
	121	ENTRY(arm926_flush_icache_all)
	122	mov r0, #0
	123	mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
6ebbf2ce	124	ret lr
c8c90860 MW	125	ENDPROC(arm926_flush_icache_all)
c8c90860 MW	126
1da177e4 LT	127	/*
	128	* flush_user_cache_all()
	129	*
	130	* Clean and invalidate all cache entries in a particular
	131	* address space.
	132	*/
	133	ENTRY(arm926_flush_user_cache_all)
	134	/* FALLTHROUGH */
	135
	136	/*
	137	* flush_kern_cache_all()
	138	*
	139	* Clean and invalidate the entire cache.
	140	*/
	141	ENTRY(arm926_flush_kern_cache_all)
	142	mov r2, #VM_EXEC
	143	mov ip, #0
	144	__flush_whole_cache:
	145	#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
	146	mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
	147	#else
	148	1: mrc p15, 0, r15, c7, c14, 3 @ test,clean,invalidate
	149	bne 1b
	150	#endif
	151	tst r2, #VM_EXEC
	152	mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache
	153	mcrne p15, 0, ip, c7, c10, 4 @ drain WB
6ebbf2ce	154	ret lr
1da177e4 LT	155
	156	/*
	157	* flush_user_cache_range(start, end, flags)
	158	*
	159	* Clean and invalidate a range of cache entries in the
	160	* specified address range.
	161	*
	162	* - start - start address (inclusive)
	163	* - end - end address (exclusive)
	164	* - flags - vm_flags describing address space
	165	*/
	166	ENTRY(arm926_flush_user_cache_range)
	167	mov ip, #0
	168	sub r3, r1, r0 @ calculate total size
	169	cmp r3, #CACHE_DLIMIT
	170	bgt __flush_whole_cache
	171	1: tst r2, #VM_EXEC
	172	#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
	173	mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
	174	mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
	175	add r0, r0, #CACHE_DLINESIZE
	176	mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
	177	mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
	178	add r0, r0, #CACHE_DLINESIZE
	179	#else
	180	mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
	181	mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
	182	add r0, r0, #CACHE_DLINESIZE
	183	mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry
	184	mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry
	185	add r0, r0, #CACHE_DLINESIZE
	186	#endif
	187	cmp r0, r1
	188	blo 1b
	189	tst r2, #VM_EXEC
	190	mcrne p15, 0, ip, c7, c10, 4 @ drain WB
6ebbf2ce	191	ret lr
1da177e4 LT	192
	193	/*
	194	* coherent_kern_range(start, end)
	195	*
	196	* Ensure coherency between the Icache and the Dcache in the
	197	* region described by start, end. If you have non-snooping
	198	* Harvard caches, you need to implement this function.
	199	*
	200	* - start - virtual start address
	201	* - end - virtual end address
	202	*/
	203	ENTRY(arm926_coherent_kern_range)
	204	/* FALLTHROUGH */
	205
	206	/*
	207	* coherent_user_range(start, end)
	208	*
	209	* Ensure coherency between the Icache and the Dcache in the
	210	* region described by start, end. If you have non-snooping
	211	* Harvard caches, you need to implement this function.
	212	*
	213	* - start - virtual start address
	214	* - end - virtual end address
	215	*/
	216	ENTRY(arm926_coherent_user_range)
	217	bic r0, r0, #CACHE_DLINESIZE - 1
	218	1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
	219	mcr p15, 0, r0, c7, c5, 1 @ invalidate I entry
	220	add r0, r0, #CACHE_DLINESIZE
	221	cmp r0, r1
	222	blo 1b
	223	mcr p15, 0, r0, c7, c10, 4 @ drain WB
c5102f59	224	mov r0, #0
6ebbf2ce	225	ret lr
1da177e4 LT	226
1da177e4 LT	227	/*
2c9b9c84	228	* flush_kern_dcache_area(void *addr, size_t size)
1da177e4 LT	229	*
	230	* Ensure no D cache aliasing occurs, either with itself or
	231	* the I cache
	232	*
2c9b9c84 RK	233	* - addr - kernel address
2c9b9c84 RK	234	* - size - region size
1da177e4	235	*/
2c9b9c84 RK	236	ENTRY(arm926_flush_kern_dcache_area)
2c9b9c84 RK	237	add r1, r0, r1
1da177e4 LT	238	1: mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
	239	add r0, r0, #CACHE_DLINESIZE
	240	cmp r0, r1
	241	blo 1b
	242	mov r0, #0
	243	mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache
	244	mcr p15, 0, r0, c7, c10, 4 @ drain WB
6ebbf2ce	245	ret lr
1da177e4 LT	246
	247	/*
	248	* dma_inv_range(start, end)
	249	*
	250	* Invalidate (discard) the specified virtual address range.
	251	* May not write back any entries. If 'start' or 'end'
	252	* are not cache line aligned, those lines must be written
	253	* back.
	254	*
	255	* - start - virtual start address
	256	* - end - virtual end address
	257	*
	258	* (same as v4wb)
	259	*/
702b94bf	260	arm926_dma_inv_range:
1da177e4 LT	261	#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
	262	tst r0, #CACHE_DLINESIZE - 1
	263	mcrne p15, 0, r0, c7, c10, 1 @ clean D entry
	264	tst r1, #CACHE_DLINESIZE - 1
	265	mcrne p15, 0, r1, c7, c10, 1 @ clean D entry
	266	#endif
	267	bic r0, r0, #CACHE_DLINESIZE - 1
	268	1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
	269	add r0, r0, #CACHE_DLINESIZE
	270	cmp r0, r1
	271	blo 1b
	272	mcr p15, 0, r0, c7, c10, 4 @ drain WB
6ebbf2ce	273	ret lr
1da177e4 LT	274
	275	/*
	276	* dma_clean_range(start, end)
	277	*
	278	* Clean the specified virtual address range.
	279	*
	280	* - start - virtual start address
	281	* - end - virtual end address
	282	*
	283	* (same as v4wb)
	284	*/
702b94bf	285	arm926_dma_clean_range:
1da177e4 LT	286	#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
	287	bic r0, r0, #CACHE_DLINESIZE - 1
	288	1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
	289	add r0, r0, #CACHE_DLINESIZE
	290	cmp r0, r1
	291	blo 1b
	292	#endif
	293	mcr p15, 0, r0, c7, c10, 4 @ drain WB
6ebbf2ce	294	ret lr
1da177e4 LT	295
	296	/*
	297	* dma_flush_range(start, end)
	298	*
	299	* Clean and invalidate the specified virtual address range.
	300	*
	301	* - start - virtual start address
	302	* - end - virtual end address
	303	*/
	304	ENTRY(arm926_dma_flush_range)
	305	bic r0, r0, #CACHE_DLINESIZE - 1
	306	1:
	307	#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
	308	mcr p15, 0, r0, c7, c14, 1 @ clean+invalidate D entry
	309	#else
b3a8b751	310	mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
1da177e4 LT	311	#endif
	312	add r0, r0, #CACHE_DLINESIZE
	313	cmp r0, r1
	314	blo 1b
	315	mcr p15, 0, r0, c7, c10, 4 @ drain WB
6ebbf2ce	316	ret lr
1da177e4	317
a9c9147e RK	318	/*
	319	* dma_map_area(start, size, dir)
	320	* - start - kernel virtual start address
	321	* - size - size of region
	322	* - dir - DMA direction
	323	*/
	324	ENTRY(arm926_dma_map_area)
	325	add r1, r1, r0
	326	cmp r2, #DMA_TO_DEVICE
	327	beq arm926_dma_clean_range
	328	bcs arm926_dma_inv_range
	329	b arm926_dma_flush_range
	330	ENDPROC(arm926_dma_map_area)
	331
	332	/*
	333	* dma_unmap_area(start, size, dir)
	334	* - start - kernel virtual start address
	335	* - size - size of region
	336	* - dir - DMA direction
	337	*/
	338	ENTRY(arm926_dma_unmap_area)
6ebbf2ce	339	ret lr
a9c9147e RK	340	ENDPROC(arm926_dma_unmap_area)
a9c9147e RK	341
031bd879 LP	342	.globl arm926_flush_kern_cache_louis
	343	.equ arm926_flush_kern_cache_louis, arm926_flush_kern_cache_all
	344
be90da45 DM	345	@ define struct cpu_cache_fns (see <asm/cacheflush.h> and proc-macros.S)
be90da45 DM	346	define_cache_functions arm926
1da177e4 LT	347
	348	ENTRY(cpu_arm926_dcache_clean_area)
	349	#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
	350	1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry
	351	add r0, r0, #CACHE_DLINESIZE
	352	subs r1, r1, #CACHE_DLINESIZE
	353	bhi 1b
	354	#endif
	355	mcr p15, 0, r0, c7, c10, 4 @ drain WB
6ebbf2ce	356	ret lr
1da177e4 LT	357
	358	/* =============================== PageTable ============================== */
	359
	360	/*
	361	* cpu_arm926_switch_mm(pgd)
	362	*
	363	* Set the translation base pointer to be as described by pgd.
	364	*
	365	* pgd: new page tables
	366	*/
	367	.align 5
	368	ENTRY(cpu_arm926_switch_mm)
d090ddda	369	#ifdef CONFIG_MMU
1da177e4 LT	370	mov ip, #0
	371	#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
	372	mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
	373	#else
	374	@ && 'Clean & Invalidate whole DCache'
	375	1: mrc p15, 0, r15, c7, c14, 3 @ test,clean,invalidate
	376	bne 1b
	377	#endif
	378	mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache
	379	mcr p15, 0, ip, c7, c10, 4 @ drain WB
	380	mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
	381	mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs
d090ddda	382	#endif
6ebbf2ce	383	ret lr
1da177e4 LT	384
1da177e4 LT	385	/*
ad1ae2fe	386	* cpu_arm926_set_pte_ext(ptep, pte, ext)
1da177e4 LT	387	*
	388	* Set a PTE and flush it out
	389	*/
	390	.align 5
ad1ae2fe	391	ENTRY(cpu_arm926_set_pte_ext)
d090ddda	392	#ifdef CONFIG_MMU
da091653	393	armv3_set_pte_ext
1da177e4 LT	394	mov r0, r0
	395	#ifndef CONFIG_CPU_DCACHE_WRITETHROUGH
	396	mcr p15, 0, r0, c7, c10, 1 @ clean D entry
	397	#endif
	398	mcr p15, 0, r0, c7, c10, 4 @ drain WB
d090ddda	399	#endif
6ebbf2ce	400	ret lr
1da177e4	401
f6b0fa02 RK	402	/* Suspend/resume support: taken from arch/arm/plat-s3c24xx/sleep.S */
f6b0fa02 RK	403	.globl cpu_arm926_suspend_size
de8e71ca	404	.equ cpu_arm926_suspend_size, 4 * 3
b6c7aabd	405	#ifdef CONFIG_ARM_CPU_SUSPEND
f6b0fa02	406	ENTRY(cpu_arm926_do_suspend)
de8e71ca	407	stmfd sp!, {r4 - r6, lr}
f6b0fa02 RK	408	mrc p15, 0, r4, c13, c0, 0 @ PID
f6b0fa02 RK	409	mrc p15, 0, r5, c3, c0, 0 @ Domain ID
de8e71ca RK	410	mrc p15, 0, r6, c1, c0, 0 @ Control register
	411	stmia r0, {r4 - r6}
	412	ldmfd sp!, {r4 - r6, pc}
f6b0fa02 RK	413	ENDPROC(cpu_arm926_do_suspend)
	414
	415	ENTRY(cpu_arm926_do_resume)
	416	mov ip, #0
	417	mcr p15, 0, ip, c8, c7, 0 @ invalidate I+D TLBs
	418	mcr p15, 0, ip, c7, c7, 0 @ invalidate I+D caches
de8e71ca	419	ldmia r0, {r4 - r6}
f6b0fa02 RK	420	mcr p15, 0, r4, c13, c0, 0 @ PID
f6b0fa02 RK	421	mcr p15, 0, r5, c3, c0, 0 @ Domain ID
de8e71ca RK	422	mcr p15, 0, r1, c2, c0, 0 @ TTB address
de8e71ca RK	423	mov r0, r6 @ control register
f6b0fa02 RK	424	b cpu_resume_mmu
f6b0fa02 RK	425	ENDPROC(cpu_arm926_do_resume)
f6b0fa02 RK	426	#endif
f6b0fa02 RK	427
1da177e4 LT	428	.type __arm926_setup, #function
	429	__arm926_setup:
	430	mov r0, #0
	431	mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4
	432	mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4
d090ddda	433	#ifdef CONFIG_MMU
1da177e4	434	mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4
d090ddda	435	#endif
1da177e4 LT	436
	437
	438	#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
	439	mov r0, #4 @ disable write-back on caches explicitly
	440	mcr p15, 7, r0, c15, c0, 0
	441	#endif
	442
22b19086 RK	443	adr r5, arm926_crval
22b19086 RK	444	ldmia r5, {r5, r6}
1da177e4	445	mrc p15, 0, r0, c1, c0 @ get control register v4
1da177e4	446	bic r0, r0, r5
22b19086	447	orr r0, r0, r6
1da177e4 LT	448	#ifdef CONFIG_CPU_CACHE_ROUND_ROBIN
	449	orr r0, r0, #0x4000 @ .1.. .... .... ....
	450	#endif
6ebbf2ce	451	ret lr
1da177e4 LT	452	.size __arm926_setup, . - __arm926_setup
	453
	454	/*
	455	* R
	456	* .RVI ZFRS BLDP WCAM
	457	* .011 0001 ..11 0101
	458	*
	459	*/
22b19086 RK	460	.type arm926_crval, #object
	461	arm926_crval:
	462	crval clear=0x00007f3f, mmuset=0x00003135, ucset=0x00001134
1da177e4 LT	463
	464	__INITDATA
	465
be90da45 DM	466	@ define struct processor (see <asm/proc-fns.h> and proc-macros.S)
be90da45 DM	467	define_processor_functions arm926, dabort=v5tj_early_abort, pabort=legacy_pabort, suspend=1
1da177e4 LT	468
	469	.section ".rodata"
	470
be90da45 DM	471	string cpu_arch_name, "armv5tej"
	472	string cpu_elf_name, "v5"
	473	string cpu_arm926_name, "ARM926EJ-S"
1da177e4 LT	474
	475	.align
	476
bf35706f	477	.section ".proc.info.init", #alloc
1da177e4 LT	478
	479	.type __arm926_proc_info,#object
	480	__arm926_proc_info:
	481	.long 0x41069260 @ ARM926EJ-S (v5TEJ)
	482	.long 0xff0ffff0
	483	.long PMD_TYPE_SECT \| \
	484	PMD_SECT_BUFFERABLE \| \
	485	PMD_SECT_CACHEABLE \| \
	486	PMD_BIT4 \| \
	487	PMD_SECT_AP_WRITE \| \
	488	PMD_SECT_AP_READ
8799ee9f RK	489	.long PMD_TYPE_SECT \| \
	490	PMD_BIT4 \| \
	491	PMD_SECT_AP_WRITE \| \
	492	PMD_SECT_AP_READ
bf35706f	493	initfn __arm926_setup, __arm926_proc_info
1da177e4 LT	494	.long cpu_arch_name
1da177e4 LT	495	.long cpu_elf_name
efe90d27	496	.long HWCAP_SWP\|HWCAP_HALF\|HWCAP_THUMB\|HWCAP_FAST_MULT\|HWCAP_EDSP\|HWCAP_JAVA
1da177e4 LT	497	.long cpu_arm926_name
	498	.long arm926_processor_functions
	499	.long v4wbi_tlb_fns
	500	.long v4wb_user_fns
	501	.long arm926_cache_fns
	502	.size __arm926_proc_info, . - __arm926_proc_info