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1 | /* |
2 | * linux/arch/arm/mm/proc-sa110.S | |
3 | * | |
4 | * Copyright (C) 1997-2002 Russell King | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License version 2 as | |
8 | * published by the Free Software Foundation. | |
9 | * | |
10 | * MMU functions for SA110 | |
11 | * | |
12 | * These are the low level assembler for performing cache and TLB | |
13 | * functions on the StrongARM-110. | |
14 | */ | |
15 | #include <linux/linkage.h> | |
16 | #include <linux/init.h> | |
17 | #include <asm/assembler.h> | |
e6ae744d | 18 | #include <asm/asm-offsets.h> |
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19 | #include <asm/procinfo.h> |
20 | #include <asm/hardware.h> | |
74945c86 | 21 | #include <asm/pgtable-hwdef.h> |
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22 | #include <asm/pgtable.h> |
23 | #include <asm/ptrace.h> | |
24 | ||
25 | /* | |
26 | * the cache line size of the I and D cache | |
27 | */ | |
28 | #define DCACHELINESIZE 32 | |
95f3df6b | 29 | |
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30 | .text |
31 | ||
32 | /* | |
33 | * cpu_sa110_proc_init() | |
34 | */ | |
35 | ENTRY(cpu_sa110_proc_init) | |
36 | mov r0, #0 | |
37 | mcr p15, 0, r0, c15, c1, 2 @ Enable clock switching | |
38 | mov pc, lr | |
39 | ||
40 | /* | |
41 | * cpu_sa110_proc_fin() | |
42 | */ | |
43 | ENTRY(cpu_sa110_proc_fin) | |
44 | stmfd sp!, {lr} | |
45 | mov ip, #PSR_F_BIT | PSR_I_BIT | SVC_MODE | |
46 | msr cpsr_c, ip | |
47 | bl v4wb_flush_kern_cache_all @ clean caches | |
48 | 1: mov r0, #0 | |
49 | mcr p15, 0, r0, c15, c2, 2 @ Disable clock switching | |
50 | mrc p15, 0, r0, c1, c0, 0 @ ctrl register | |
51 | bic r0, r0, #0x1000 @ ...i............ | |
52 | bic r0, r0, #0x000e @ ............wca. | |
53 | mcr p15, 0, r0, c1, c0, 0 @ disable caches | |
54 | ldmfd sp!, {pc} | |
55 | ||
56 | /* | |
57 | * cpu_sa110_reset(loc) | |
58 | * | |
59 | * Perform a soft reset of the system. Put the CPU into the | |
60 | * same state as it would be if it had been reset, and branch | |
61 | * to what would be the reset vector. | |
62 | * | |
63 | * loc: location to jump to for soft reset | |
64 | */ | |
65 | .align 5 | |
66 | ENTRY(cpu_sa110_reset) | |
67 | mov ip, #0 | |
68 | mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches | |
69 | mcr p15, 0, ip, c7, c10, 4 @ drain WB | |
70 | mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs | |
71 | mrc p15, 0, ip, c1, c0, 0 @ ctrl register | |
72 | bic ip, ip, #0x000f @ ............wcam | |
73 | bic ip, ip, #0x1100 @ ...i...s........ | |
74 | mcr p15, 0, ip, c1, c0, 0 @ ctrl register | |
75 | mov pc, r0 | |
76 | ||
77 | /* | |
78 | * cpu_sa110_do_idle(type) | |
79 | * | |
80 | * Cause the processor to idle | |
81 | * | |
82 | * type: call type: | |
83 | * 0 = slow idle | |
84 | * 1 = fast idle | |
85 | * 2 = switch to slow processor clock | |
86 | * 3 = switch to fast processor clock | |
87 | */ | |
88 | .align 5 | |
89 | ||
90 | ENTRY(cpu_sa110_do_idle) | |
91 | mcr p15, 0, ip, c15, c2, 2 @ disable clock switching | |
92 | ldr r1, =UNCACHEABLE_ADDR @ load from uncacheable loc | |
93 | ldr r1, [r1, #0] @ force switch to MCLK | |
94 | mov r0, r0 @ safety | |
95 | mov r0, r0 @ safety | |
96 | mov r0, r0 @ safety | |
97 | mcr p15, 0, r0, c15, c8, 2 @ Wait for interrupt, cache aligned | |
98 | mov r0, r0 @ safety | |
99 | mov r0, r0 @ safety | |
100 | mov r0, r0 @ safety | |
101 | mcr p15, 0, r0, c15, c1, 2 @ enable clock switching | |
102 | mov pc, lr | |
103 | ||
104 | /* ================================= CACHE ================================ */ | |
105 | ||
106 | /* | |
107 | * cpu_sa110_dcache_clean_area(addr,sz) | |
108 | * | |
109 | * Clean the specified entry of any caches such that the MMU | |
110 | * translation fetches will obtain correct data. | |
111 | * | |
112 | * addr: cache-unaligned virtual address | |
113 | */ | |
114 | .align 5 | |
115 | ENTRY(cpu_sa110_dcache_clean_area) | |
116 | 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry | |
117 | add r0, r0, #DCACHELINESIZE | |
118 | subs r1, r1, #DCACHELINESIZE | |
119 | bhi 1b | |
120 | mov pc, lr | |
121 | ||
122 | /* =============================== PageTable ============================== */ | |
123 | ||
124 | /* | |
125 | * cpu_sa110_switch_mm(pgd) | |
126 | * | |
127 | * Set the translation base pointer to be as described by pgd. | |
128 | * | |
129 | * pgd: new page tables | |
130 | */ | |
131 | .align 5 | |
132 | ENTRY(cpu_sa110_switch_mm) | |
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133 | str lr, [sp, #-4]! |
134 | bl v4wb_flush_kern_cache_all @ clears IP | |
1da177e4 | 135 | mcr p15, 0, r0, c2, c0, 0 @ load page table pointer |
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136 | mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs |
137 | ldr pc, [sp], #4 | |
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138 | |
139 | /* | |
140 | * cpu_sa110_set_pte(ptep, pte) | |
141 | * | |
142 | * Set a PTE and flush it out | |
143 | */ | |
144 | .align 5 | |
145 | ENTRY(cpu_sa110_set_pte) | |
146 | str r1, [r0], #-2048 @ linux version | |
147 | ||
148 | eor r1, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY | |
149 | ||
150 | bic r2, r1, #PTE_SMALL_AP_MASK | |
151 | bic r2, r2, #PTE_TYPE_MASK | |
152 | orr r2, r2, #PTE_TYPE_SMALL | |
153 | ||
154 | tst r1, #L_PTE_USER @ User? | |
155 | orrne r2, r2, #PTE_SMALL_AP_URO_SRW | |
156 | ||
157 | tst r1, #L_PTE_WRITE | L_PTE_DIRTY @ Write and Dirty? | |
158 | orreq r2, r2, #PTE_SMALL_AP_UNO_SRW | |
159 | ||
160 | tst r1, #L_PTE_PRESENT | L_PTE_YOUNG @ Present and Young? | |
161 | movne r2, #0 | |
162 | ||
163 | str r2, [r0] @ hardware version | |
164 | mov r0, r0 | |
165 | mcr p15, 0, r0, c7, c10, 1 @ clean D entry | |
166 | mcr p15, 0, r0, c7, c10, 4 @ drain WB | |
167 | mov pc, lr | |
168 | ||
169 | __INIT | |
170 | ||
171 | .type __sa110_setup, #function | |
172 | __sa110_setup: | |
173 | mov r10, #0 | |
174 | mcr p15, 0, r10, c7, c7 @ invalidate I,D caches on v4 | |
175 | mcr p15, 0, r10, c7, c10, 4 @ drain write buffer on v4 | |
176 | mcr p15, 0, r10, c8, c7 @ invalidate I,D TLBs on v4 | |
177 | mrc p15, 0, r0, c1, c0 @ get control register v4 | |
178 | ldr r5, sa110_cr1_clear | |
179 | bic r0, r0, r5 | |
180 | ldr r5, sa110_cr1_set | |
181 | orr r0, r0, r5 | |
182 | mov pc, lr | |
183 | .size __sa110_setup, . - __sa110_setup | |
184 | ||
185 | /* | |
186 | * R | |
187 | * .RVI ZFRS BLDP WCAM | |
188 | * ..01 0001 ..11 1101 | |
189 | * | |
190 | */ | |
191 | .type sa110_cr1_clear, #object | |
192 | .type sa110_cr1_set, #object | |
193 | sa110_cr1_clear: | |
194 | .word 0x3f3f | |
195 | sa110_cr1_set: | |
196 | .word 0x113d | |
197 | ||
198 | __INITDATA | |
199 | ||
200 | /* | |
201 | * Purpose : Function pointers used to access above functions - all calls | |
202 | * come through these | |
203 | */ | |
204 | ||
205 | .type sa110_processor_functions, #object | |
206 | ENTRY(sa110_processor_functions) | |
207 | .word v4_early_abort | |
208 | .word cpu_sa110_proc_init | |
209 | .word cpu_sa110_proc_fin | |
210 | .word cpu_sa110_reset | |
211 | .word cpu_sa110_do_idle | |
212 | .word cpu_sa110_dcache_clean_area | |
213 | .word cpu_sa110_switch_mm | |
214 | .word cpu_sa110_set_pte | |
215 | .size sa110_processor_functions, . - sa110_processor_functions | |
216 | ||
217 | .section ".rodata" | |
218 | ||
219 | .type cpu_arch_name, #object | |
220 | cpu_arch_name: | |
221 | .asciz "armv4" | |
222 | .size cpu_arch_name, . - cpu_arch_name | |
223 | ||
224 | .type cpu_elf_name, #object | |
225 | cpu_elf_name: | |
226 | .asciz "v4" | |
227 | .size cpu_elf_name, . - cpu_elf_name | |
228 | ||
229 | .type cpu_sa110_name, #object | |
230 | cpu_sa110_name: | |
231 | .asciz "StrongARM-110" | |
232 | .size cpu_sa110_name, . - cpu_sa110_name | |
233 | ||
234 | .align | |
235 | ||
02b7dd12 | 236 | .section ".proc.info.init", #alloc, #execinstr |
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237 | |
238 | .type __sa110_proc_info,#object | |
239 | __sa110_proc_info: | |
240 | .long 0x4401a100 | |
241 | .long 0xfffffff0 | |
242 | .long PMD_TYPE_SECT | \ | |
243 | PMD_SECT_BUFFERABLE | \ | |
244 | PMD_SECT_CACHEABLE | \ | |
245 | PMD_SECT_AP_WRITE | \ | |
246 | PMD_SECT_AP_READ | |
247 | b __sa110_setup | |
248 | .long cpu_arch_name | |
249 | .long cpu_elf_name | |
250 | .long HWCAP_SWP | HWCAP_HALF | HWCAP_26BIT | HWCAP_FAST_MULT | |
251 | .long cpu_sa110_name | |
252 | .long sa110_processor_functions | |
253 | .long v4wb_tlb_fns | |
254 | .long v4wb_user_fns | |
255 | .long v4wb_cache_fns | |
256 | .size __sa110_proc_info, . - __sa110_proc_info |