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1da177e4 LT |
1 | /* |
2 | * linux/arch/arm/mm/proc-v6.S | |
3 | * | |
4 | * Copyright (C) 2001 Deep Blue Solutions Ltd. | |
d090ddda | 5 | * Modified by Catalin Marinas for noMMU support |
1da177e4 LT |
6 | * |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | * | |
11 | * This is the "shell" of the ARMv6 processor support. | |
12 | */ | |
991da17e | 13 | #include <linux/init.h> |
1da177e4 LT |
14 | #include <linux/linkage.h> |
15 | #include <asm/assembler.h> | |
e6ae744d | 16 | #include <asm/asm-offsets.h> |
5ec9407d | 17 | #include <asm/hwcap.h> |
74945c86 | 18 | #include <asm/pgtable-hwdef.h> |
1da177e4 LT |
19 | #include <asm/pgtable.h> |
20 | ||
21 | #include "proc-macros.S" | |
22 | ||
23 | #define D_CACHE_LINE_SIZE 32 | |
24 | ||
3747b36e RK |
25 | #define TTB_C (1 << 0) |
26 | #define TTB_S (1 << 1) | |
27 | #define TTB_IMP (1 << 2) | |
28 | #define TTB_RGN_NC (0 << 3) | |
29 | #define TTB_RGN_WBWA (1 << 3) | |
30 | #define TTB_RGN_WT (2 << 3) | |
31 | #define TTB_RGN_WB (3 << 3) | |
32 | ||
f00ec48f RK |
33 | #define TTB_FLAGS_UP TTB_RGN_WBWA |
34 | #define PMD_FLAGS_UP PMD_SECT_WB | |
35 | #define TTB_FLAGS_SMP TTB_RGN_WBWA|TTB_S | |
36 | #define PMD_FLAGS_SMP PMD_SECT_WBWA|PMD_SECT_S | |
f2131d34 | 37 | |
1da177e4 LT |
38 | ENTRY(cpu_v6_proc_init) |
39 | mov pc, lr | |
40 | ||
41 | ENTRY(cpu_v6_proc_fin) | |
67c5587a TL |
42 | mrc p15, 0, r0, c1, c0, 0 @ ctrl register |
43 | bic r0, r0, #0x1000 @ ...i............ | |
44 | bic r0, r0, #0x0006 @ .............ca. | |
45 | mcr p15, 0, r0, c1, c0, 0 @ disable caches | |
9ca03a21 | 46 | mov pc, lr |
1da177e4 LT |
47 | |
48 | /* | |
49 | * cpu_v6_reset(loc) | |
50 | * | |
51 | * Perform a soft reset of the system. Put the CPU into the | |
52 | * same state as it would be if it had been reset, and branch | |
53 | * to what would be the reset vector. | |
54 | * | |
55 | * - loc - location to jump to for soft reset | |
1da177e4 LT |
56 | */ |
57 | .align 5 | |
1a4baafa | 58 | .pushsection .idmap.text, "ax" |
1da177e4 | 59 | ENTRY(cpu_v6_reset) |
f4daf06f WD |
60 | mrc p15, 0, r1, c1, c0, 0 @ ctrl register |
61 | bic r1, r1, #0x1 @ ...............m | |
62 | mcr p15, 0, r1, c1, c0, 0 @ disable MMU | |
63 | mov r1, #0 | |
64 | mcr p15, 0, r1, c7, c5, 4 @ ISB | |
1da177e4 | 65 | mov pc, r0 |
1a4baafa WD |
66 | ENDPROC(cpu_v6_reset) |
67 | .popsection | |
1da177e4 LT |
68 | |
69 | /* | |
70 | * cpu_v6_do_idle() | |
71 | * | |
72 | * Idle the processor (eg, wait for interrupt). | |
73 | * | |
74 | * IRQs are already disabled. | |
75 | */ | |
76 | ENTRY(cpu_v6_do_idle) | |
8553cb67 CM |
77 | mov r1, #0 |
78 | mcr p15, 0, r1, c7, c10, 4 @ DWB - WFI may enter a low-power mode | |
1da177e4 LT |
79 | mcr p15, 0, r1, c7, c0, 4 @ wait for interrupt |
80 | mov pc, lr | |
81 | ||
82 | ENTRY(cpu_v6_dcache_clean_area) | |
83 | #ifndef TLB_CAN_READ_FROM_L1_CACHE | |
84 | 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry | |
85 | add r0, r0, #D_CACHE_LINE_SIZE | |
86 | subs r1, r1, #D_CACHE_LINE_SIZE | |
87 | bhi 1b | |
88 | #endif | |
89 | mov pc, lr | |
90 | ||
91 | /* | |
92 | * cpu_arm926_switch_mm(pgd_phys, tsk) | |
93 | * | |
94 | * Set the translation table base pointer to be pgd_phys | |
95 | * | |
96 | * - pgd_phys - physical address of new TTB | |
97 | * | |
98 | * It is assumed that: | |
99 | * - we are not using split page tables | |
100 | */ | |
101 | ENTRY(cpu_v6_switch_mm) | |
d090ddda | 102 | #ifdef CONFIG_MMU |
1da177e4 LT |
103 | mov r2, #0 |
104 | ldr r1, [r1, #MM_CONTEXT_ID] @ get mm->context.id | |
f00ec48f RK |
105 | ALT_SMP(orr r0, r0, #TTB_FLAGS_SMP) |
106 | ALT_UP(orr r0, r0, #TTB_FLAGS_UP) | |
d93742f5 | 107 | mcr p15, 0, r2, c7, c5, 6 @ flush BTAC/BTB |
1da177e4 LT |
108 | mcr p15, 0, r2, c7, c10, 4 @ drain write buffer |
109 | mcr p15, 0, r0, c2, c0, 0 @ set TTB 0 | |
110 | mcr p15, 0, r1, c13, c0, 1 @ set context ID | |
d090ddda | 111 | #endif |
1da177e4 LT |
112 | mov pc, lr |
113 | ||
1da177e4 | 114 | /* |
ad1ae2fe | 115 | * cpu_v6_set_pte_ext(ptep, pte, ext) |
1da177e4 LT |
116 | * |
117 | * Set a level 2 translation table entry. | |
118 | * | |
119 | * - ptep - pointer to level 2 translation table entry | |
120 | * (hardware version is stored at -1024 bytes) | |
121 | * - pte - PTE value to store | |
ad1ae2fe | 122 | * - ext - value for extended PTE bits |
1da177e4 | 123 | */ |
639b0ae7 RK |
124 | armv6_mt_table cpu_v6 |
125 | ||
ad1ae2fe | 126 | ENTRY(cpu_v6_set_pte_ext) |
d090ddda | 127 | #ifdef CONFIG_MMU |
639b0ae7 | 128 | armv6_set_pte_ext cpu_v6 |
d090ddda | 129 | #endif |
1da177e4 LT |
130 | mov pc, lr |
131 | ||
f6b0fa02 RK |
132 | /* Suspend/resume support: taken from arch/arm/mach-s3c64xx/sleep.S */ |
133 | .globl cpu_v6_suspend_size | |
1aede681 | 134 | .equ cpu_v6_suspend_size, 4 * 6 |
29ea23ff | 135 | #ifdef CONFIG_PM_SLEEP |
f6b0fa02 | 136 | ENTRY(cpu_v6_do_suspend) |
1aede681 | 137 | stmfd sp!, {r4 - r9, lr} |
f6b0fa02 | 138 | mrc p15, 0, r4, c13, c0, 0 @ FCSE/PID |
1aede681 RK |
139 | mrc p15, 0, r5, c3, c0, 0 @ Domain ID |
140 | mrc p15, 0, r6, c2, c0, 1 @ Translation table base 1 | |
141 | mrc p15, 0, r7, c1, c0, 1 @ auxiliary control register | |
142 | mrc p15, 0, r8, c1, c0, 2 @ co-processor access control | |
143 | mrc p15, 0, r9, c1, c0, 0 @ control register | |
144 | stmia r0, {r4 - r9} | |
145 | ldmfd sp!, {r4- r9, pc} | |
f6b0fa02 RK |
146 | ENDPROC(cpu_v6_do_suspend) |
147 | ||
148 | ENTRY(cpu_v6_do_resume) | |
149 | mov ip, #0 | |
150 | mcr p15, 0, ip, c7, c14, 0 @ clean+invalidate D cache | |
151 | mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache | |
152 | mcr p15, 0, ip, c7, c15, 0 @ clean+invalidate cache | |
153 | mcr p15, 0, ip, c7, c10, 4 @ drain write buffer | |
1aede681 RK |
154 | mcr p15, 0, ip, c13, c0, 1 @ set reserved context ID |
155 | ldmia r0, {r4 - r9} | |
f6b0fa02 | 156 | mcr p15, 0, r4, c13, c0, 0 @ FCSE/PID |
1aede681 | 157 | mcr p15, 0, r5, c3, c0, 0 @ Domain ID |
de8e71ca RK |
158 | ALT_SMP(orr r1, r1, #TTB_FLAGS_SMP) |
159 | ALT_UP(orr r1, r1, #TTB_FLAGS_UP) | |
160 | mcr p15, 0, r1, c2, c0, 0 @ Translation table base 0 | |
1aede681 RK |
161 | mcr p15, 0, r6, c2, c0, 1 @ Translation table base 1 |
162 | mcr p15, 0, r7, c1, c0, 1 @ auxiliary control register | |
163 | mcr p15, 0, r8, c1, c0, 2 @ co-processor access control | |
f6b0fa02 RK |
164 | mcr p15, 0, ip, c2, c0, 2 @ TTB control register |
165 | mcr p15, 0, ip, c7, c5, 4 @ ISB | |
1aede681 | 166 | mov r0, r9 @ control register |
f6b0fa02 RK |
167 | b cpu_resume_mmu |
168 | ENDPROC(cpu_v6_do_resume) | |
f6b0fa02 | 169 | #endif |
1da177e4 | 170 | |
7b7dc6e8 | 171 | string cpu_v6_name, "ARMv6-compatible processor" |
edabd38e | 172 | |
1da177e4 LT |
173 | .align |
174 | ||
5085f3ff | 175 | __CPUINIT |
1da177e4 LT |
176 | |
177 | /* | |
178 | * __v6_setup | |
179 | * | |
180 | * Initialise TLB, Caches, and MMU state ready to switch the MMU | |
181 | * on. Return in r0 the new CP15 C1 control register setting. | |
182 | * | |
183 | * We automatically detect if we have a Harvard cache, and use the | |
184 | * Harvard cache control instructions insead of the unified cache | |
185 | * control instructions. | |
186 | * | |
187 | * This should be able to cover all ARMv6 cores. | |
188 | * | |
189 | * It is assumed that: | |
190 | * - cache type register is implemented | |
191 | */ | |
192 | __v6_setup: | |
862184fe | 193 | #ifdef CONFIG_SMP |
f00ec48f RK |
194 | ALT_SMP(mrc p15, 0, r0, c1, c0, 1) @ Enable SMP/nAMP mode |
195 | ALT_UP(nop) | |
862184fe | 196 | orr r0, r0, #0x20 |
f00ec48f RK |
197 | ALT_SMP(mcr p15, 0, r0, c1, c0, 1) |
198 | ALT_UP(nop) | |
862184fe RK |
199 | #endif |
200 | ||
1da177e4 LT |
201 | mov r0, #0 |
202 | mcr p15, 0, r0, c7, c14, 0 @ clean+invalidate D cache | |
203 | mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache | |
204 | mcr p15, 0, r0, c7, c15, 0 @ clean+invalidate cache | |
205 | mcr p15, 0, r0, c7, c10, 4 @ drain write buffer | |
d090ddda | 206 | #ifdef CONFIG_MMU |
1da177e4 LT |
207 | mcr p15, 0, r0, c8, c7, 0 @ invalidate I + D TLBs |
208 | mcr p15, 0, r0, c2, c0, 2 @ TTB control register | |
f00ec48f RK |
209 | ALT_SMP(orr r4, r4, #TTB_FLAGS_SMP) |
210 | ALT_UP(orr r4, r4, #TTB_FLAGS_UP) | |
d427958a CM |
211 | ALT_SMP(orr r8, r8, #TTB_FLAGS_SMP) |
212 | ALT_UP(orr r8, r8, #TTB_FLAGS_UP) | |
213 | mcr p15, 0, r8, c2, c0, 1 @ load TTB1 | |
d090ddda | 214 | #endif /* CONFIG_MMU */ |
22b19086 RK |
215 | adr r5, v6_crval |
216 | ldmia r5, {r5, r6} | |
26584853 CM |
217 | #ifdef CONFIG_CPU_ENDIAN_BE8 |
218 | orr r6, r6, #1 << 25 @ big-endian page tables | |
219 | #endif | |
1da177e4 | 220 | mrc p15, 0, r0, c1, c0, 0 @ read control register |
1da177e4 | 221 | bic r0, r0, r5 @ clear bits them |
22b19086 | 222 | orr r0, r0, r6 @ set them |
145e10e1 CM |
223 | #ifdef CONFIG_ARM_ERRATA_364296 |
224 | /* | |
225 | * Workaround for the 364296 ARM1136 r0p2 erratum (possible cache data | |
226 | * corruption with hit-under-miss enabled). The conditional code below | |
227 | * (setting the undocumented bit 31 in the auxiliary control register | |
228 | * and the FI bit in the control register) disables hit-under-miss | |
229 | * without putting the processor into full low interrupt latency mode. | |
230 | */ | |
231 | ldr r6, =0x4107b362 @ id for ARM1136 r0p2 | |
232 | mrc p15, 0, r5, c0, c0, 0 @ get processor id | |
233 | teq r5, r6 @ check for the faulty core | |
234 | mrceq p15, 0, r5, c1, c0, 1 @ load aux control reg | |
235 | orreq r5, r5, #(1 << 31) @ set the undocumented bit 31 | |
236 | mcreq p15, 0, r5, c1, c0, 1 @ write aux control reg | |
237 | orreq r0, r0, #(1 << 21) @ low interrupt latency configuration | |
238 | #endif | |
1da177e4 LT |
239 | mov pc, lr @ return to head.S:__ret |
240 | ||
241 | /* | |
242 | * V X F I D LR | |
243 | * .... ...E PUI. .T.T 4RVI ZFRS BLDP WCAM | |
244 | * rrrr rrrx xxx0 0101 xxxx xxxx x111 xxxx < forced | |
245 | * 0 110 0011 1.00 .111 1101 < we want | |
246 | */ | |
22b19086 RK |
247 | .type v6_crval, #object |
248 | v6_crval: | |
249 | crval clear=0x01e0fb7f, mmuset=0x00c0387d, ucset=0x00c0187c | |
1da177e4 | 250 | |
5085f3ff RK |
251 | __INITDATA |
252 | ||
7b7dc6e8 DM |
253 | @ define struct processor (see <asm/proc-fns.h> and proc-macros.S) |
254 | define_processor_functions v6, dabort=v6_early_abort, pabort=v6_pabort, suspend=1 | |
1da177e4 | 255 | |
5085f3ff RK |
256 | .section ".rodata" |
257 | ||
7b7dc6e8 DM |
258 | string cpu_arch_name, "armv6" |
259 | string cpu_elf_name, "v6" | |
1da177e4 LT |
260 | .align |
261 | ||
02b7dd12 | 262 | .section ".proc.info.init", #alloc, #execinstr |
1da177e4 LT |
263 | |
264 | /* | |
265 | * Match any ARMv6 processor core. | |
266 | */ | |
267 | .type __v6_proc_info, #object | |
268 | __v6_proc_info: | |
269 | .long 0x0007b000 | |
270 | .long 0x0007f000 | |
f00ec48f RK |
271 | ALT_SMP(.long \ |
272 | PMD_TYPE_SECT | \ | |
273 | PMD_SECT_AP_WRITE | \ | |
274 | PMD_SECT_AP_READ | \ | |
275 | PMD_FLAGS_SMP) | |
276 | ALT_UP(.long \ | |
277 | PMD_TYPE_SECT | \ | |
1da177e4 | 278 | PMD_SECT_AP_WRITE | \ |
4b46d641 | 279 | PMD_SECT_AP_READ | \ |
f00ec48f | 280 | PMD_FLAGS_UP) |
8799ee9f RK |
281 | .long PMD_TYPE_SECT | \ |
282 | PMD_SECT_XN | \ | |
283 | PMD_SECT_AP_WRITE | \ | |
284 | PMD_SECT_AP_READ | |
1da177e4 LT |
285 | b __v6_setup |
286 | .long cpu_arch_name | |
287 | .long cpu_elf_name | |
f159f4ed TL |
288 | /* See also feat_v6_fixup() for HWCAP_TLS */ |
289 | .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP|HWCAP_JAVA|HWCAP_TLS | |
1da177e4 LT |
290 | .long cpu_v6_name |
291 | .long v6_processor_functions | |
292 | .long v6wbi_tlb_fns | |
293 | .long v6_user_fns | |
294 | .long v6_cache_fns | |
295 | .size __v6_proc_info, . - __v6_proc_info |