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1da177e4 LT |
1 | /* |
2 | * linux/arch/arm/mm/proc-v6.S | |
3 | * | |
4 | * Copyright (C) 2001 Deep Blue Solutions Ltd. | |
d090ddda | 5 | * Modified by Catalin Marinas for noMMU support |
1da177e4 LT |
6 | * |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | * | |
11 | * This is the "shell" of the ARMv6 processor support. | |
12 | */ | |
991da17e | 13 | #include <linux/init.h> |
1da177e4 LT |
14 | #include <linux/linkage.h> |
15 | #include <asm/assembler.h> | |
e6ae744d | 16 | #include <asm/asm-offsets.h> |
5ec9407d | 17 | #include <asm/hwcap.h> |
74945c86 | 18 | #include <asm/pgtable-hwdef.h> |
1da177e4 LT |
19 | #include <asm/pgtable.h> |
20 | ||
21 | #include "proc-macros.S" | |
22 | ||
23 | #define D_CACHE_LINE_SIZE 32 | |
24 | ||
3747b36e RK |
25 | #define TTB_C (1 << 0) |
26 | #define TTB_S (1 << 1) | |
27 | #define TTB_IMP (1 << 2) | |
28 | #define TTB_RGN_NC (0 << 3) | |
29 | #define TTB_RGN_WBWA (1 << 3) | |
30 | #define TTB_RGN_WT (2 << 3) | |
31 | #define TTB_RGN_WB (3 << 3) | |
32 | ||
f00ec48f RK |
33 | #define TTB_FLAGS_UP TTB_RGN_WBWA |
34 | #define PMD_FLAGS_UP PMD_SECT_WB | |
35 | #define TTB_FLAGS_SMP TTB_RGN_WBWA|TTB_S | |
36 | #define PMD_FLAGS_SMP PMD_SECT_WBWA|PMD_SECT_S | |
f2131d34 | 37 | |
1da177e4 LT |
38 | ENTRY(cpu_v6_proc_init) |
39 | mov pc, lr | |
40 | ||
41 | ENTRY(cpu_v6_proc_fin) | |
67c5587a TL |
42 | mrc p15, 0, r0, c1, c0, 0 @ ctrl register |
43 | bic r0, r0, #0x1000 @ ...i............ | |
44 | bic r0, r0, #0x0006 @ .............ca. | |
45 | mcr p15, 0, r0, c1, c0, 0 @ disable caches | |
9ca03a21 | 46 | mov pc, lr |
1da177e4 LT |
47 | |
48 | /* | |
49 | * cpu_v6_reset(loc) | |
50 | * | |
51 | * Perform a soft reset of the system. Put the CPU into the | |
52 | * same state as it would be if it had been reset, and branch | |
53 | * to what would be the reset vector. | |
54 | * | |
55 | * - loc - location to jump to for soft reset | |
1da177e4 LT |
56 | */ |
57 | .align 5 | |
58 | ENTRY(cpu_v6_reset) | |
59 | mov pc, r0 | |
60 | ||
61 | /* | |
62 | * cpu_v6_do_idle() | |
63 | * | |
64 | * Idle the processor (eg, wait for interrupt). | |
65 | * | |
66 | * IRQs are already disabled. | |
67 | */ | |
68 | ENTRY(cpu_v6_do_idle) | |
8553cb67 CM |
69 | mov r1, #0 |
70 | mcr p15, 0, r1, c7, c10, 4 @ DWB - WFI may enter a low-power mode | |
1da177e4 LT |
71 | mcr p15, 0, r1, c7, c0, 4 @ wait for interrupt |
72 | mov pc, lr | |
73 | ||
74 | ENTRY(cpu_v6_dcache_clean_area) | |
75 | #ifndef TLB_CAN_READ_FROM_L1_CACHE | |
76 | 1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry | |
77 | add r0, r0, #D_CACHE_LINE_SIZE | |
78 | subs r1, r1, #D_CACHE_LINE_SIZE | |
79 | bhi 1b | |
80 | #endif | |
81 | mov pc, lr | |
82 | ||
83 | /* | |
84 | * cpu_arm926_switch_mm(pgd_phys, tsk) | |
85 | * | |
86 | * Set the translation table base pointer to be pgd_phys | |
87 | * | |
88 | * - pgd_phys - physical address of new TTB | |
89 | * | |
90 | * It is assumed that: | |
91 | * - we are not using split page tables | |
92 | */ | |
93 | ENTRY(cpu_v6_switch_mm) | |
d090ddda | 94 | #ifdef CONFIG_MMU |
1da177e4 LT |
95 | mov r2, #0 |
96 | ldr r1, [r1, #MM_CONTEXT_ID] @ get mm->context.id | |
f00ec48f RK |
97 | ALT_SMP(orr r0, r0, #TTB_FLAGS_SMP) |
98 | ALT_UP(orr r0, r0, #TTB_FLAGS_UP) | |
d93742f5 | 99 | mcr p15, 0, r2, c7, c5, 6 @ flush BTAC/BTB |
1da177e4 LT |
100 | mcr p15, 0, r2, c7, c10, 4 @ drain write buffer |
101 | mcr p15, 0, r0, c2, c0, 0 @ set TTB 0 | |
102 | mcr p15, 0, r1, c13, c0, 1 @ set context ID | |
d090ddda | 103 | #endif |
1da177e4 LT |
104 | mov pc, lr |
105 | ||
1da177e4 | 106 | /* |
ad1ae2fe | 107 | * cpu_v6_set_pte_ext(ptep, pte, ext) |
1da177e4 LT |
108 | * |
109 | * Set a level 2 translation table entry. | |
110 | * | |
111 | * - ptep - pointer to level 2 translation table entry | |
112 | * (hardware version is stored at -1024 bytes) | |
113 | * - pte - PTE value to store | |
ad1ae2fe | 114 | * - ext - value for extended PTE bits |
1da177e4 | 115 | */ |
639b0ae7 RK |
116 | armv6_mt_table cpu_v6 |
117 | ||
ad1ae2fe | 118 | ENTRY(cpu_v6_set_pte_ext) |
d090ddda | 119 | #ifdef CONFIG_MMU |
639b0ae7 | 120 | armv6_set_pte_ext cpu_v6 |
d090ddda | 121 | #endif |
1da177e4 LT |
122 | mov pc, lr |
123 | ||
f6b0fa02 RK |
124 | /* Suspend/resume support: taken from arch/arm/mach-s3c64xx/sleep.S */ |
125 | .globl cpu_v6_suspend_size | |
126 | .equ cpu_v6_suspend_size, 4 * 8 | |
29ea23ff | 127 | #ifdef CONFIG_PM_SLEEP |
f6b0fa02 RK |
128 | ENTRY(cpu_v6_do_suspend) |
129 | stmfd sp!, {r4 - r11, lr} | |
130 | mrc p15, 0, r4, c13, c0, 0 @ FCSE/PID | |
131 | mrc p15, 0, r5, c13, c0, 1 @ Context ID | |
132 | mrc p15, 0, r6, c3, c0, 0 @ Domain ID | |
133 | mrc p15, 0, r7, c2, c0, 0 @ Translation table base 0 | |
134 | mrc p15, 0, r8, c2, c0, 1 @ Translation table base 1 | |
25985edc | 135 | mrc p15, 0, r9, c1, c0, 1 @ auxiliary control register |
f6b0fa02 RK |
136 | mrc p15, 0, r10, c1, c0, 2 @ co-processor access control |
137 | mrc p15, 0, r11, c1, c0, 0 @ control register | |
138 | stmia r0, {r4 - r11} | |
139 | ldmfd sp!, {r4- r11, pc} | |
140 | ENDPROC(cpu_v6_do_suspend) | |
141 | ||
142 | ENTRY(cpu_v6_do_resume) | |
143 | mov ip, #0 | |
144 | mcr p15, 0, ip, c7, c14, 0 @ clean+invalidate D cache | |
145 | mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache | |
146 | mcr p15, 0, ip, c7, c15, 0 @ clean+invalidate cache | |
147 | mcr p15, 0, ip, c7, c10, 4 @ drain write buffer | |
148 | ldmia r0, {r4 - r11} | |
149 | mcr p15, 0, r4, c13, c0, 0 @ FCSE/PID | |
150 | mcr p15, 0, r5, c13, c0, 1 @ Context ID | |
151 | mcr p15, 0, r6, c3, c0, 0 @ Domain ID | |
152 | mcr p15, 0, r7, c2, c0, 0 @ Translation table base 0 | |
153 | mcr p15, 0, r8, c2, c0, 1 @ Translation table base 1 | |
25985edc | 154 | mcr p15, 0, r9, c1, c0, 1 @ auxiliary control register |
f6b0fa02 RK |
155 | mcr p15, 0, r10, c1, c0, 2 @ co-processor access control |
156 | mcr p15, 0, ip, c2, c0, 2 @ TTB control register | |
157 | mcr p15, 0, ip, c7, c5, 4 @ ISB | |
158 | mov r0, r11 @ control register | |
159 | mov r2, r7, lsr #14 @ get TTB0 base | |
160 | mov r2, r2, lsl #14 | |
161 | ldr r3, cpu_resume_l1_flags | |
162 | b cpu_resume_mmu | |
163 | ENDPROC(cpu_v6_do_resume) | |
164 | cpu_resume_l1_flags: | |
165 | ALT_SMP(.long PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_FLAGS_SMP) | |
166 | ALT_UP(.long PMD_TYPE_SECT | PMD_SECT_AP_WRITE | PMD_FLAGS_UP) | |
167 | #else | |
168 | #define cpu_v6_do_suspend 0 | |
169 | #define cpu_v6_do_resume 0 | |
170 | #endif | |
1da177e4 LT |
171 | |
172 | ||
edabd38e | 173 | .type cpu_v6_name, #object |
1da177e4 | 174 | cpu_v6_name: |
94b1e96d | 175 | .asciz "ARMv6-compatible processor" |
edabd38e SB |
176 | .size cpu_v6_name, . - cpu_v6_name |
177 | ||
1da177e4 LT |
178 | .align |
179 | ||
5085f3ff | 180 | __CPUINIT |
1da177e4 LT |
181 | |
182 | /* | |
183 | * __v6_setup | |
184 | * | |
185 | * Initialise TLB, Caches, and MMU state ready to switch the MMU | |
186 | * on. Return in r0 the new CP15 C1 control register setting. | |
187 | * | |
188 | * We automatically detect if we have a Harvard cache, and use the | |
189 | * Harvard cache control instructions insead of the unified cache | |
190 | * control instructions. | |
191 | * | |
192 | * This should be able to cover all ARMv6 cores. | |
193 | * | |
194 | * It is assumed that: | |
195 | * - cache type register is implemented | |
196 | */ | |
197 | __v6_setup: | |
862184fe | 198 | #ifdef CONFIG_SMP |
f00ec48f RK |
199 | ALT_SMP(mrc p15, 0, r0, c1, c0, 1) @ Enable SMP/nAMP mode |
200 | ALT_UP(nop) | |
862184fe | 201 | orr r0, r0, #0x20 |
f00ec48f RK |
202 | ALT_SMP(mcr p15, 0, r0, c1, c0, 1) |
203 | ALT_UP(nop) | |
862184fe RK |
204 | #endif |
205 | ||
1da177e4 LT |
206 | mov r0, #0 |
207 | mcr p15, 0, r0, c7, c14, 0 @ clean+invalidate D cache | |
208 | mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache | |
209 | mcr p15, 0, r0, c7, c15, 0 @ clean+invalidate cache | |
210 | mcr p15, 0, r0, c7, c10, 4 @ drain write buffer | |
d090ddda | 211 | #ifdef CONFIG_MMU |
1da177e4 LT |
212 | mcr p15, 0, r0, c8, c7, 0 @ invalidate I + D TLBs |
213 | mcr p15, 0, r0, c2, c0, 2 @ TTB control register | |
f00ec48f RK |
214 | ALT_SMP(orr r4, r4, #TTB_FLAGS_SMP) |
215 | ALT_UP(orr r4, r4, #TTB_FLAGS_UP) | |
1da177e4 | 216 | mcr p15, 0, r4, c2, c0, 1 @ load TTB1 |
d090ddda | 217 | #endif /* CONFIG_MMU */ |
22b19086 RK |
218 | adr r5, v6_crval |
219 | ldmia r5, {r5, r6} | |
26584853 CM |
220 | #ifdef CONFIG_CPU_ENDIAN_BE8 |
221 | orr r6, r6, #1 << 25 @ big-endian page tables | |
222 | #endif | |
1da177e4 | 223 | mrc p15, 0, r0, c1, c0, 0 @ read control register |
1da177e4 | 224 | bic r0, r0, r5 @ clear bits them |
22b19086 | 225 | orr r0, r0, r6 @ set them |
1da177e4 LT |
226 | mov pc, lr @ return to head.S:__ret |
227 | ||
228 | /* | |
229 | * V X F I D LR | |
230 | * .... ...E PUI. .T.T 4RVI ZFRS BLDP WCAM | |
231 | * rrrr rrrx xxx0 0101 xxxx xxxx x111 xxxx < forced | |
232 | * 0 110 0011 1.00 .111 1101 < we want | |
233 | */ | |
22b19086 RK |
234 | .type v6_crval, #object |
235 | v6_crval: | |
236 | crval clear=0x01e0fb7f, mmuset=0x00c0387d, ucset=0x00c0187c | |
1da177e4 | 237 | |
5085f3ff RK |
238 | __INITDATA |
239 | ||
1da177e4 LT |
240 | .type v6_processor_functions, #object |
241 | ENTRY(v6_processor_functions) | |
242 | .word v6_early_abort | |
4fb28474 | 243 | .word v6_pabort |
1da177e4 LT |
244 | .word cpu_v6_proc_init |
245 | .word cpu_v6_proc_fin | |
246 | .word cpu_v6_reset | |
247 | .word cpu_v6_do_idle | |
248 | .word cpu_v6_dcache_clean_area | |
249 | .word cpu_v6_switch_mm | |
ad1ae2fe | 250 | .word cpu_v6_set_pte_ext |
f6b0fa02 RK |
251 | .word cpu_v6_suspend_size |
252 | .word cpu_v6_do_suspend | |
253 | .word cpu_v6_do_resume | |
1da177e4 LT |
254 | .size v6_processor_functions, . - v6_processor_functions |
255 | ||
5085f3ff RK |
256 | .section ".rodata" |
257 | ||
1da177e4 LT |
258 | .type cpu_arch_name, #object |
259 | cpu_arch_name: | |
260 | .asciz "armv6" | |
261 | .size cpu_arch_name, . - cpu_arch_name | |
262 | ||
263 | .type cpu_elf_name, #object | |
264 | cpu_elf_name: | |
265 | .asciz "v6" | |
266 | .size cpu_elf_name, . - cpu_elf_name | |
267 | .align | |
268 | ||
02b7dd12 | 269 | .section ".proc.info.init", #alloc, #execinstr |
1da177e4 LT |
270 | |
271 | /* | |
272 | * Match any ARMv6 processor core. | |
273 | */ | |
274 | .type __v6_proc_info, #object | |
275 | __v6_proc_info: | |
276 | .long 0x0007b000 | |
277 | .long 0x0007f000 | |
f00ec48f RK |
278 | ALT_SMP(.long \ |
279 | PMD_TYPE_SECT | \ | |
280 | PMD_SECT_AP_WRITE | \ | |
281 | PMD_SECT_AP_READ | \ | |
282 | PMD_FLAGS_SMP) | |
283 | ALT_UP(.long \ | |
284 | PMD_TYPE_SECT | \ | |
1da177e4 | 285 | PMD_SECT_AP_WRITE | \ |
4b46d641 | 286 | PMD_SECT_AP_READ | \ |
f00ec48f | 287 | PMD_FLAGS_UP) |
8799ee9f RK |
288 | .long PMD_TYPE_SECT | \ |
289 | PMD_SECT_XN | \ | |
290 | PMD_SECT_AP_WRITE | \ | |
291 | PMD_SECT_AP_READ | |
1da177e4 LT |
292 | b __v6_setup |
293 | .long cpu_arch_name | |
294 | .long cpu_elf_name | |
f159f4ed TL |
295 | /* See also feat_v6_fixup() for HWCAP_TLS */ |
296 | .long HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP|HWCAP_JAVA|HWCAP_TLS | |
1da177e4 LT |
297 | .long cpu_v6_name |
298 | .long v6_processor_functions | |
299 | .long v6wbi_tlb_fns | |
300 | .long v6_user_fns | |
301 | .long v6_cache_fns | |
302 | .size __v6_proc_info, . - __v6_proc_info |