[deliverable/linux.git] / arch / arm / mm / proc-xsc3.S

/*
 * linux/arch/arm/mm/proc-xsc3.S
 *
 * Original Author: Matthew Gilbert
 * Current Maintainer: Lennert Buytenhek <buytenh@wantstofly.org>
 *
 * Copyright 2004 (C) Intel Corp.
 * Copyright 2005 (C) MontaVista Software, Inc.
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 * MMU functions for the Intel XScale3 Core (XSC3).  The XSC3 core is
 * an extension to Intel's original XScale core that adds the following
 * features:
 *
 * - ARMv6 Supersections
 * - Low Locality Reference pages (replaces mini-cache)
 * - 36-bit addressing
 * - L2 cache
 * - Cache coherency if chipset supports it
 *
 * Based on original XScale code by Nicolas Pitre.
 */

#include <linux/linkage.h>
#include <linux/init.h>
#include <asm/assembler.h>
#include <asm/elf.h>
#include <asm/hardware.h>
#include <asm/pgtable.h>
#include <asm/pgtable-hwdef.h>
#include <asm/page.h>
#include <asm/ptrace.h>
#include "proc-macros.S"

/*
 * This is the maximum size of an area which will be flushed.  If the
 * area is larger than this, then we flush the whole cache.
 */
#define MAX_AREA_SIZE	32768

/*
 * The cache line size of the L1 I, L1 D and unified L2 cache.
 */
#define CACHELINESIZE	32

/*
 * The size of the L1 D cache.
 */
#define CACHESIZE	32768

/*
 * Run with L2 enabled.
 */
#define L2_CACHE_ENABLE	1

/*
 * This macro is used to wait for a CP15 write and is needed when we
 * have to ensure that the last operation to the coprocessor was
 * completed before continuing with operation.
 */
	.macro	cpwait_ret, lr, rd
	mrc	p15, 0, \rd, c2, c0, 0		@ arbitrary read of cp15
	sub	pc, \lr, \rd, LSR #32		@ wait for completion and
						@ flush instruction pipeline
	.endm

/*
 * This macro cleans and invalidates the entire L1 D cache.
 */

 	.macro  clean_d_cache rd, rs
	mov	\rd, #0x1f00
	orr	\rd, \rd, #0x00e0
1:	mcr	p15, 0, \rd, c7, c14, 2		@ clean/invalidate L1 D line
	adds	\rd, \rd, #0x40000000
	bcc	1b
	subs	\rd, \rd, #0x20
	bpl	1b
	.endm

	.text

/*
 * cpu_xsc3_proc_init()
 *
 * Nothing too exciting at the moment
 */
ENTRY(cpu_xsc3_proc_init)
	mov	pc, lr

/*
 * cpu_xsc3_proc_fin()
 */
ENTRY(cpu_xsc3_proc_fin)
	str	lr, [sp, #-4]!
	mov	r0, #PSR_F_BIT|PSR_I_BIT|SVC_MODE
	msr	cpsr_c, r0
	bl	xsc3_flush_kern_cache_all	@ clean caches
	mrc	p15, 0, r0, c1, c0, 0		@ ctrl register
	bic	r0, r0, #0x1800			@ ...IZ...........
	bic	r0, r0, #0x0006			@ .............CA.
	mcr	p15, 0, r0, c1, c0, 0		@ disable caches
	ldr	pc, [sp], #4

/*
 * cpu_xsc3_reset(loc)
 *
 * Perform a soft reset of the system.  Put the CPU into the
 * same state as it would be if it had been reset, and branch
 * to what would be the reset vector.
 *
 * loc: location to jump to for soft reset
 */
	.align	5
ENTRY(cpu_xsc3_reset)
	mov	r1, #PSR_F_BIT|PSR_I_BIT|SVC_MODE
	msr	cpsr_c, r1			@ reset CPSR
	mrc	p15, 0, r1, c1, c0, 0		@ ctrl register
	bic	r1, r1, #0x3900			@ ..VIZ..S........
	bic	r1, r1, #0x0086			@ ........B....CA.
	mcr	p15, 0, r1, c1, c0, 0		@ ctrl register
	mcr	p15, 0, ip, c7, c7, 0		@ invalidate L1 caches and BTB
	bic	r1, r1, #0x0001			@ ...............M
	mcr	p15, 0, r1, c1, c0, 0		@ ctrl register
	@ CAUTION: MMU turned off from this point.  We count on the pipeline
	@ already containing those two last instructions to survive.
	mcr	p15, 0, ip, c8, c7, 0		@ invalidate I and D TLBs
	mov	pc, r0

/*
 * cpu_xsc3_do_idle()
 *
 * Cause the processor to idle
 *
 * For now we do nothing but go to idle mode for every case
 *
 * XScale supports clock switching, but using idle mode support
 * allows external hardware to react to system state changes.
 */
	.align	5

ENTRY(cpu_xsc3_do_idle)
	mov	r0, #1
	mcr	p14, 0, r0, c7, c0, 0		@ go to idle
	mov	pc, lr

/* ================================= CACHE ================================ */

/*
 *	flush_user_cache_all()
 *
 *	Invalidate all cache entries in a particular address
 *	space.
 */
ENTRY(xsc3_flush_user_cache_all)
	/* FALLTHROUGH */

/*
 *	flush_kern_cache_all()
 *
 *	Clean and invalidate the entire cache.
 */
ENTRY(xsc3_flush_kern_cache_all)
	mov	r2, #VM_EXEC
	mov	ip, #0
__flush_whole_cache:
	clean_d_cache r0, r1
	tst	r2, #VM_EXEC
	mcrne	p15, 0, ip, c7, c5, 0		@ invalidate L1 I cache and BTB
	mcrne	p15, 0, ip, c7, c10, 4		@ data write barrier
	mcrne	p15, 0, ip, c7, c5, 4		@ prefetch flush
	mov	pc, lr

/*
 *	flush_user_cache_range(start, end, vm_flags)
 *
 *	Invalidate a range of cache entries in the specified
 *	address space.
 *
 *	- start - start address (may not be aligned)
 *	- end	- end address (exclusive, may not be aligned)
 *	- vma	- vma_area_struct describing address space
 */
	.align	5
ENTRY(xsc3_flush_user_cache_range)
	mov	ip, #0
	sub	r3, r1, r0			@ calculate total size
	cmp	r3, #MAX_AREA_SIZE
	bhs	__flush_whole_cache

1:	tst	r2, #VM_EXEC
	mcrne	p15, 0, r0, c7, c5, 1		@ invalidate L1 I line
	mcr	p15, 0, r0, c7, c14, 1		@ clean/invalidate L1 D line
	add	r0, r0, #CACHELINESIZE
	cmp	r0, r1
	blo	1b
	tst	r2, #VM_EXEC
	mcrne	p15, 0, ip, c7, c5, 6		@ invalidate BTB
	mcrne	p15, 0, ip, c7, c10, 4		@ data write barrier
	mcrne	p15, 0, ip, c7, c5, 4		@ prefetch flush
	mov	pc, lr

/*
 *	coherent_kern_range(start, end)
 *
 *	Ensure coherency between the I cache and the D cache in the
 *	region described by start.  If you have non-snooping
 *	Harvard caches, you need to implement this function.
 *
 *	- start  - virtual start address
 *	- end	 - virtual end address
 *
 *	Note: single I-cache line invalidation isn't used here since
 *	it also trashes the mini I-cache used by JTAG debuggers.
 */
ENTRY(xsc3_coherent_kern_range)
/* FALLTHROUGH */
ENTRY(xsc3_coherent_user_range)
	bic	r0, r0, #CACHELINESIZE - 1
1:	mcr	p15, 0, r0, c7, c10, 1		@ clean L1 D line
	add	r0, r0, #CACHELINESIZE
	cmp	r0, r1
	blo	1b
	mov	r0, #0
	mcr	p15, 0, r0, c7, c5, 0		@ invalidate L1 I cache and BTB
	mcr	p15, 0, r0, c7, c10, 4		@ data write barrier
	mcr	p15, 0, r0, c7, c5, 4		@ prefetch flush
	mov	pc, lr

/*
 *	flush_kern_dcache_page(void *page)
 *
 *	Ensure no D cache aliasing occurs, either with itself or
 *	the I cache.
 *
 *	- addr	- page aligned address
 */
ENTRY(xsc3_flush_kern_dcache_page)
	add	r1, r0, #PAGE_SZ
1:	mcr	p15, 0, r0, c7, c14, 1		@ clean/invalidate L1 D line
	add	r0, r0, #CACHELINESIZE
	cmp	r0, r1
	blo	1b
	mov	r0, #0
	mcr	p15, 0, r0, c7, c5, 0		@ invalidate L1 I cache and BTB
	mcr	p15, 0, r0, c7, c10, 4		@ data write barrier
	mcr	p15, 0, r0, c7, c5, 4		@ prefetch flush
	mov	pc, lr

/*
 *	dma_inv_range(start, end)
 *
 *	Invalidate (discard) the specified virtual address range.
 *	May not write back any entries.  If 'start' or 'end'
 *	are not cache line aligned, those lines must be written
 *	back.
 *
 *	- start  - virtual start address
 *	- end	 - virtual end address
 */
ENTRY(xsc3_dma_inv_range)
	tst	r0, #CACHELINESIZE - 1
	bic	r0, r0, #CACHELINESIZE - 1
	mcrne	p15, 0, r0, c7, c10, 1		@ clean L1 D line
	mcrne	p15, 1, r0, c7, c11, 1		@ clean L2 line
	tst	r1, #CACHELINESIZE - 1
	mcrne	p15, 0, r1, c7, c10, 1		@ clean L1 D line
	mcrne	p15, 1, r1, c7, c11, 1		@ clean L2 line
1:	mcr	p15, 0, r0, c7, c6, 1		@ invalidate L1 D line
	mcr	p15, 1, r0, c7, c7, 1		@ invalidate L2 line
	add	r0, r0, #CACHELINESIZE
	cmp	r0, r1
	blo	1b
	mcr	p15, 0, r0, c7, c10, 4		@ data write barrier
	mov	pc, lr

/*
 *	dma_clean_range(start, end)
 *
 *	Clean the specified virtual address range.
 *
 *	- start  - virtual start address
 *	- end	 - virtual end address
 */
ENTRY(xsc3_dma_clean_range)
	bic	r0, r0, #CACHELINESIZE - 1
1:	mcr	p15, 0, r0, c7, c10, 1		@ clean L1 D line
	mcr	p15, 1, r0, c7, c11, 1		@ clean L2 line
	add	r0, r0, #CACHELINESIZE
	cmp	r0, r1
	blo	1b
	mcr	p15, 0, r0, c7, c10, 4		@ data write barrier
	mov	pc, lr

/*
 *	dma_flush_range(start, end)
 *
 *	Clean and invalidate the specified virtual address range.
 *
 *	- start  - virtual start address
 *	- end	 - virtual end address
 */
ENTRY(xsc3_dma_flush_range)
	bic	r0, r0, #CACHELINESIZE - 1
1:	mcr	p15, 0, r0, c7, c14, 1		@ clean/invalidate L1 D line
	mcr	p15, 1, r0, c7, c11, 1		@ clean L2 line
	mcr	p15, 1, r0, c7, c7, 1		@ invalidate L2 line
	add	r0, r0, #CACHELINESIZE
	cmp	r0, r1
	blo	1b
	mcr	p15, 0, r0, c7, c10, 4		@ data write barrier
	mov	pc, lr

ENTRY(xsc3_cache_fns)
	.long	xsc3_flush_kern_cache_all
	.long	xsc3_flush_user_cache_all
	.long	xsc3_flush_user_cache_range
	.long	xsc3_coherent_kern_range
	.long	xsc3_coherent_user_range
	.long	xsc3_flush_kern_dcache_page
	.long	xsc3_dma_inv_range
	.long	xsc3_dma_clean_range
	.long	xsc3_dma_flush_range

ENTRY(cpu_xsc3_dcache_clean_area)
1:	mcr	p15, 0, r0, c7, c10, 1		@ clean L1 D line
	add	r0, r0, #CACHELINESIZE
	subs	r1, r1, #CACHELINESIZE
	bhi	1b
	mov	pc, lr

/* =============================== PageTable ============================== */

/*
 * cpu_xsc3_switch_mm(pgd)
 *
 * Set the translation base pointer to be as described by pgd.
 *
 * pgd: new page tables
 */
	.align	5
ENTRY(cpu_xsc3_switch_mm)
	clean_d_cache r1, r2
	mcr	p15, 0, ip, c7, c5, 0		@ invalidate L1 I cache and BTB
	mcr	p15, 0, ip, c7, c10, 4		@ data write barrier
	mcr	p15, 0, ip, c7, c5, 4		@ prefetch flush
#ifdef L2_CACHE_ENABLE
	orr	r0, r0, #0x18			@ cache the page table in L2
#endif
	mcr	p15, 0, r0, c2, c0, 0		@ load page table pointer
	mcr	p15, 0, ip, c8, c7, 0		@ invalidate I and D TLBs
	cpwait_ret lr, ip

/*
 * cpu_xsc3_set_pte_ext(ptep, pte, ext)
 *
 * Set a PTE and flush it out
 *
 */
	.align	5
ENTRY(cpu_xsc3_set_pte_ext)
	str	r1, [r0], #-2048		@ linux version

	bic	r2, r1, #0xff0			@ keep C, B bits
	orr	r2, r2, #PTE_TYPE_EXT		@ extended page
	tst	r1, #L_PTE_SHARED		@ shared?
	orrne	r2, r2, #0x200

	eor	r3, r1, #L_PTE_PRESENT | L_PTE_YOUNG | L_PTE_WRITE | L_PTE_DIRTY

	tst	r3, #L_PTE_USER			@ user?
	orrne	r2, r2, #PTE_EXT_AP_URO_SRW	@ yes -> user r/o, system r/w

	tst	r3, #L_PTE_WRITE | L_PTE_DIRTY	@ write and dirty?
	orreq	r2, r2, #PTE_EXT_AP_UNO_SRW	@ yes -> user n/a, system r/w
						@ combined with user -> user r/w

#if L2_CACHE_ENABLE
	@ If it's cacheable, it needs to be in L2 also.
	eor	ip, r1, #L_PTE_CACHEABLE
	tst	ip, #L_PTE_CACHEABLE
	orreq	r2, r2, #PTE_EXT_TEX(0x5)
#endif

	tst	r3, #L_PTE_PRESENT | L_PTE_YOUNG	@ present and young?
	movne	r2, #0				@ no -> fault

	str	r2, [r0]			@ hardware version
	mov	ip, #0
	mcr	p15, 0, r0, c7, c10, 1		@ clean L1 D line
	mcr	p15, 0, ip, c7, c10, 4		@ data write barrier
	mov	pc, lr

	.ltorg

	.align

	__INIT

	.type	__xsc3_setup, #function
__xsc3_setup:
	mov	r0, #PSR_F_BIT|PSR_I_BIT|SVC_MODE
	msr	cpsr_c, r0
	mcr	p15, 0, ip, c7, c7, 0		@ invalidate L1 caches and BTB
	mcr	p15, 0, ip, c7, c10, 4		@ data write barrier
	mcr	p15, 0, ip, c7, c5, 4		@ prefetch flush
	mcr	p15, 0, ip, c8, c7, 0		@ invalidate I and D TLBs
#if L2_CACHE_ENABLE
	orr	r4, r4, #0x18			@ cache the page table in L2
#endif
	mcr	p15, 0, r4, c2, c0, 0		@ load page table pointer

	mov	r0, #0				@ don't allow CP access
	mcr	p15, 0, r0, c15, c1, 0		@ write CP access register

	mrc	p15, 0, r0, c1, c0, 1		@ get auxiliary control reg
	and	r0, r0, #2			@ preserve bit P bit setting
#if L2_CACHE_ENABLE
	orr	r0, r0, #(1 << 10)		@ enable L2 for LLR cache
#endif
	mcr	p15, 0, r0, c1, c0, 1		@ set auxiliary control reg

	adr	r5, xsc3_crval
	ldmia	r5, {r5, r6}
	mrc	p15, 0, r0, c1, c0, 0		@ get control register
	bic	r0, r0, r5			@ ..V. ..R. .... ..A.
	orr	r0, r0, r6			@ ..VI Z..S .... .C.M (mmu)
						@ ...I Z..S .... .... (uc)
#if L2_CACHE_ENABLE
	orr 	r0, r0, #0x04000000		@ L2 enable
#endif
	mov	pc, lr

	.size	__xsc3_setup, . - __xsc3_setup

	.type	xsc3_crval, #object
xsc3_crval:
	crval	clear=0x04002202, mmuset=0x00003905, ucset=0x00001900

	__INITDATA

/*
 * Purpose : Function pointers used to access above functions - all calls
 *	     come through these
 */

	.type	xsc3_processor_functions, #object
ENTRY(xsc3_processor_functions)
	.word	v5t_early_abort
	.word	pabort_noifar
	.word	cpu_xsc3_proc_init
	.word	cpu_xsc3_proc_fin
	.word	cpu_xsc3_reset
	.word	cpu_xsc3_do_idle
	.word	cpu_xsc3_dcache_clean_area
	.word	cpu_xsc3_switch_mm
	.word	cpu_xsc3_set_pte_ext
	.size	xsc3_processor_functions, . - xsc3_processor_functions

	.section ".rodata"

	.type	cpu_arch_name, #object
cpu_arch_name:
	.asciz	"armv5te"
	.size	cpu_arch_name, . - cpu_arch_name

	.type	cpu_elf_name, #object
cpu_elf_name:
	.asciz	"v5"
	.size	cpu_elf_name, . - cpu_elf_name

	.type	cpu_xsc3_name, #object
cpu_xsc3_name:
	.asciz	"XScale-V3 based processor"
	.size	cpu_xsc3_name, . - cpu_xsc3_name

	.align

	.section ".proc.info.init", #alloc, #execinstr

	.type	__xsc3_proc_info,#object
__xsc3_proc_info:
	.long	0x69056000
	.long	0xffffe000
	.long	PMD_TYPE_SECT | \
		PMD_SECT_BUFFERABLE | \
		PMD_SECT_CACHEABLE | \
		PMD_SECT_AP_WRITE | \
		PMD_SECT_AP_READ
	.long	PMD_TYPE_SECT | \
		PMD_SECT_AP_WRITE | \
		PMD_SECT_AP_READ
	b	__xsc3_setup
	.long	cpu_arch_name
	.long	cpu_elf_name
	.long	HWCAP_SWP|HWCAP_HALF|HWCAP_THUMB|HWCAP_FAST_MULT|HWCAP_EDSP
	.long	cpu_xsc3_name
	.long	xsc3_processor_functions
	.long	v4wbi_tlb_fns
	.long	xsc3_mc_user_fns
	.long	xsc3_cache_fns
	.size	__xsc3_proc_info, . - __xsc3_proc_info
Commit	Line	Data
23bdf86a LB	1	/*
	2	* linux/arch/arm/mm/proc-xsc3.S
	3	*
	4	* Original Author: Matthew Gilbert
57fee39f	5	* Current Maintainer: Lennert Buytenhek <buytenh@wantstofly.org>
23bdf86a LB	6	*
23bdf86a LB	7	* Copyright 2004 (C) Intel Corp.
850b4293	8	* Copyright 2005 (C) MontaVista Software, Inc.
23bdf86a LB	9	*
	10	* This program is free software; you can redistribute it and/or modify
	11	* it under the terms of the GNU General Public License version 2 as
	12	* published by the Free Software Foundation.
	13	*
850b4293 LB	14	* MMU functions for the Intel XScale3 Core (XSC3). The XSC3 core is
850b4293 LB	15	* an extension to Intel's original XScale core that adds the following
23bdf86a LB	16	* features:
	17	*
	18	* - ARMv6 Supersections
	19	* - Low Locality Reference pages (replaces mini-cache)
	20	* - 36-bit addressing
	21	* - L2 cache
850b4293	22	* - Cache coherency if chipset supports it
23bdf86a	23	*
850b4293	24	* Based on original XScale code by Nicolas Pitre.
23bdf86a LB	25	*/
	26
	27	#include <linux/linkage.h>
	28	#include <linux/init.h>
	29	#include <asm/assembler.h>
ee90dabc	30	#include <asm/elf.h>
23bdf86a LB	31	#include <asm/hardware.h>
23bdf86a LB	32	#include <asm/pgtable.h>
b48340af	33	#include <asm/pgtable-hwdef.h>
23bdf86a LB	34	#include <asm/page.h>
	35	#include <asm/ptrace.h>
	36	#include "proc-macros.S"
	37
	38	/*
	39	* This is the maximum size of an area which will be flushed. If the
	40	* area is larger than this, then we flush the whole cache.
	41	*/
	42	#define MAX_AREA_SIZE 32768
	43
	44	/*
850b4293	45	* The cache line size of the L1 I, L1 D and unified L2 cache.
23bdf86a LB	46	*/
	47	#define CACHELINESIZE 32
	48
	49	/*
850b4293	50	* The size of the L1 D cache.
23bdf86a LB	51	*/
	52	#define CACHESIZE 32768
	53
	54	/*
	55	* Run with L2 enabled.
	56	*/
	57	#define L2_CACHE_ENABLE 1
	58
23bdf86a	59	/*
850b4293 LB	60	* This macro is used to wait for a CP15 write and is needed when we
	61	* have to ensure that the last operation to the coprocessor was
	62	* completed before continuing with operation.
23bdf86a LB	63	*/
	64	.macro cpwait_ret, lr, rd
	65	mrc p15, 0, \rd, c2, c0, 0 @ arbitrary read of cp15
	66	sub pc, \lr, \rd, LSR #32 @ wait for completion and
	67	@ flush instruction pipeline
	68	.endm
	69
	70	/*
850b4293	71	* This macro cleans and invalidates the entire L1 D cache.
23bdf86a LB	72	*/
	73
	74	.macro clean_d_cache rd, rs
	75	mov \rd, #0x1f00
	76	orr \rd, \rd, #0x00e0
850b4293	77	1: mcr p15, 0, \rd, c7, c14, 2 @ clean/invalidate L1 D line
23bdf86a LB	78	adds \rd, \rd, #0x40000000
	79	bcc 1b
	80	subs \rd, \rd, #0x20
	81	bpl 1b
	82	.endm
	83
	84	.text
	85
	86	/*
	87	* cpu_xsc3_proc_init()
	88	*
	89	* Nothing too exciting at the moment
	90	*/
	91	ENTRY(cpu_xsc3_proc_init)
	92	mov pc, lr
	93
	94	/*
	95	* cpu_xsc3_proc_fin()
	96	*/
	97	ENTRY(cpu_xsc3_proc_fin)
	98	str lr, [sp, #-4]!
	99	mov r0, #PSR_F_BIT\|PSR_I_BIT\|SVC_MODE
	100	msr cpsr_c, r0
	101	bl xsc3_flush_kern_cache_all @ clean caches
	102	mrc p15, 0, r0, c1, c0, 0 @ ctrl register
	103	bic r0, r0, #0x1800 @ ...IZ...........
	104	bic r0, r0, #0x0006 @ .............CA.
	105	mcr p15, 0, r0, c1, c0, 0 @ disable caches
	106	ldr pc, [sp], #4
	107
	108	/*
	109	* cpu_xsc3_reset(loc)
	110	*
	111	* Perform a soft reset of the system. Put the CPU into the
	112	* same state as it would be if it had been reset, and branch
	113	* to what would be the reset vector.
	114	*
	115	* loc: location to jump to for soft reset
	116	*/
	117	.align 5
	118	ENTRY(cpu_xsc3_reset)
	119	mov r1, #PSR_F_BIT\|PSR_I_BIT\|SVC_MODE
	120	msr cpsr_c, r1 @ reset CPSR
	121	mrc p15, 0, r1, c1, c0, 0 @ ctrl register
23bdf86a	122	bic r1, r1, #0x3900 @ ..VIZ..S........
850b4293	123	bic r1, r1, #0x0086 @ ........B....CA.
23bdf86a	124	mcr p15, 0, r1, c1, c0, 0 @ ctrl register
850b4293	125	mcr p15, 0, ip, c7, c7, 0 @ invalidate L1 caches and BTB
23bdf86a LB	126	bic r1, r1, #0x0001 @ ...............M
	127	mcr p15, 0, r1, c1, c0, 0 @ ctrl register
	128	@ CAUTION: MMU turned off from this point. We count on the pipeline
	129	@ already containing those two last instructions to survive.
850b4293	130	mcr p15, 0, ip, c8, c7, 0 @ invalidate I and D TLBs
23bdf86a LB	131	mov pc, r0
	132
	133	/*
	134	* cpu_xsc3_do_idle()
	135	*
	136	* Cause the processor to idle
	137	*
	138	* For now we do nothing but go to idle mode for every case
	139	*
	140	* XScale supports clock switching, but using idle mode support
	141	* allows external hardware to react to system state changes.
23bdf86a LB	142	*/
	143	.align 5
	144
	145	ENTRY(cpu_xsc3_do_idle)
	146	mov r0, #1
850b4293	147	mcr p14, 0, r0, c7, c0, 0 @ go to idle
23bdf86a LB	148	mov pc, lr
	149
	150	/* ================================= CACHE ================================ */
	151
	152	/*
	153	* flush_user_cache_all()
	154	*
	155	* Invalidate all cache entries in a particular address
	156	* space.
	157	*/
	158	ENTRY(xsc3_flush_user_cache_all)
	159	/* FALLTHROUGH */
	160
	161	/*
	162	* flush_kern_cache_all()
	163	*
	164	* Clean and invalidate the entire cache.
	165	*/
	166	ENTRY(xsc3_flush_kern_cache_all)
	167	mov r2, #VM_EXEC
	168	mov ip, #0
	169	__flush_whole_cache:
	170	clean_d_cache r0, r1
	171	tst r2, #VM_EXEC
850b4293 LB	172	mcrne p15, 0, ip, c7, c5, 0 @ invalidate L1 I cache and BTB
	173	mcrne p15, 0, ip, c7, c10, 4 @ data write barrier
	174	mcrne p15, 0, ip, c7, c5, 4 @ prefetch flush
23bdf86a LB	175	mov pc, lr
	176
	177	/*
	178	* flush_user_cache_range(start, end, vm_flags)
	179	*
	180	* Invalidate a range of cache entries in the specified
	181	* address space.
	182	*
	183	* - start - start address (may not be aligned)
	184	* - end - end address (exclusive, may not be aligned)
	185	* - vma - vma_area_struct describing address space
	186	*/
	187	.align 5
	188	ENTRY(xsc3_flush_user_cache_range)
	189	mov ip, #0
	190	sub r3, r1, r0 @ calculate total size
	191	cmp r3, #MAX_AREA_SIZE
	192	bhs __flush_whole_cache
	193
	194	1: tst r2, #VM_EXEC
850b4293 LB	195	mcrne p15, 0, r0, c7, c5, 1 @ invalidate L1 I line
850b4293 LB	196	mcr p15, 0, r0, c7, c14, 1 @ clean/invalidate L1 D line
23bdf86a LB	197	add r0, r0, #CACHELINESIZE
	198	cmp r0, r1
	199	blo 1b
	200	tst r2, #VM_EXEC
850b4293 LB	201	mcrne p15, 0, ip, c7, c5, 6 @ invalidate BTB
	202	mcrne p15, 0, ip, c7, c10, 4 @ data write barrier
	203	mcrne p15, 0, ip, c7, c5, 4 @ prefetch flush
23bdf86a LB	204	mov pc, lr
	205
	206	/*
	207	* coherent_kern_range(start, end)
	208	*
850b4293	209	* Ensure coherency between the I cache and the D cache in the
23bdf86a LB	210	* region described by start. If you have non-snooping
	211	* Harvard caches, you need to implement this function.
	212	*
	213	* - start - virtual start address
	214	* - end - virtual end address
	215	*
	216	* Note: single I-cache line invalidation isn't used here since
	217	* it also trashes the mini I-cache used by JTAG debuggers.
	218	*/
	219	ENTRY(xsc3_coherent_kern_range)
	220	/* FALLTHROUGH */
	221	ENTRY(xsc3_coherent_user_range)
	222	bic r0, r0, #CACHELINESIZE - 1
850b4293	223	1: mcr p15, 0, r0, c7, c10, 1 @ clean L1 D line
23bdf86a LB	224	add r0, r0, #CACHELINESIZE
	225	cmp r0, r1
	226	blo 1b
	227	mov r0, #0
850b4293 LB	228	mcr p15, 0, r0, c7, c5, 0 @ invalidate L1 I cache and BTB
	229	mcr p15, 0, r0, c7, c10, 4 @ data write barrier
	230	mcr p15, 0, r0, c7, c5, 4 @ prefetch flush
23bdf86a LB	231	mov pc, lr
	232
	233	/*
	234	* flush_kern_dcache_page(void *page)
	235	*
	236	* Ensure no D cache aliasing occurs, either with itself or
850b4293	237	* the I cache.
23bdf86a LB	238	*
	239	* - addr - page aligned address
	240	*/
	241	ENTRY(xsc3_flush_kern_dcache_page)
	242	add r1, r0, #PAGE_SZ
850b4293	243	1: mcr p15, 0, r0, c7, c14, 1 @ clean/invalidate L1 D line
23bdf86a LB	244	add r0, r0, #CACHELINESIZE
	245	cmp r0, r1
	246	blo 1b
	247	mov r0, #0
850b4293 LB	248	mcr p15, 0, r0, c7, c5, 0 @ invalidate L1 I cache and BTB
	249	mcr p15, 0, r0, c7, c10, 4 @ data write barrier
	250	mcr p15, 0, r0, c7, c5, 4 @ prefetch flush
23bdf86a LB	251	mov pc, lr
	252
	253	/*
	254	* dma_inv_range(start, end)
	255	*
	256	* Invalidate (discard) the specified virtual address range.
	257	* May not write back any entries. If 'start' or 'end'
	258	* are not cache line aligned, those lines must be written
	259	* back.
	260	*
	261	* - start - virtual start address
	262	* - end - virtual end address
	263	*/
	264	ENTRY(xsc3_dma_inv_range)
	265	tst r0, #CACHELINESIZE - 1
	266	bic r0, r0, #CACHELINESIZE - 1
850b4293 LB	267	mcrne p15, 0, r0, c7, c10, 1 @ clean L1 D line
850b4293 LB	268	mcrne p15, 1, r0, c7, c11, 1 @ clean L2 line
23bdf86a	269	tst r1, #CACHELINESIZE - 1
850b4293 LB	270	mcrne p15, 0, r1, c7, c10, 1 @ clean L1 D line
	271	mcrne p15, 1, r1, c7, c11, 1 @ clean L2 line
	272	1: mcr p15, 0, r0, c7, c6, 1 @ invalidate L1 D line
	273	mcr p15, 1, r0, c7, c7, 1 @ invalidate L2 line
23bdf86a LB	274	add r0, r0, #CACHELINESIZE
	275	cmp r0, r1
	276	blo 1b
850b4293	277	mcr p15, 0, r0, c7, c10, 4 @ data write barrier
23bdf86a LB	278	mov pc, lr
	279
	280	/*
	281	* dma_clean_range(start, end)
	282	*
	283	* Clean the specified virtual address range.
	284	*
	285	* - start - virtual start address
	286	* - end - virtual end address
	287	*/
	288	ENTRY(xsc3_dma_clean_range)
	289	bic r0, r0, #CACHELINESIZE - 1
850b4293 LB	290	1: mcr p15, 0, r0, c7, c10, 1 @ clean L1 D line
850b4293 LB	291	mcr p15, 1, r0, c7, c11, 1 @ clean L2 line
23bdf86a LB	292	add r0, r0, #CACHELINESIZE
	293	cmp r0, r1
	294	blo 1b
850b4293	295	mcr p15, 0, r0, c7, c10, 4 @ data write barrier
23bdf86a LB	296	mov pc, lr
	297
	298	/*
	299	* dma_flush_range(start, end)
	300	*
	301	* Clean and invalidate the specified virtual address range.
	302	*
	303	* - start - virtual start address
	304	* - end - virtual end address
	305	*/
	306	ENTRY(xsc3_dma_flush_range)
	307	bic r0, r0, #CACHELINESIZE - 1
850b4293 LB	308	1: mcr p15, 0, r0, c7, c14, 1 @ clean/invalidate L1 D line
	309	mcr p15, 1, r0, c7, c11, 1 @ clean L2 line
	310	mcr p15, 1, r0, c7, c7, 1 @ invalidate L2 line
23bdf86a LB	311	add r0, r0, #CACHELINESIZE
	312	cmp r0, r1
	313	blo 1b
850b4293	314	mcr p15, 0, r0, c7, c10, 4 @ data write barrier
23bdf86a LB	315	mov pc, lr
	316
	317	ENTRY(xsc3_cache_fns)
	318	.long xsc3_flush_kern_cache_all
	319	.long xsc3_flush_user_cache_all
	320	.long xsc3_flush_user_cache_range
	321	.long xsc3_coherent_kern_range
	322	.long xsc3_coherent_user_range
	323	.long xsc3_flush_kern_dcache_page
	324	.long xsc3_dma_inv_range
	325	.long xsc3_dma_clean_range
	326	.long xsc3_dma_flush_range
	327
	328	ENTRY(cpu_xsc3_dcache_clean_area)
850b4293	329	1: mcr p15, 0, r0, c7, c10, 1 @ clean L1 D line
23bdf86a LB	330	add r0, r0, #CACHELINESIZE
	331	subs r1, r1, #CACHELINESIZE
	332	bhi 1b
	333	mov pc, lr
	334
	335	/* =============================== PageTable ============================== */
	336
	337	/*
	338	* cpu_xsc3_switch_mm(pgd)
	339	*
	340	* Set the translation base pointer to be as described by pgd.
	341	*
	342	* pgd: new page tables
	343	*/
	344	.align 5
	345	ENTRY(cpu_xsc3_switch_mm)
	346	clean_d_cache r1, r2
850b4293 LB	347	mcr p15, 0, ip, c7, c5, 0 @ invalidate L1 I cache and BTB
	348	mcr p15, 0, ip, c7, c10, 4 @ data write barrier
	349	mcr p15, 0, ip, c7, c5, 4 @ prefetch flush
23bdf86a LB	350	#ifdef L2_CACHE_ENABLE
	351	orr r0, r0, #0x18 @ cache the page table in L2
	352	#endif
	353	mcr p15, 0, r0, c2, c0, 0 @ load page table pointer
850b4293	354	mcr p15, 0, ip, c8, c7, 0 @ invalidate I and D TLBs
23bdf86a LB	355	cpwait_ret lr, ip
	356
	357	/*
ad1ae2fe	358	* cpu_xsc3_set_pte_ext(ptep, pte, ext)
23bdf86a LB	359	*
	360	* Set a PTE and flush it out
	361	*
	362	*/
	363	.align 5
ad1ae2fe	364	ENTRY(cpu_xsc3_set_pte_ext)
23bdf86a LB	365	str r1, [r0], #-2048 @ linux version
23bdf86a LB	366
850b4293	367	bic r2, r1, #0xff0 @ keep C, B bits
23bdf86a	368	orr r2, r2, #PTE_TYPE_EXT @ extended page
850b4293	369	tst r1, #L_PTE_SHARED @ shared?
0e5fdca7	370	orrne r2, r2, #0x200
23bdf86a LB	371
	372	eor r3, r1, #L_PTE_PRESENT \| L_PTE_YOUNG \| L_PTE_WRITE \| L_PTE_DIRTY
	373
850b4293	374	tst r3, #L_PTE_USER @ user?
23bdf86a LB	375	orrne r2, r2, #PTE_EXT_AP_URO_SRW @ yes -> user r/o, system r/w
23bdf86a LB	376
850b4293	377	tst r3, #L_PTE_WRITE \| L_PTE_DIRTY @ write and dirty?
23bdf86a LB	378	orreq r2, r2, #PTE_EXT_AP_UNO_SRW @ yes -> user n/a, system r/w
	379	@ combined with user -> user r/w
	380
	381	#if L2_CACHE_ENABLE
850b4293	382	@ If it's cacheable, it needs to be in L2 also.
23bdf86a LB	383	eor ip, r1, #L_PTE_CACHEABLE
	384	tst ip, #L_PTE_CACHEABLE
	385	orreq r2, r2, #PTE_EXT_TEX(0x5)
	386	#endif
	387
850b4293	388	tst r3, #L_PTE_PRESENT \| L_PTE_YOUNG @ present and young?
23bdf86a LB	389	movne r2, #0 @ no -> fault
	390
	391	str r2, [r0] @ hardware version
	392	mov ip, #0
850b4293 LB	393	mcr p15, 0, r0, c7, c10, 1 @ clean L1 D line
850b4293 LB	394	mcr p15, 0, ip, c7, c10, 4 @ data write barrier
23bdf86a LB	395	mov pc, lr
	396
	397	.ltorg
	398
	399	.align
	400
	401	__INIT
	402
	403	.type __xsc3_setup, #function
	404	__xsc3_setup:
	405	mov r0, #PSR_F_BIT\|PSR_I_BIT\|SVC_MODE
	406	msr cpsr_c, r0
850b4293 LB	407	mcr p15, 0, ip, c7, c7, 0 @ invalidate L1 caches and BTB
	408	mcr p15, 0, ip, c7, c10, 4 @ data write barrier
	409	mcr p15, 0, ip, c7, c5, 4 @ prefetch flush
	410	mcr p15, 0, ip, c8, c7, 0 @ invalidate I and D TLBs
23bdf86a LB	411	#if L2_CACHE_ENABLE
	412	orr r4, r4, #0x18 @ cache the page table in L2
	413	#endif
	414	mcr p15, 0, r4, c2, c0, 0 @ load page table pointer
850b4293 LB	415
	416	mov r0, #0 @ don't allow CP access
	417	mcr p15, 0, r0, c15, c1, 0 @ write CP access register
	418
23bdf86a LB	419	mrc p15, 0, r0, c1, c0, 1 @ get auxiliary control reg
	420	and r0, r0, #2 @ preserve bit P bit setting
	421	#if L2_CACHE_ENABLE
	422	orr r0, r0, #(1 << 10) @ enable L2 for LLR cache
	423	#endif
	424	mcr p15, 0, r0, c1, c0, 1 @ set auxiliary control reg
22b19086 RK	425
	426	adr r5, xsc3_crval
	427	ldmia r5, {r5, r6}
23bdf86a	428	mrc p15, 0, r0, c1, c0, 0 @ get control register
850b4293 LB	429	bic r0, r0, r5 @ ..V. ..R. .... ..A.
	430	orr r0, r0, r6 @ ..VI Z..S .... .C.M (mmu)
	431	@ ...I Z..S .... .... (uc)
23bdf86a	432	#if L2_CACHE_ENABLE
22b19086	433	orr r0, r0, #0x04000000 @ L2 enable
23bdf86a LB	434	#endif
	435	mov pc, lr
	436
	437	.size __xsc3_setup, . - __xsc3_setup
	438
22b19086 RK	439	.type xsc3_crval, #object
22b19086 RK	440	xsc3_crval:
850b4293	441	crval clear=0x04002202, mmuset=0x00003905, ucset=0x00001900
22b19086	442
23bdf86a LB	443	__INITDATA
	444
	445	/*
	446	* Purpose : Function pointers used to access above functions - all calls
	447	* come through these
	448	*/
	449
	450	.type xsc3_processor_functions, #object
	451	ENTRY(xsc3_processor_functions)
	452	.word v5t_early_abort
4a1fd556	453	.word pabort_noifar
23bdf86a LB	454	.word cpu_xsc3_proc_init
	455	.word cpu_xsc3_proc_fin
	456	.word cpu_xsc3_reset
	457	.word cpu_xsc3_do_idle
	458	.word cpu_xsc3_dcache_clean_area
	459	.word cpu_xsc3_switch_mm
ad1ae2fe	460	.word cpu_xsc3_set_pte_ext
23bdf86a LB	461	.size xsc3_processor_functions, . - xsc3_processor_functions
	462
	463	.section ".rodata"
	464
	465	.type cpu_arch_name, #object
	466	cpu_arch_name:
	467	.asciz "armv5te"
	468	.size cpu_arch_name, . - cpu_arch_name
	469
	470	.type cpu_elf_name, #object
	471	cpu_elf_name:
	472	.asciz "v5"
	473	.size cpu_elf_name, . - cpu_elf_name
	474
	475	.type cpu_xsc3_name, #object
	476	cpu_xsc3_name:
850b4293	477	.asciz "XScale-V3 based processor"
23bdf86a LB	478	.size cpu_xsc3_name, . - cpu_xsc3_name
	479
	480	.align
	481
	482	.section ".proc.info.init", #alloc, #execinstr
	483
	484	.type __xsc3_proc_info,#object
	485	__xsc3_proc_info:
	486	.long 0x69056000
	487	.long 0xffffe000
8799ee9f RK	488	.long PMD_TYPE_SECT \| \
	489	PMD_SECT_BUFFERABLE \| \
	490	PMD_SECT_CACHEABLE \| \
	491	PMD_SECT_AP_WRITE \| \
	492	PMD_SECT_AP_READ
850b4293	493	.long PMD_TYPE_SECT \| \
8799ee9f RK	494	PMD_SECT_AP_WRITE \| \
8799ee9f RK	495	PMD_SECT_AP_READ
23bdf86a LB	496	b __xsc3_setup
	497	.long cpu_arch_name
	498	.long cpu_elf_name
	499	.long HWCAP_SWP\|HWCAP_HALF\|HWCAP_THUMB\|HWCAP_FAST_MULT\|HWCAP_EDSP
	500	.long cpu_xsc3_name
	501	.long xsc3_processor_functions
	502	.long v4wbi_tlb_fns
	503	.long xsc3_mc_user_fns
	504	.long xsc3_cache_fns
	505	.size __xsc3_proc_info, . - __xsc3_proc_info