projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 28853ac8 PZ |
1 | /* |
| 2 | * linux/arch/arm/mm/tlb-fa.S | |
| 3 | * | |
| 4 | * Copyright (C) 2005 Faraday Corp. | |
| 5 | * Copyright (C) 2008-2009 Paulius Zaleckas <paulius.zaleckas@teltonika.lt> | |
| 6 | * | |
| 7 | * Based on tlb-v4wbi.S: | |
| 8 | * Copyright (C) 1997-2002 Russell King | |
| 9 | * | |
| 10 | * This program is free software; you can redistribute it and/or modify | |
| 11 | * it under the terms of the GNU General Public License version 2 as | |
| 12 | * published by the Free Software Foundation. | |
| 13 | * | |
| 14 | * ARM architecture version 4, Faraday variation. | |
| 15 | * This assume an unified TLBs, with a write buffer, and branch target buffer (BTB) | |
| 16 | * | |
| 17 | * Processors: FA520 FA526 FA626 | |
| 18 | */ | |
| 19 | #include <linux/linkage.h> | |
| 20 | #include <linux/init.h> | |
| 6ebbf2ce | 21 | #include <asm/assembler.h> |
| 28853ac8 PZ |
22 | #include <asm/asm-offsets.h> |
| 23 | #include <asm/tlbflush.h> | |
| 24 | #include "proc-macros.S" | |
| 25 | ||
| 26 | ||
| 27 | /* | |
| 28 | * flush_user_tlb_range(start, end, mm) | |
| 29 | * | |
| 30 | * Invalidate a range of TLB entries in the specified address space. | |
| 31 | * | |
| 32 | * - start - range start address | |
| 33 | * - end - range end address | |
| 34 | * - mm - mm_struct describing address space | |
| 35 | */ | |
| 36 | .align 4 | |
| 37 | ENTRY(fa_flush_user_tlb_range) | |
| 38 | vma_vm_mm ip, r2 | |
| 39 | act_mm r3 @ get current->active_mm | |
| 40 | eors r3, ip, r3 @ == mm ? | |
| 6ebbf2ce | 41 | retne lr @ no, we dont do anything |
| 28853ac8 PZ |
42 | mov r3, #0 |
| 43 | mcr p15, 0, r3, c7, c10, 4 @ drain WB | |
| 44 | bic r0, r0, #0x0ff | |
| 45 | bic r0, r0, #0xf00 | |
| 46 | 1: mcr p15, 0, r0, c8, c7, 1 @ invalidate UTLB entry | |
| 47 | add r0, r0, #PAGE_SZ | |
| 48 | cmp r0, r1 | |
| 49 | blo 1b | |
| 28853ac8 | 50 | mcr p15, 0, r3, c7, c10, 4 @ data write barrier |
| 6ebbf2ce | 51 | ret lr |
| 28853ac8 PZ |
52 | |
| 53 | ||
| 54 | ENTRY(fa_flush_kern_tlb_range) | |
| 55 | mov r3, #0 | |
| 56 | mcr p15, 0, r3, c7, c10, 4 @ drain WB | |
| 57 | bic r0, r0, #0x0ff | |
| 58 | bic r0, r0, #0xf00 | |
| 59 | 1: mcr p15, 0, r0, c8, c7, 1 @ invalidate UTLB entry | |
| 60 | add r0, r0, #PAGE_SZ | |
| 61 | cmp r0, r1 | |
| 62 | blo 1b | |
| 28853ac8 | 63 | mcr p15, 0, r3, c7, c10, 4 @ data write barrier |
| 4348810a | 64 | mcr p15, 0, r3, c7, c5, 4 @ prefetch flush (isb) |
| 6ebbf2ce | 65 | ret lr |
| 28853ac8 PZ |
66 | |
| 67 | __INITDATA | |
| 68 | ||
| 27eebe4c DM |
69 | /* define struct cpu_tlb_fns (see <asm/tlbflush.h> and proc-macros.S) */ |
| 70 | define_tlb_functions fa, fa_tlb_flags |