[deliverable/linux.git] / arch / arm / mm / tlb-v6.S

/*
 *  linux/arch/arm/mm/tlb-v6.S
 *
 *  Copyright (C) 1997-2002 Russell King
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 *
 *  ARM architecture version 6 TLB handling functions.
 *  These assume a split I/D TLB.
 */
#include <linux/init.h>
#include <linux/linkage.h>
#include <asm/asm-offsets.h>
#include <asm/page.h>
#include <asm/tlbflush.h>
#include "proc-macros.S"

#define HARVARD_TLB

/*
 *	v6wbi_flush_user_tlb_range(start, end, vma)
 *
 *	Invalidate a range of TLB entries in the specified address space.
 *
 *	- start - start address (may not be aligned)
 *	- end   - end address (exclusive, may not be aligned)
 *	- vma   - vma_struct describing address range
 *
 *	It is assumed that:
 *	- the "Invalidate single entry" instruction will invalidate
 *	  both the I and the D TLBs on Harvard-style TLBs
 */
ENTRY(v6wbi_flush_user_tlb_range)
	vma_vm_mm r3, r2			@ get vma->vm_mm
	mov	ip, #0
	mmid	r3, r3				@ get vm_mm->context.id
	mcr	p15, 0, ip, c7, c10, 4		@ drain write buffer
	mov	r0, r0, lsr #PAGE_SHIFT		@ align address
	mov	r1, r1, lsr #PAGE_SHIFT
	asid	r3, r3				@ mask ASID
	orr	r0, r3, r0, lsl #PAGE_SHIFT	@ Create initial MVA
	mov	r1, r1, lsl #PAGE_SHIFT
	vma_vm_flags r2, r2			@ get vma->vm_flags
1:
#ifdef HARVARD_TLB
	mcr	p15, 0, r0, c8, c6, 1		@ TLB invalidate D MVA (was 1)
	tst	r2, #VM_EXEC			@ Executable area ?
	mcrne	p15, 0, r0, c8, c5, 1		@ TLB invalidate I MVA (was 1)
#else
	mcr	p15, 0, r0, c8, c7, 1		@ TLB invalidate MVA (was 1)
#endif
	add	r0, r0, #PAGE_SZ
	cmp	r0, r1
	blo	1b
	mcr	p15, 0, ip, c7, c10, 4		@ data synchronization barrier
	mov	pc, lr

/*
 *	v6wbi_flush_kern_tlb_range(start,end)
 *
 *	Invalidate a range of kernel TLB entries
 *
 *	- start - start address (may not be aligned)
 *	- end   - end address (exclusive, may not be aligned)
 */
ENTRY(v6wbi_flush_kern_tlb_range)
	mov	r2, #0
	mcr	p15, 0, r2, c7, c10, 4		@ drain write buffer
	mov	r0, r0, lsr #PAGE_SHIFT		@ align address
	mov	r1, r1, lsr #PAGE_SHIFT
	mov	r0, r0, lsl #PAGE_SHIFT
	mov	r1, r1, lsl #PAGE_SHIFT
1:
#ifdef HARVARD_TLB
	mcr	p15, 0, r0, c8, c6, 1		@ TLB invalidate D MVA
	mcr	p15, 0, r0, c8, c5, 1		@ TLB invalidate I MVA
#else
	mcr	p15, 0, r0, c8, c7, 1		@ TLB invalidate MVA
#endif
	add	r0, r0, #PAGE_SZ
	cmp	r0, r1
	blo	1b
	mcr	p15, 0, r2, c7, c10, 4		@ data synchronization barrier
	mcr	p15, 0, r2, c7, c5, 4		@ prefetch flush (isb)
	mov	pc, lr

	__INIT

	/* define struct cpu_tlb_fns (see <asm/tlbflush.h> and proc-macros.S) */
	define_tlb_functions v6wbi, v6wbi_tlb_flags
Commit	Line	Data
1da177e4 LT	1	/*
	2	* linux/arch/arm/mm/tlb-v6.S
	3	*
	4	* Copyright (C) 1997-2002 Russell King
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License version 2 as
	8	* published by the Free Software Foundation.
	9	*
	10	* ARM architecture version 6 TLB handling functions.
	11	* These assume a split I/D TLB.
	12	*/
991da17e	13	#include <linux/init.h>
1da177e4	14	#include <linux/linkage.h>
e6ae744d	15	#include <asm/asm-offsets.h>
1da177e4 LT	16	#include <asm/page.h>
	17	#include <asm/tlbflush.h>
	18	#include "proc-macros.S"
	19
	20	#define HARVARD_TLB
	21
	22	/*
	23	* v6wbi_flush_user_tlb_range(start, end, vma)
	24	*
	25	* Invalidate a range of TLB entries in the specified address space.
	26	*
	27	* - start - start address (may not be aligned)
	28	* - end - end address (exclusive, may not be aligned)
	29	* - vma - vma_struct describing address range
	30	*
	31	* It is assumed that:
	32	* - the "Invalidate single entry" instruction will invalidate
	33	* both the I and the D TLBs on Harvard-style TLBs
	34	*/
	35	ENTRY(v6wbi_flush_user_tlb_range)
	36	vma_vm_mm r3, r2 @ get vma->vm_mm
	37	mov ip, #0
	38	mmid r3, r3 @ get vm_mm->context.id
	39	mcr p15, 0, ip, c7, c10, 4 @ drain write buffer
	40	mov r0, r0, lsr #PAGE_SHIFT @ align address
	41	mov r1, r1, lsr #PAGE_SHIFT
	42	asid r3, r3 @ mask ASID
	43	orr r0, r3, r0, lsl #PAGE_SHIFT @ Create initial MVA
	44	mov r1, r1, lsl #PAGE_SHIFT
	45	vma_vm_flags r2, r2 @ get vma->vm_flags
	46	1:
	47	#ifdef HARVARD_TLB
	48	mcr p15, 0, r0, c8, c6, 1 @ TLB invalidate D MVA (was 1)
	49	tst r2, #VM_EXEC @ Executable area ?
	50	mcrne p15, 0, r0, c8, c5, 1 @ TLB invalidate I MVA (was 1)
	51	#else
	52	mcr p15, 0, r0, c8, c7, 1 @ TLB invalidate MVA (was 1)
	53	#endif
	54	add r0, r0, #PAGE_SZ
	55	cmp r0, r1
	56	blo 1b
e6a5d66f	57	mcr p15, 0, ip, c7, c10, 4 @ data synchronization barrier
1da177e4 LT	58	mov pc, lr
	59
	60	/*
	61	* v6wbi_flush_kern_tlb_range(start,end)
	62	*
	63	* Invalidate a range of kernel TLB entries
	64	*
	65	* - start - start address (may not be aligned)
	66	* - end - end address (exclusive, may not be aligned)
	67	*/
	68	ENTRY(v6wbi_flush_kern_tlb_range)
	69	mov r2, #0
	70	mcr p15, 0, r2, c7, c10, 4 @ drain write buffer
	71	mov r0, r0, lsr #PAGE_SHIFT @ align address
	72	mov r1, r1, lsr #PAGE_SHIFT
	73	mov r0, r0, lsl #PAGE_SHIFT
	74	mov r1, r1, lsl #PAGE_SHIFT
	75	1:
	76	#ifdef HARVARD_TLB
	77	mcr p15, 0, r0, c8, c6, 1 @ TLB invalidate D MVA
	78	mcr p15, 0, r0, c8, c5, 1 @ TLB invalidate I MVA
	79	#else
	80	mcr p15, 0, r0, c8, c7, 1 @ TLB invalidate MVA
	81	#endif
	82	add r0, r0, #PAGE_SZ
	83	cmp r0, r1
	84	blo 1b
6a0e2430	85	mcr p15, 0, r2, c7, c10, 4 @ data synchronization barrier
4348810a	86	mcr p15, 0, r2, c7, c5, 4 @ prefetch flush (isb)
1da177e4 LT	87	mov pc, lr
1da177e4 LT	88
991da17e	89	__INIT
1da177e4	90
3b7f39fa DM	91	/* define struct cpu_tlb_fns (see <asm/tlbflush.h> and proc-macros.S) */
3b7f39fa DM	92	define_tlb_functions v6wbi, v6wbi_tlb_flags