[deliverable/linux.git] / arch / arm / plat-iop / time.c

/*
 * arch/arm/plat-iop/time.c
 *
 * Timer code for IOP32x and IOP33x based systems
 *
 * Author: Deepak Saxena <dsaxena@mvista.com>
 *
 * Copyright 2002-2003 MontaVista Software Inc.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License as published by the
 * Free Software Foundation; either version 2 of the License, or (at your
 * option) any later version.
 */

#include <linux/kernel.h>
#include <linux/interrupt.h>
#include <linux/time.h>
#include <linux/init.h>
#include <linux/timex.h>
#include <linux/sched.h>
#include <linux/io.h>
#include <linux/clocksource.h>
#include <linux/clockchips.h>
#include <mach/hardware.h>
#include <asm/irq.h>
#include <asm/uaccess.h>
#include <asm/mach/irq.h>
#include <asm/mach/time.h>
#include <mach/time.h>

/*
 * Minimum clocksource/clockevent timer range in seconds
 */
#define IOP_MIN_RANGE 4

/*
 * IOP clocksource (free-running timer 1).
 */
static cycle_t notrace iop_clocksource_read(struct clocksource *unused)
{
	return 0xffffffffu - read_tcr1();
}

static struct clocksource iop_clocksource = {
	.name 		= "iop_timer1",
	.rating		= 300,
	.read		= iop_clocksource_read,
	.mask		= CLOCKSOURCE_MASK(32),
	.flags		= CLOCK_SOURCE_IS_CONTINUOUS,
};

/*
 * IOP sched_clock() implementation via its clocksource.
 */
unsigned long long sched_clock(void)
{
	cycle_t cyc = iop_clocksource_read(NULL);
	struct clocksource *cs = &iop_clocksource;

	return clocksource_cyc2ns(cyc, cs->mult, cs->shift);
}

/*
 * IOP clockevents (interrupting timer 0).
 */
static int iop_set_next_event(unsigned long delta,
			      struct clock_event_device *unused)
{
	u32 tmr = IOP_TMR_PRIVILEGED | IOP_TMR_RATIO_1_1;

	BUG_ON(delta == 0);
	write_tmr0(tmr & ~(IOP_TMR_EN | IOP_TMR_RELOAD));
	write_tcr0(delta);
	write_tmr0((tmr & ~IOP_TMR_RELOAD) | IOP_TMR_EN);

	return 0;
}

static unsigned long ticks_per_jiffy;

static void iop_set_mode(enum clock_event_mode mode,
			 struct clock_event_device *unused)
{
	u32 tmr = read_tmr0();

	switch (mode) {
	case CLOCK_EVT_MODE_PERIODIC:
		write_tmr0(tmr & ~IOP_TMR_EN);
		write_tcr0(ticks_per_jiffy - 1);
		tmr |= (IOP_TMR_RELOAD | IOP_TMR_EN);
		break;
	case CLOCK_EVT_MODE_ONESHOT:
		/* ->set_next_event sets period and enables timer */
		tmr &= ~(IOP_TMR_RELOAD | IOP_TMR_EN);
		break;
	case CLOCK_EVT_MODE_RESUME:
		tmr |= IOP_TMR_EN;
		break;
	case CLOCK_EVT_MODE_SHUTDOWN:
	case CLOCK_EVT_MODE_UNUSED:
	default:
		tmr &= ~IOP_TMR_EN;
		break;
	}

	write_tmr0(tmr);
}

static struct clock_event_device iop_clockevent = {
	.name		= "iop_timer0",
	.features       = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
	.rating         = 300,
	.set_next_event	= iop_set_next_event,
	.set_mode	= iop_set_mode,
};

static irqreturn_t
iop_timer_interrupt(int irq, void *dev_id)
{
	struct clock_event_device *evt = dev_id;

	write_tisr(1);
	evt->event_handler(evt);
	return IRQ_HANDLED;
}

static struct irqaction iop_timer_irq = {
	.name		= "IOP Timer Tick",
	.handler	= iop_timer_interrupt,
	.flags		= IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
	.dev_id		= &iop_clockevent,
};

static unsigned long iop_tick_rate;
unsigned long get_iop_tick_rate(void)
{
	return iop_tick_rate;
}
EXPORT_SYMBOL(get_iop_tick_rate);

void __init iop_init_time(unsigned long tick_rate)
{
	u32 timer_ctl;

	ticks_per_jiffy = DIV_ROUND_CLOSEST(tick_rate, HZ);
	iop_tick_rate = tick_rate;

	timer_ctl = IOP_TMR_EN | IOP_TMR_PRIVILEGED |
			IOP_TMR_RELOAD | IOP_TMR_RATIO_1_1;

	/*
	 * Set up interrupting clockevent timer 0.
	 */
	write_tmr0(timer_ctl & ~IOP_TMR_EN);
	setup_irq(IRQ_IOP_TIMER0, &iop_timer_irq);
	clockevents_calc_mult_shift(&iop_clockevent,
				    tick_rate, IOP_MIN_RANGE);
	iop_clockevent.max_delta_ns =
		clockevent_delta2ns(0xfffffffe, &iop_clockevent);
	iop_clockevent.min_delta_ns =
		clockevent_delta2ns(0xf, &iop_clockevent);
	iop_clockevent.cpumask = cpumask_of(0);
	clockevents_register_device(&iop_clockevent);
	write_trr0(ticks_per_jiffy - 1);
	write_tcr0(ticks_per_jiffy - 1);
	write_tmr0(timer_ctl);

	/*
	 * Set up free-running clocksource timer 1.
	 */
	write_trr1(0xffffffff);
	write_tcr1(0xffffffff);
	write_tmr1(timer_ctl);
	clocksource_calc_mult_shift(&iop_clocksource, tick_rate,
				    IOP_MIN_RANGE);
	clocksource_register(&iop_clocksource);
}
Commit	Line	Data
48388b2a LB	1	/*
	2	* arch/arm/plat-iop/time.c
	3	*
	4	* Timer code for IOP32x and IOP33x based systems
	5	*
	6	* Author: Deepak Saxena <dsaxena@mvista.com>
	7	*
	8	* Copyright 2002-2003 MontaVista Software Inc.
	9	*
	10	* This program is free software; you can redistribute it and/or modify it
	11	* under the terms of the GNU General Public License as published by the
	12	* Free Software Foundation; either version 2 of the License, or (at your
	13	* option) any later version.
	14	*/
	15
	16	#include <linux/kernel.h>
	17	#include <linux/interrupt.h>
	18	#include <linux/time.h>
	19	#include <linux/init.h>
	20	#include <linux/timex.h>
a5542a0f	21	#include <linux/sched.h>
fced80c7	22	#include <linux/io.h>
a91549a8	23	#include <linux/clocksource.h>
469d3044	24	#include <linux/clockchips.h>
a09e64fb	25	#include <mach/hardware.h>
48388b2a LB	26	#include <asm/irq.h>
	27	#include <asm/uaccess.h>
	28	#include <asm/mach/irq.h>
	29	#include <asm/mach/time.h>
a09e64fb	30	#include <mach/time.h>
48388b2a	31
7d633975 LW	32	/*
	33	* Minimum clocksource/clockevent timer range in seconds
	34	*/
	35	#define IOP_MIN_RANGE 4
	36
a91549a8 MP	37	/*
	38	* IOP clocksource (free-running timer 1).
	39	*/
a5542a0f	40	static cycle_t notrace iop_clocksource_read(struct clocksource *unused)
a91549a8 MP	41	{
	42	return 0xffffffffu - read_tcr1();
	43	}
	44
	45	static struct clocksource iop_clocksource = {
	46	.name = "iop_timer1",
	47	.rating = 300,
	48	.read = iop_clocksource_read,
	49	.mask = CLOCKSOURCE_MASK(32),
	50	.flags = CLOCK_SOURCE_IS_CONTINUOUS,
	51	};
	52
345a3229 MP	53	/*
	54	* IOP sched_clock() implementation via its clocksource.
	55	*/
	56	unsigned long long sched_clock(void)
	57	{
	58	cycle_t cyc = iop_clocksource_read(NULL);
	59	struct clocksource *cs = &iop_clocksource;
	60
	61	return clocksource_cyc2ns(cyc, cs->mult, cs->shift);
	62	}
	63
469d3044 MP	64	/*
	65	* IOP clockevents (interrupting timer 0).
	66	*/
	67	static int iop_set_next_event(unsigned long delta,
	68	struct clock_event_device *unused)
	69	{
	70	u32 tmr = IOP_TMR_PRIVILEGED \| IOP_TMR_RATIO_1_1;
	71
	72	BUG_ON(delta == 0);
	73	write_tmr0(tmr & ~(IOP_TMR_EN \| IOP_TMR_RELOAD));
	74	write_tcr0(delta);
	75	write_tmr0((tmr & ~IOP_TMR_RELOAD) \| IOP_TMR_EN);
	76
	77	return 0;
	78	}
	79
48388b2a	80	static unsigned long ticks_per_jiffy;
469d3044 MP	81
	82	static void iop_set_mode(enum clock_event_mode mode,
	83	struct clock_event_device *unused)
	84	{
	85	u32 tmr = read_tmr0();
	86
	87	switch (mode) {
	88	case CLOCK_EVT_MODE_PERIODIC:
	89	write_tmr0(tmr & ~IOP_TMR_EN);
	90	write_tcr0(ticks_per_jiffy - 1);
	91	tmr \|= (IOP_TMR_RELOAD \| IOP_TMR_EN);
	92	break;
	93	case CLOCK_EVT_MODE_ONESHOT:
	94	/* ->set_next_event sets period and enables timer */
	95	tmr &= ~(IOP_TMR_RELOAD \| IOP_TMR_EN);
	96	break;
	97	case CLOCK_EVT_MODE_RESUME:
	98	tmr \|= IOP_TMR_EN;
	99	break;
	100	case CLOCK_EVT_MODE_SHUTDOWN:
	101	case CLOCK_EVT_MODE_UNUSED:
	102	default:
	103	tmr &= ~IOP_TMR_EN;
	104	break;
	105	}
	106
	107	write_tmr0(tmr);
	108	}
	109
	110	static struct clock_event_device iop_clockevent = {
	111	.name = "iop_timer0",
	112	.features = CLOCK_EVT_FEAT_PERIODIC \| CLOCK_EVT_FEAT_ONESHOT,
	113	.rating = 300,
	114	.set_next_event = iop_set_next_event,
	115	.set_mode = iop_set_mode,
	116	};
	117
48388b2a	118	static irqreturn_t
3668b45d	119	iop_timer_interrupt(int irq, void *dev_id)
48388b2a	120	{
469d3044	121	struct clock_event_device *evt = dev_id;
48388b2a	122
469d3044 MP	123	write_tisr(1);
469d3044 MP	124	evt->event_handler(evt);
48388b2a LB	125	return IRQ_HANDLED;
	126	}
	127
3668b45d DW	128	static struct irqaction iop_timer_irq = {
	129	.name = "IOP Timer Tick",
	130	.handler = iop_timer_interrupt,
b30fabad	131	.flags = IRQF_DISABLED \| IRQF_TIMER \| IRQF_IRQPOLL,
469d3044	132	.dev_id = &iop_clockevent,
48388b2a LB	133	};
48388b2a LB	134
70c14ff0 DW	135	static unsigned long iop_tick_rate;
	136	unsigned long get_iop_tick_rate(void)
	137	{
	138	return iop_tick_rate;
	139	}
	140	EXPORT_SYMBOL(get_iop_tick_rate);
	141
3668b45d	142	void __init iop_init_time(unsigned long tick_rate)
48388b2a LB	143	{
	144	u32 timer_ctl;
	145
a692838d	146	ticks_per_jiffy = DIV_ROUND_CLOSEST(tick_rate, HZ);
70c14ff0	147	iop_tick_rate = tick_rate;
48388b2a	148
3668b45d DW	149	timer_ctl = IOP_TMR_EN \| IOP_TMR_PRIVILEGED \|
3668b45d DW	150	IOP_TMR_RELOAD \| IOP_TMR_RATIO_1_1;
48388b2a LB	151
48388b2a LB	152	/*
469d3044	153	* Set up interrupting clockevent timer 0.
48388b2a	154	*/
469d3044 MP	155	write_tmr0(timer_ctl & ~IOP_TMR_EN);
469d3044 MP	156	setup_irq(IRQ_IOP_TIMER0, &iop_timer_irq);
7d633975 LW	157	clockevents_calc_mult_shift(&iop_clockevent,
7d633975 LW	158	tick_rate, IOP_MIN_RANGE);
469d3044 MP	159	iop_clockevent.max_delta_ns =
	160	clockevent_delta2ns(0xfffffffe, &iop_clockevent);
	161	iop_clockevent.min_delta_ns =
	162	clockevent_delta2ns(0xf, &iop_clockevent);
	163	iop_clockevent.cpumask = cpumask_of(0);
	164	clockevents_register_device(&iop_clockevent);
3668b45d	165	write_trr0(ticks_per_jiffy - 1);
469d3044	166	write_tcr0(ticks_per_jiffy - 1);
3668b45d	167	write_tmr0(timer_ctl);
a91549a8 MP	168
	169	/*
	170	* Set up free-running clocksource timer 1.
	171	*/
3668b45d	172	write_trr1(0xffffffff);
a91549a8	173	write_tcr1(0xffffffff);
3668b45d	174	write_tmr1(timer_ctl);
7d633975 LW	175	clocksource_calc_mult_shift(&iop_clocksource, tick_rate,
7d633975 LW	176	IOP_MIN_RANGE);
a91549a8	177	clocksource_register(&iop_clocksource);
48388b2a	178	}