[deliverable/linux.git] / arch / arm / plat-iop / time.c

/*
 * arch/arm/plat-iop/time.c
 *
 * Timer code for IOP32x and IOP33x based systems
 *
 * Author: Deepak Saxena <dsaxena@mvista.com>
 *
 * Copyright 2002-2003 MontaVista Software Inc.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms of the GNU General Public License as published by the
 * Free Software Foundation; either version 2 of the License, or (at your
 * option) any later version.
 */

#include <linux/kernel.h>
#include <linux/interrupt.h>
#include <linux/time.h>
#include <linux/init.h>
#include <linux/timex.h>
#include <linux/io.h>
#include <linux/clocksource.h>
#include <linux/clockchips.h>
#include <linux/export.h>
#include <linux/sched_clock.h>
#include <mach/hardware.h>
#include <asm/irq.h>
#include <asm/uaccess.h>
#include <asm/mach/irq.h>
#include <asm/mach/time.h>
#include <mach/time.h>

/*
 * Minimum clocksource/clockevent timer range in seconds
 */
#define IOP_MIN_RANGE 4

/*
 * IOP clocksource (free-running timer 1).
 */
static cycle_t notrace iop_clocksource_read(struct clocksource *unused)
{
	return 0xffffffffu - read_tcr1();
}

static struct clocksource iop_clocksource = {
	.name 		= "iop_timer1",
	.rating		= 300,
	.read		= iop_clocksource_read,
	.mask		= CLOCKSOURCE_MASK(32),
	.flags		= CLOCK_SOURCE_IS_CONTINUOUS,
};

/*
 * IOP sched_clock() implementation via its clocksource.
 */
static u64 notrace iop_read_sched_clock(void)
{
	return 0xffffffffu - read_tcr1();
}

/*
 * IOP clockevents (interrupting timer 0).
 */
static int iop_set_next_event(unsigned long delta,
			      struct clock_event_device *unused)
{
	u32 tmr = IOP_TMR_PRIVILEGED | IOP_TMR_RATIO_1_1;

	BUG_ON(delta == 0);
	write_tmr0(tmr & ~(IOP_TMR_EN | IOP_TMR_RELOAD));
	write_tcr0(delta);
	write_tmr0((tmr & ~IOP_TMR_RELOAD) | IOP_TMR_EN);

	return 0;
}

static unsigned long ticks_per_jiffy;

static int iop_set_periodic(struct clock_event_device *evt)
{
	u32 tmr = read_tmr0();

	write_tmr0(tmr & ~IOP_TMR_EN);
	write_tcr0(ticks_per_jiffy - 1);
	write_trr0(ticks_per_jiffy - 1);
	tmr |= (IOP_TMR_RELOAD | IOP_TMR_EN);

	write_tmr0(tmr);
	return 0;
}

static int iop_set_oneshot(struct clock_event_device *evt)
{
	u32 tmr = read_tmr0();

	/* ->set_next_event sets period and enables timer */
	tmr &= ~(IOP_TMR_RELOAD | IOP_TMR_EN);
	write_tmr0(tmr);
	return 0;
}

static int iop_shutdown(struct clock_event_device *evt)
{
	u32 tmr = read_tmr0();

	tmr &= ~IOP_TMR_EN;
	write_tmr0(tmr);
	return 0;
}

static int iop_resume(struct clock_event_device *evt)
{
	u32 tmr = read_tmr0();

	tmr |= IOP_TMR_EN;
	write_tmr0(tmr);
	return 0;
}

static struct clock_event_device iop_clockevent = {
	.name			= "iop_timer0",
	.features		= CLOCK_EVT_FEAT_PERIODIC |
				  CLOCK_EVT_FEAT_ONESHOT,
	.rating			= 300,
	.set_next_event		= iop_set_next_event,
	.set_state_shutdown	= iop_shutdown,
	.set_state_periodic	= iop_set_periodic,
	.tick_resume		= iop_resume,
	.set_state_oneshot	= iop_set_oneshot,
};

static irqreturn_t
iop_timer_interrupt(int irq, void *dev_id)
{
	struct clock_event_device *evt = dev_id;

	write_tisr(1);
	evt->event_handler(evt);
	return IRQ_HANDLED;
}

static struct irqaction iop_timer_irq = {
	.name		= "IOP Timer Tick",
	.handler	= iop_timer_interrupt,
	.flags		= IRQF_TIMER | IRQF_IRQPOLL,
	.dev_id		= &iop_clockevent,
};

static unsigned long iop_tick_rate;
unsigned long get_iop_tick_rate(void)
{
	return iop_tick_rate;
}
EXPORT_SYMBOL(get_iop_tick_rate);

void __init iop_init_time(unsigned long tick_rate)
{
	u32 timer_ctl;

	sched_clock_register(iop_read_sched_clock, 32, tick_rate);

	ticks_per_jiffy = DIV_ROUND_CLOSEST(tick_rate, HZ);
	iop_tick_rate = tick_rate;

	timer_ctl = IOP_TMR_EN | IOP_TMR_PRIVILEGED |
			IOP_TMR_RELOAD | IOP_TMR_RATIO_1_1;

	/*
	 * Set up interrupting clockevent timer 0.
	 */
	write_tmr0(timer_ctl & ~IOP_TMR_EN);
	write_tisr(1);
	setup_irq(IRQ_IOP_TIMER0, &iop_timer_irq);
	iop_clockevent.cpumask = cpumask_of(0);
	clockevents_config_and_register(&iop_clockevent, tick_rate,
					0xf, 0xfffffffe);

	/*
	 * Set up free-running clocksource timer 1.
	 */
	write_trr1(0xffffffff);
	write_tcr1(0xffffffff);
	write_tmr1(timer_ctl);
	clocksource_register_hz(&iop_clocksource, tick_rate);
}
Commit	Line	Data
48388b2a LB	1	/*
	2	* arch/arm/plat-iop/time.c
	3	*
	4	* Timer code for IOP32x and IOP33x based systems
	5	*
	6	* Author: Deepak Saxena <dsaxena@mvista.com>
	7	*
	8	* Copyright 2002-2003 MontaVista Software Inc.
	9	*
	10	* This program is free software; you can redistribute it and/or modify it
	11	* under the terms of the GNU General Public License as published by the
	12	* Free Software Foundation; either version 2 of the License, or (at your
	13	* option) any later version.
	14	*/
	15
	16	#include <linux/kernel.h>
	17	#include <linux/interrupt.h>
	18	#include <linux/time.h>
	19	#include <linux/init.h>
	20	#include <linux/timex.h>
fced80c7	21	#include <linux/io.h>
a91549a8	22	#include <linux/clocksource.h>
469d3044	23	#include <linux/clockchips.h>
dc28094b	24	#include <linux/export.h>
38ff87f7	25	#include <linux/sched_clock.h>
a09e64fb	26	#include <mach/hardware.h>
48388b2a LB	27	#include <asm/irq.h>
	28	#include <asm/uaccess.h>
	29	#include <asm/mach/irq.h>
	30	#include <asm/mach/time.h>
a09e64fb	31	#include <mach/time.h>
48388b2a	32
7d633975 LW	33	/*
	34	* Minimum clocksource/clockevent timer range in seconds
	35	*/
	36	#define IOP_MIN_RANGE 4
	37
a91549a8 MP	38	/*
	39	* IOP clocksource (free-running timer 1).
	40	*/
a5542a0f	41	static cycle_t notrace iop_clocksource_read(struct clocksource *unused)
a91549a8 MP	42	{
	43	return 0xffffffffu - read_tcr1();
	44	}
	45
	46	static struct clocksource iop_clocksource = {
	47	.name = "iop_timer1",
	48	.rating = 300,
	49	.read = iop_clocksource_read,
	50	.mask = CLOCKSOURCE_MASK(32),
	51	.flags = CLOCK_SOURCE_IS_CONTINUOUS,
	52	};
	53
345a3229 MP	54	/*
	55	* IOP sched_clock() implementation via its clocksource.
	56	*/
c66af541	57	static u64 notrace iop_read_sched_clock(void)
345a3229	58	{
2f0778af	59	return 0xffffffffu - read_tcr1();
345a3229 MP	60	}
345a3229 MP	61
469d3044 MP	62	/*
	63	* IOP clockevents (interrupting timer 0).
	64	*/
	65	static int iop_set_next_event(unsigned long delta,
	66	struct clock_event_device *unused)
	67	{
	68	u32 tmr = IOP_TMR_PRIVILEGED \| IOP_TMR_RATIO_1_1;
	69
	70	BUG_ON(delta == 0);
	71	write_tmr0(tmr & ~(IOP_TMR_EN \| IOP_TMR_RELOAD));
	72	write_tcr0(delta);
	73	write_tmr0((tmr & ~IOP_TMR_RELOAD) \| IOP_TMR_EN);
	74
	75	return 0;
	76	}
	77
48388b2a	78	static unsigned long ticks_per_jiffy;
469d3044	79
8d778377	80	static int iop_set_periodic(struct clock_event_device *evt)
469d3044 MP	81	{
	82	u32 tmr = read_tmr0();
	83
8d778377 VK	84	write_tmr0(tmr & ~IOP_TMR_EN);
	85	write_tcr0(ticks_per_jiffy - 1);
	86	write_trr0(ticks_per_jiffy - 1);
	87	tmr \|= (IOP_TMR_RELOAD \| IOP_TMR_EN);
469d3044 MP	88
469d3044 MP	89	write_tmr0(tmr);
8d778377 VK	90	return 0;
	91	}
	92
	93	static int iop_set_oneshot(struct clock_event_device *evt)
	94	{
	95	u32 tmr = read_tmr0();
	96
	97	/* ->set_next_event sets period and enables timer */
	98	tmr &= ~(IOP_TMR_RELOAD \| IOP_TMR_EN);
	99	write_tmr0(tmr);
	100	return 0;
	101	}
	102
	103	static int iop_shutdown(struct clock_event_device *evt)
	104	{
	105	u32 tmr = read_tmr0();
	106
	107	tmr &= ~IOP_TMR_EN;
	108	write_tmr0(tmr);
	109	return 0;
	110	}
	111
	112	static int iop_resume(struct clock_event_device *evt)
	113	{
	114	u32 tmr = read_tmr0();
	115
	116	tmr \|= IOP_TMR_EN;
	117	write_tmr0(tmr);
	118	return 0;
469d3044 MP	119	}
	120
	121	static struct clock_event_device iop_clockevent = {
8d778377 VK	122	.name = "iop_timer0",
	123	.features = CLOCK_EVT_FEAT_PERIODIC \|
	124	CLOCK_EVT_FEAT_ONESHOT,
	125	.rating = 300,
	126	.set_next_event = iop_set_next_event,
	127	.set_state_shutdown = iop_shutdown,
	128	.set_state_periodic = iop_set_periodic,
	129	.tick_resume = iop_resume,
	130	.set_state_oneshot = iop_set_oneshot,
469d3044 MP	131	};
469d3044 MP	132
48388b2a	133	static irqreturn_t
3668b45d	134	iop_timer_interrupt(int irq, void *dev_id)
48388b2a	135	{
469d3044	136	struct clock_event_device *evt = dev_id;
48388b2a	137
469d3044 MP	138	write_tisr(1);
469d3044 MP	139	evt->event_handler(evt);
48388b2a LB	140	return IRQ_HANDLED;
	141	}
	142
3668b45d DW	143	static struct irqaction iop_timer_irq = {
	144	.name = "IOP Timer Tick",
	145	.handler = iop_timer_interrupt,
78f6db99	146	.flags = IRQF_TIMER \| IRQF_IRQPOLL,
469d3044	147	.dev_id = &iop_clockevent,
48388b2a LB	148	};
48388b2a LB	149
70c14ff0 DW	150	static unsigned long iop_tick_rate;
	151	unsigned long get_iop_tick_rate(void)
	152	{
	153	return iop_tick_rate;
	154	}
	155	EXPORT_SYMBOL(get_iop_tick_rate);
	156
3668b45d	157	void __init iop_init_time(unsigned long tick_rate)
48388b2a LB	158	{
	159	u32 timer_ctl;
	160
c66af541	161	sched_clock_register(iop_read_sched_clock, 32, tick_rate);
08f26b1e	162
a692838d	163	ticks_per_jiffy = DIV_ROUND_CLOSEST(tick_rate, HZ);
70c14ff0	164	iop_tick_rate = tick_rate;
48388b2a	165
3668b45d DW	166	timer_ctl = IOP_TMR_EN \| IOP_TMR_PRIVILEGED \|
3668b45d DW	167	IOP_TMR_RELOAD \| IOP_TMR_RATIO_1_1;
48388b2a LB	168
48388b2a LB	169	/*
469d3044	170	* Set up interrupting clockevent timer 0.
48388b2a	171	*/
469d3044	172	write_tmr0(timer_ctl & ~IOP_TMR_EN);
40cc5244	173	write_tisr(1);
469d3044	174	setup_irq(IRQ_IOP_TIMER0, &iop_timer_irq);
469d3044	175	iop_clockevent.cpumask = cpumask_of(0);
838a2ae8 SG	176	clockevents_config_and_register(&iop_clockevent, tick_rate,
838a2ae8 SG	177	0xf, 0xfffffffe);
a91549a8 MP	178
	179	/*
	180	* Set up free-running clocksource timer 1.
	181	*/
3668b45d	182	write_trr1(0xffffffff);
a91549a8	183	write_tcr1(0xffffffff);
3668b45d	184	write_tmr1(timer_ctl);
d28b116b	185	clocksource_register_hz(&iop_clocksource, tick_rate);
48388b2a	186	}