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1 | /* |
2 | * Copyright (C) 2007 Lennert Buytenhek <buytenh@wantstofly.org> | |
3 | * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. | |
4 | */ | |
5 | ||
6 | /* | |
7 | * This program is free software; you can redistribute it and/or modify | |
8 | * it under the terms of the GNU General Public License version 2 as | |
9 | * published by the Free Software Foundation. | |
10 | */ | |
11 | ||
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12 | #include <mach/hardware.h> |
13 | ||
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14 | #define AVIC_NIMASK 0x04 |
15 | ||
52c543f9 QJ |
16 | @ this macro disables fast irq (not implemented) |
17 | .macro disable_fiq | |
18 | .endm | |
19 | ||
20 | .macro get_irqnr_preamble, base, tmp | |
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21 | ldr \base, =avic_base |
22 | ldr \base, [\base] | |
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23 | #ifdef CONFIG_MXC_IRQ_PRIOR |
24 | ldr r4, [\base, #AVIC_NIMASK] | |
25 | #endif | |
52c543f9 QJ |
26 | .endm |
27 | ||
28 | .macro arch_ret_to_user, tmp1, tmp2 | |
29 | .endm | |
30 | ||
31 | @ this macro checks which interrupt occured | |
32 | @ and returns its number in irqnr | |
33 | @ and returns if an interrupt occured in irqstat | |
34 | .macro get_irqnr_and_base, irqnr, irqstat, base, tmp | |
52c543f9 QJ |
35 | @ Load offset & priority of the highest priority |
36 | @ interrupt pending from AVIC_NIVECSR | |
37 | ldr \irqstat, [\base, #0x40] | |
38 | @ Shift to get the decoded IRQ number, using ASR so | |
39 | @ 'no interrupt pending' becomes 0xffffffff | |
40 | mov \irqnr, \irqstat, asr #16 | |
41 | @ set zero flag if IRQ + 1 == 0 | |
42 | adds \tmp, \irqnr, #1 | |
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43 | #ifdef CONFIG_MXC_IRQ_PRIOR |
44 | bicne \tmp, \irqstat, #0xFFFFFFE0 | |
45 | strne \tmp, [\base, #AVIC_NIMASK] | |
46 | streq r4, [\base, #AVIC_NIMASK] | |
47 | #endif | |
52c543f9 QJ |
48 | .endm |
49 | ||
50 | @ irq priority table (not used) | |
51 | .macro irq_prio_table | |
52 | .endm |