[deliverable/linux.git] / arch / arm / plat-mxc / include / mach / mx27.h

/*
 * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
 * Copyright 2008 Juergen Beisert, kernel@pengutronix.de
 *
 * This contains i.MX27-specific hardware definitions. For those
 * hardware pieces that are common between i.MX21 and i.MX27, have a
 * look at mx2x.h.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version 2
 * of the License, or (at your option) any later version.
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
 * MA  02110-1301, USA.
 */

#ifndef __MACH_MX27_H__
#define __MACH_MX27_H__

#ifndef __ASSEMBLER__
#include <linux/io.h>
#endif

#define MX27_AIPI_BASE_ADDR		0x10000000
#define MX27_AIPI_SIZE			SZ_1M
#define MX27_DMA_BASE_ADDR			(MX27_AIPI_BASE_ADDR + 0x01000)
#define MX27_WDOG_BASE_ADDR			(MX27_AIPI_BASE_ADDR + 0x02000)
#define MX27_GPT1_BASE_ADDR			(MX27_AIPI_BASE_ADDR + 0x03000)
#define MX27_GPT2_BASE_ADDR			(MX27_AIPI_BASE_ADDR + 0x04000)
#define MX27_GPT3_BASE_ADDR			(MX27_AIPI_BASE_ADDR + 0x05000)
#define MX27_PWM_BASE_ADDR			(MX27_AIPI_BASE_ADDR + 0x06000)
#define MX27_RTC_BASE_ADDR			(MX27_AIPI_BASE_ADDR + 0x07000)
#define MX27_KPP_BASE_ADDR			(MX27_AIPI_BASE_ADDR + 0x08000)
#define MX27_OWIRE_BASE_ADDR			(MX27_AIPI_BASE_ADDR + 0x09000)
#define MX27_UART1_BASE_ADDR			(MX27_AIPI_BASE_ADDR + 0x0a000)
#define MX27_UART2_BASE_ADDR			(MX27_AIPI_BASE_ADDR + 0x0b000)
#define MX27_UART3_BASE_ADDR			(MX27_AIPI_BASE_ADDR + 0x0c000)
#define MX27_UART4_BASE_ADDR			(MX27_AIPI_BASE_ADDR + 0x0d000)
#define MX27_CSPI1_BASE_ADDR			(MX27_AIPI_BASE_ADDR + 0x0e000)
#define MX27_CSPI2_BASE_ADDR			(MX27_AIPI_BASE_ADDR + 0x0f000)
#define MX27_SSI1_BASE_ADDR			(MX27_AIPI_BASE_ADDR + 0x10000)
#define MX27_SSI2_BASE_ADDR			(MX27_AIPI_BASE_ADDR + 0x11000)
#define MX27_I2C1_BASE_ADDR			(MX27_AIPI_BASE_ADDR + 0x12000)
#define MX27_SDHC1_BASE_ADDR			(MX27_AIPI_BASE_ADDR + 0x13000)
#define MX27_SDHC2_BASE_ADDR			(MX27_AIPI_BASE_ADDR + 0x14000)
#define MX27_GPIO_BASE_ADDR			(MX27_AIPI_BASE_ADDR + 0x15000)
#define MX27_AUDMUX_BASE_ADDR			(MX27_AIPI_BASE_ADDR + 0x16000)
#define MX27_CSPI3_BASE_ADDR			(MX27_AIPI_BASE_ADDR + 0x17000)
#define MX27_MSHC_BASE_ADDR			(MX27_AIPI_BASE_ADDR + 0x18000)
#define MX27_GPT5_BASE_ADDR			(MX27_AIPI_BASE_ADDR + 0x19000)
#define MX27_GPT4_BASE_ADDR			(MX27_AIPI_BASE_ADDR + 0x1a000)
#define MX27_UART5_BASE_ADDR			(MX27_AIPI_BASE_ADDR + 0x1b000)
#define MX27_UART6_BASE_ADDR			(MX27_AIPI_BASE_ADDR + 0x1c000)
#define MX27_I2C2_BASE_ADDR			(MX27_AIPI_BASE_ADDR + 0x1d000)
#define MX27_SDHC3_BASE_ADDR			(MX27_AIPI_BASE_ADDR + 0x1e000)
#define MX27_GPT6_BASE_ADDR			(MX27_AIPI_BASE_ADDR + 0x1f000)
#define MX27_LCDC_BASE_ADDR			(MX27_AIPI_BASE_ADDR + 0x21000)
#define MX27_SLCDC_BASE_ADDR			(MX27_AIPI_BASE_ADDR + 0x22000)
#define MX27_VPU_BASE_ADDR			(MX27_AIPI_BASE_ADDR + 0x23000)
#define MX27_USB_BASE_ADDR			(MX27_AIPI_BASE_ADDR + 0x24000)
#define MX27_USB_OTG_BASE_ADDR			(MX27_USB_BASE_ADDR + 0x0000)
#define MX27_USB_HS1_BASE_ADDR			(MX27_USB_BASE_ADDR + 0x0200)
#define MX27_USB_HS2_BASE_ADDR			(MX27_USB_BASE_ADDR + 0x0400)
#define MX27_SAHARA_BASE_ADDR			(MX27_AIPI_BASE_ADDR + 0x25000)
#define MX27_EMMAPP_BASE_ADDR			(MX27_AIPI_BASE_ADDR + 0x26000)
#define MX27_EMMAPRP_BASE_ADDR			(MX27_AIPI_BASE_ADDR + 0x26400)
#define MX27_CCM_BASE_ADDR			(MX27_AIPI_BASE_ADDR + 0x27000)
#define MX27_SYSCTRL_BASE_ADDR			(MX27_AIPI_BASE_ADDR + 0x27800)
#define MX27_IIM_BASE_ADDR			(MX27_AIPI_BASE_ADDR + 0x28000)
#define MX27_RTIC_BASE_ADDR			(MX27_AIPI_BASE_ADDR + 0x2a000)
#define MX27_FEC_BASE_ADDR			(MX27_AIPI_BASE_ADDR + 0x2b000)
#define MX27_SCC_BASE_ADDR			(MX27_AIPI_BASE_ADDR + 0x2c000)
#define MX27_ETB_BASE_ADDR			(MX27_AIPI_BASE_ADDR + 0x3b000)
#define MX27_ETB_RAM_BASE_ADDR			(MX27_AIPI_BASE_ADDR + 0x3c000)
#define MX27_JAM_BASE_ADDR			(MX27_AIPI_BASE_ADDR + 0x3e000)
#define MX27_MAX_BASE_ADDR			(MX27_AIPI_BASE_ADDR + 0x3f000)

#define MX27_AVIC_BASE_ADDR		0x10040000

/* ROM patch */
#define MX27_ROMP_BASE_ADDR		0x10041000

#define MX27_SAHB1_BASE_ADDR		0x80000000
#define MX27_SAHB1_SIZE			SZ_1M
#define MX27_CSI_BASE_ADDR			(MX27_SAHB1_BASE_ADDR + 0x0000)
#define MX27_ATA_BASE_ADDR			(MX27_SAHB1_BASE_ADDR + 0x1000)

/* Memory regions and CS */
#define MX27_SDRAM_BASE_ADDR		0xa0000000
#define MX27_CSD1_BASE_ADDR		0xb0000000

#define MX27_CS0_BASE_ADDR		0xc0000000
#define MX27_CS1_BASE_ADDR		0xc8000000
#define MX27_CS2_BASE_ADDR		0xd0000000
#define MX27_CS3_BASE_ADDR		0xd2000000
#define MX27_CS4_BASE_ADDR		0xd4000000
#define MX27_CS5_BASE_ADDR		0xd6000000

/* NAND, SDRAM, WEIM, M3IF, EMI controllers */
#define MX27_X_MEMC_BASE_ADDR		0xd8000000
#define MX27_X_MEMC_SIZE		SZ_1M
#define MX27_NFC_BASE_ADDR			(MX27_X_MEMC_BASE_ADDR)
#define MX27_SDRAMC_BASE_ADDR			(MX27_X_MEMC_BASE_ADDR + 0x1000)
#define MX27_WEIM_BASE_ADDR			(MX27_X_MEMC_BASE_ADDR + 0x2000)
#define MX27_M3IF_BASE_ADDR			(MX27_X_MEMC_BASE_ADDR + 0x3000)
#define MX27_PCMCIA_CTL_BASE_ADDR		(MX27_X_MEMC_BASE_ADDR + 0x4000)

#define MX27_WEIM_CSCRx_BASE_ADDR(cs)	(MX27_WEIM_BASE_ADDR + (cs) * 0x10)
#define MX27_WEIM_CSCRxU(cs)			(MX27_WEIM_CSCRx_BASE_ADDR(cs))
#define MX27_WEIM_CSCRxL(cs)			(MX27_WEIM_CSCRx_BASE_ADDR(cs) + 0x4)
#define MX27_WEIM_CSCRxA(cs)			(MX27_WEIM_CSCRx_BASE_ADDR(cs) + 0x8)

#define MX27_PCMCIA_MEM_BASE_ADDR	0xdc000000

/* IRAM */
#define MX27_IRAM_BASE_ADDR		0xffff4c00	/* internal ram */

#define MX27_IO_P2V(x)			IMX_IO_P2V(x)
#define MX27_IO_ADDRESS(x)		IOMEM(MX27_IO_P2V(x))

#ifndef __ASSEMBLER__
static inline void mx27_setup_weimcs(size_t cs,
		unsigned upper, unsigned lower, unsigned addional)
{
	__raw_writel(upper, MX27_IO_ADDRESS(MX27_WEIM_CSCRxU(cs)));
	__raw_writel(lower, MX27_IO_ADDRESS(MX27_WEIM_CSCRxL(cs)));
	__raw_writel(addional, MX27_IO_ADDRESS(MX27_WEIM_CSCRxA(cs)));
}
#endif

/* fixed interrupt numbers */
#define MX27_INT_I2C2		1
#define MX27_INT_GPT6		2
#define MX27_INT_GPT5		3
#define MX27_INT_GPT4		4
#define MX27_INT_RTIC		5
#define MX27_INT_CSPI3		6
#define MX27_INT_SDHC		7
#define MX27_INT_GPIO		8
#define MX27_INT_SDHC3		9
#define MX27_INT_SDHC2		10
#define MX27_INT_SDHC1		11
#define MX27_INT_I2C1		12
#define MX27_INT_SSI2		13
#define MX27_INT_SSI1		14
#define MX27_INT_CSPI2		15
#define MX27_INT_CSPI1		16
#define MX27_INT_UART4		17
#define MX27_INT_UART3		18
#define MX27_INT_UART2		19
#define MX27_INT_UART1		20
#define MX27_INT_KPP		21
#define MX27_INT_RTC		22
#define MX27_INT_PWM		23
#define MX27_INT_GPT3		24
#define MX27_INT_GPT2		25
#define MX27_INT_GPT1		26
#define MX27_INT_WDOG		27
#define MX27_INT_PCMCIA		28
#define MX27_INT_NFC		29
#define MX27_INT_ATA		30
#define MX27_INT_CSI		31
#define MX27_INT_DMACH0		32
#define MX27_INT_DMACH1		33
#define MX27_INT_DMACH2		34
#define MX27_INT_DMACH3		35
#define MX27_INT_DMACH4		36
#define MX27_INT_DMACH5		37
#define MX27_INT_DMACH6		38
#define MX27_INT_DMACH7		39
#define MX27_INT_DMACH8		40
#define MX27_INT_DMACH9		41
#define MX27_INT_DMACH10	42
#define MX27_INT_DMACH11	43
#define MX27_INT_DMACH12	44
#define MX27_INT_DMACH13	45
#define MX27_INT_DMACH14	46
#define MX27_INT_DMACH15	47
#define MX27_INT_UART6		48
#define MX27_INT_UART5		49
#define MX27_INT_FEC		50
#define MX27_INT_EMMAPRP	51
#define MX27_INT_EMMAPP		52
#define MX27_INT_VPU		53
#define MX27_INT_USB_HS1	54
#define MX27_INT_USB_HS2	55
#define MX27_INT_USB_OTG	56
#define MX27_INT_SCC_SMN	57
#define MX27_INT_SCC_SCM	58
#define MX27_INT_SAHARA		59
#define MX27_INT_SLCDC		60
#define MX27_INT_LCDC		61
#define MX27_INT_IIM		62
#define MX27_INT_CCM		63

/* fixed DMA request numbers */
#define MX27_DMA_REQ_CSPI3_RX	1
#define MX27_DMA_REQ_CSPI3_TX	2
#define MX27_DMA_REQ_EXT	3
#define MX27_DMA_REQ_MSHC	4
#define MX27_DMA_REQ_SDHC2	6
#define MX27_DMA_REQ_SDHC1	7
#define MX27_DMA_REQ_SSI2_RX0	8
#define MX27_DMA_REQ_SSI2_TX0	9
#define MX27_DMA_REQ_SSI2_RX1	10
#define MX27_DMA_REQ_SSI2_TX1	11
#define MX27_DMA_REQ_SSI1_RX0	12
#define MX27_DMA_REQ_SSI1_TX0	13
#define MX27_DMA_REQ_SSI1_RX1	14
#define MX27_DMA_REQ_SSI1_TX1	15
#define MX27_DMA_REQ_CSPI2_RX	16
#define MX27_DMA_REQ_CSPI2_TX	17
#define MX27_DMA_REQ_CSPI1_RX	18
#define MX27_DMA_REQ_CSPI1_TX	19
#define MX27_DMA_REQ_UART4_RX	20
#define MX27_DMA_REQ_UART4_TX	21
#define MX27_DMA_REQ_UART3_RX	22
#define MX27_DMA_REQ_UART3_TX	23
#define MX27_DMA_REQ_UART2_RX	24
#define MX27_DMA_REQ_UART2_TX	25
#define MX27_DMA_REQ_UART1_RX	26
#define MX27_DMA_REQ_UART1_TX	27
#define MX27_DMA_REQ_ATA_TX	28
#define MX27_DMA_REQ_ATA_RCV	29
#define MX27_DMA_REQ_CSI_STAT	30
#define MX27_DMA_REQ_CSI_RX	31
#define MX27_DMA_REQ_UART5_TX	32
#define MX27_DMA_REQ_UART5_RX	33
#define MX27_DMA_REQ_UART6_TX	34
#define MX27_DMA_REQ_UART6_RX	35
#define MX27_DMA_REQ_SDHC3	36
#define MX27_DMA_REQ_NFC	37

/* silicon revisions specific to i.MX27 */
#define CHIP_REV_1_0		0x00
#define CHIP_REV_2_0		0x01

#ifndef __ASSEMBLY__
extern int mx27_revision(void);
#endif

#endif /* ifndef __MACH_MX27_H__ */
Commit	Line	Data
f31405cc JB	1	/*
	2	* Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
	3	* Copyright 2008 Juergen Beisert, kernel@pengutronix.de
	4	*
260a1fd2 HS	5	* This contains i.MX27-specific hardware definitions. For those
	6	* hardware pieces that are common between i.MX21 and i.MX27, have a
	7	* look at mx2x.h.
	8	*
f31405cc JB	9	* This program is free software; you can redistribute it and/or
	10	* modify it under the terms of the GNU General Public License
	11	* as published by the Free Software Foundation; either version 2
	12	* of the License, or (at your option) any later version.
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
	21	* MA 02110-1301, USA.
	22	*/
	23
3cdd5441 UKK	24	#ifndef __MACH_MX27_H__
3cdd5441 UKK	25	#define __MACH_MX27_H__
f31405cc	26
a8dfb646 UKK	27	#ifndef __ASSEMBLER__
	28	#include <linux/io.h>
	29	#endif
	30
2ae959f4	31	#define MX27_AIPI_BASE_ADDR 0x10000000
2ae959f4 UKK	32	#define MX27_AIPI_SIZE SZ_1M
	33	#define MX27_DMA_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x01000)
	34	#define MX27_WDOG_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x02000)
	35	#define MX27_GPT1_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x03000)
	36	#define MX27_GPT2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x04000)
	37	#define MX27_GPT3_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x05000)
	38	#define MX27_PWM_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x06000)
	39	#define MX27_RTC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x07000)
	40	#define MX27_KPP_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x08000)
	41	#define MX27_OWIRE_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x09000)
	42	#define MX27_UART1_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x0a000)
	43	#define MX27_UART2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x0b000)
	44	#define MX27_UART3_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x0c000)
	45	#define MX27_UART4_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x0d000)
	46	#define MX27_CSPI1_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x0e000)
	47	#define MX27_CSPI2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x0f000)
	48	#define MX27_SSI1_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x10000)
	49	#define MX27_SSI2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x11000)
c6987159	50	#define MX27_I2C1_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x12000)
2ae959f4 UKK	51	#define MX27_SDHC1_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x13000)
	52	#define MX27_SDHC2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x14000)
	53	#define MX27_GPIO_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x15000)
	54	#define MX27_AUDMUX_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x16000)
	55	#define MX27_CSPI3_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x17000)
	56	#define MX27_MSHC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x18000)
	57	#define MX27_GPT5_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x19000)
	58	#define MX27_GPT4_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x1a000)
	59	#define MX27_UART5_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x1b000)
	60	#define MX27_UART6_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x1c000)
	61	#define MX27_I2C2_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x1d000)
	62	#define MX27_SDHC3_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x1e000)
	63	#define MX27_GPT6_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x1f000)
	64	#define MX27_LCDC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x21000)
	65	#define MX27_SLCDC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x22000)
	66	#define MX27_VPU_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x23000)
2eb42d5c UKK	67	#define MX27_USB_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x24000)
	68	#define MX27_USB_OTG_BASE_ADDR (MX27_USB_BASE_ADDR + 0x0000)
	69	#define MX27_USB_HS1_BASE_ADDR (MX27_USB_BASE_ADDR + 0x0200)
	70	#define MX27_USB_HS2_BASE_ADDR (MX27_USB_BASE_ADDR + 0x0400)
2ae959f4	71	#define MX27_SAHARA_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x25000)
b2997cb1 UKK	72	#define MX27_EMMAPP_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x26000)
b2997cb1 UKK	73	#define MX27_EMMAPRP_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x26400)
2ae959f4 UKK	74	#define MX27_CCM_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x27000)
	75	#define MX27_SYSCTRL_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x27800)
	76	#define MX27_IIM_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x28000)
	77	#define MX27_RTIC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x2a000)
	78	#define MX27_FEC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x2b000)
	79	#define MX27_SCC_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x2c000)
	80	#define MX27_ETB_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x3b000)
	81	#define MX27_ETB_RAM_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x3c000)
	82	#define MX27_JAM_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x3e000)
	83	#define MX27_MAX_BASE_ADDR (MX27_AIPI_BASE_ADDR + 0x3f000)
	84
	85	#define MX27_AVIC_BASE_ADDR 0x10040000
f31405cc	86
260a1fd2	87	/* ROM patch */
26b10e74	88	#define MX27_ROMP_BASE_ADDR 0x10041000
f31405cc	89
2ae959f4	90	#define MX27_SAHB1_BASE_ADDR 0x80000000
2ae959f4 UKK	91	#define MX27_SAHB1_SIZE SZ_1M
	92	#define MX27_CSI_BASE_ADDR (MX27_SAHB1_BASE_ADDR + 0x0000)
	93	#define MX27_ATA_BASE_ADDR (MX27_SAHB1_BASE_ADDR + 0x1000)
f31405cc	94
f31405cc	95	/* Memory regions and CS */
26b10e74 UKK	96	#define MX27_SDRAM_BASE_ADDR 0xa0000000
26b10e74 UKK	97	#define MX27_CSD1_BASE_ADDR 0xb0000000
f31405cc	98
26b10e74 UKK	99	#define MX27_CS0_BASE_ADDR 0xc0000000
	100	#define MX27_CS1_BASE_ADDR 0xc8000000
	101	#define MX27_CS2_BASE_ADDR 0xd0000000
	102	#define MX27_CS3_BASE_ADDR 0xd2000000
	103	#define MX27_CS4_BASE_ADDR 0xd4000000
	104	#define MX27_CS5_BASE_ADDR 0xd6000000
f31405cc	105
260a1fd2	106	/* NAND, SDRAM, WEIM, M3IF, EMI controllers */
26b10e74	107	#define MX27_X_MEMC_BASE_ADDR 0xd8000000
26b10e74 UKK	108	#define MX27_X_MEMC_SIZE SZ_1M
	109	#define MX27_NFC_BASE_ADDR (MX27_X_MEMC_BASE_ADDR)
	110	#define MX27_SDRAMC_BASE_ADDR (MX27_X_MEMC_BASE_ADDR + 0x1000)
	111	#define MX27_WEIM_BASE_ADDR (MX27_X_MEMC_BASE_ADDR + 0x2000)
	112	#define MX27_M3IF_BASE_ADDR (MX27_X_MEMC_BASE_ADDR + 0x3000)
	113	#define MX27_PCMCIA_CTL_BASE_ADDR (MX27_X_MEMC_BASE_ADDR + 0x4000)
f31405cc	114
a8dfb646 UKK	115	#define MX27_WEIM_CSCRx_BASE_ADDR(cs) (MX27_WEIM_BASE_ADDR + (cs) * 0x10)
	116	#define MX27_WEIM_CSCRxU(cs) (MX27_WEIM_CSCRx_BASE_ADDR(cs))
	117	#define MX27_WEIM_CSCRxL(cs) (MX27_WEIM_CSCRx_BASE_ADDR(cs) + 0x4)
	118	#define MX27_WEIM_CSCRxA(cs) (MX27_WEIM_CSCRx_BASE_ADDR(cs) + 0x8)
	119
26b10e74	120	#define MX27_PCMCIA_MEM_BASE_ADDR 0xdc000000
f73a42f7 UKK	121
f73a42f7 UKK	122	/* IRAM */
26b10e74	123	#define MX27_IRAM_BASE_ADDR 0xffff4c00 /* internal ram */
f73a42f7	124
a9963148	125	#define MX27_IO_P2V(x) IMX_IO_P2V(x)
f5d7a13b	126	#define MX27_IO_ADDRESS(x) IOMEM(MX27_IO_P2V(x))
bc9ea6c7	127
a8dfb646 UKK	128	#ifndef __ASSEMBLER__
	129	static inline void mx27_setup_weimcs(size_t cs,
	130	unsigned upper, unsigned lower, unsigned addional)
	131	{
	132	__raw_writel(upper, MX27_IO_ADDRESS(MX27_WEIM_CSCRxU(cs)));
	133	__raw_writel(lower, MX27_IO_ADDRESS(MX27_WEIM_CSCRxL(cs)));
	134	__raw_writel(addional, MX27_IO_ADDRESS(MX27_WEIM_CSCRxA(cs)));
	135	}
	136	#endif
	137
260a1fd2	138	/* fixed interrupt numbers */
26b10e74 UKK	139	#define MX27_INT_I2C2 1
	140	#define MX27_INT_GPT6 2
	141	#define MX27_INT_GPT5 3
	142	#define MX27_INT_GPT4 4
	143	#define MX27_INT_RTIC 5
2ae959f4	144	#define MX27_INT_CSPI3 6
26b10e74	145	#define MX27_INT_SDHC 7
2ae959f4	146	#define MX27_INT_GPIO 8
26b10e74	147	#define MX27_INT_SDHC3 9
2ae959f4 UKK	148	#define MX27_INT_SDHC2 10
2ae959f4 UKK	149	#define MX27_INT_SDHC1 11
c6987159	150	#define MX27_INT_I2C1 12
2ae959f4 UKK	151	#define MX27_INT_SSI2 13
	152	#define MX27_INT_SSI1 14
	153	#define MX27_INT_CSPI2 15
	154	#define MX27_INT_CSPI1 16
	155	#define MX27_INT_UART4 17
	156	#define MX27_INT_UART3 18
	157	#define MX27_INT_UART2 19
	158	#define MX27_INT_UART1 20
	159	#define MX27_INT_KPP 21
	160	#define MX27_INT_RTC 22
	161	#define MX27_INT_PWM 23
	162	#define MX27_INT_GPT3 24
	163	#define MX27_INT_GPT2 25
	164	#define MX27_INT_GPT1 26
	165	#define MX27_INT_WDOG 27
	166	#define MX27_INT_PCMCIA 28
00b57bf9	167	#define MX27_INT_NFC 29
26b10e74	168	#define MX27_INT_ATA 30
2ae959f4 UKK	169	#define MX27_INT_CSI 31
	170	#define MX27_INT_DMACH0 32
	171	#define MX27_INT_DMACH1 33
	172	#define MX27_INT_DMACH2 34
	173	#define MX27_INT_DMACH3 35
	174	#define MX27_INT_DMACH4 36
	175	#define MX27_INT_DMACH5 37
	176	#define MX27_INT_DMACH6 38
	177	#define MX27_INT_DMACH7 39
	178	#define MX27_INT_DMACH8 40
	179	#define MX27_INT_DMACH9 41
	180	#define MX27_INT_DMACH10 42
	181	#define MX27_INT_DMACH11 43
	182	#define MX27_INT_DMACH12 44
	183	#define MX27_INT_DMACH13 45
	184	#define MX27_INT_DMACH14 46
	185	#define MX27_INT_DMACH15 47
26b10e74 UKK	186	#define MX27_INT_UART6 48
	187	#define MX27_INT_UART5 49
	188	#define MX27_INT_FEC 50
2ae959f4 UKK	189	#define MX27_INT_EMMAPRP 51
2ae959f4 UKK	190	#define MX27_INT_EMMAPP 52
26b10e74	191	#define MX27_INT_VPU 53
2eb42d5c UKK	192	#define MX27_INT_USB_HS1 54
	193	#define MX27_INT_USB_HS2 55
	194	#define MX27_INT_USB_OTG 56
26b10e74 UKK	195	#define MX27_INT_SCC_SMN 57
	196	#define MX27_INT_SCC_SCM 58
	197	#define MX27_INT_SAHARA 59
2ae959f4 UKK	198	#define MX27_INT_SLCDC 60
2ae959f4 UKK	199	#define MX27_INT_LCDC 61
26b10e74 UKK	200	#define MX27_INT_IIM 62
26b10e74 UKK	201	#define MX27_INT_CCM 63
f31405cc JB	202
f31405cc JB	203	/* fixed DMA request numbers */
2ae959f4 UKK	204	#define MX27_DMA_REQ_CSPI3_RX 1
	205	#define MX27_DMA_REQ_CSPI3_TX 2
	206	#define MX27_DMA_REQ_EXT 3
26b10e74	207	#define MX27_DMA_REQ_MSHC 4
2ae959f4 UKK	208	#define MX27_DMA_REQ_SDHC2 6
	209	#define MX27_DMA_REQ_SDHC1 7
	210	#define MX27_DMA_REQ_SSI2_RX0 8
	211	#define MX27_DMA_REQ_SSI2_TX0 9
	212	#define MX27_DMA_REQ_SSI2_RX1 10
	213	#define MX27_DMA_REQ_SSI2_TX1 11
	214	#define MX27_DMA_REQ_SSI1_RX0 12
	215	#define MX27_DMA_REQ_SSI1_TX0 13
	216	#define MX27_DMA_REQ_SSI1_RX1 14
	217	#define MX27_DMA_REQ_SSI1_TX1 15
	218	#define MX27_DMA_REQ_CSPI2_RX 16
	219	#define MX27_DMA_REQ_CSPI2_TX 17
	220	#define MX27_DMA_REQ_CSPI1_RX 18
	221	#define MX27_DMA_REQ_CSPI1_TX 19
	222	#define MX27_DMA_REQ_UART4_RX 20
	223	#define MX27_DMA_REQ_UART4_TX 21
	224	#define MX27_DMA_REQ_UART3_RX 22
	225	#define MX27_DMA_REQ_UART3_TX 23
	226	#define MX27_DMA_REQ_UART2_RX 24
	227	#define MX27_DMA_REQ_UART2_TX 25
	228	#define MX27_DMA_REQ_UART1_RX 26
	229	#define MX27_DMA_REQ_UART1_TX 27
26b10e74 UKK	230	#define MX27_DMA_REQ_ATA_TX 28
26b10e74 UKK	231	#define MX27_DMA_REQ_ATA_RCV 29
2ae959f4 UKK	232	#define MX27_DMA_REQ_CSI_STAT 30
2ae959f4 UKK	233	#define MX27_DMA_REQ_CSI_RX 31
26b10e74 UKK	234	#define MX27_DMA_REQ_UART5_TX 32
	235	#define MX27_DMA_REQ_UART5_RX 33
	236	#define MX27_DMA_REQ_UART6_TX 34
	237	#define MX27_DMA_REQ_UART6_RX 35
	238	#define MX27_DMA_REQ_SDHC3 36
	239	#define MX27_DMA_REQ_NFC 37
f31405cc JB	240
	241	/* silicon revisions specific to i.MX27 */
	242	#define CHIP_REV_1_0 0x00
	243	#define CHIP_REV_2_0 0x01
	244
	245	#ifndef __ASSEMBLY__
	246	extern int mx27_revision(void);
	247	#endif
	248
3cdd5441	249	#endif /* ifndef __MACH_MX27_H__ */