projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 52c543f9 QJ |
1 | /* |
| 2 | * Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved. | |
| 3 | */ | |
| 4 | ||
| 5 | /* | |
| 6 | * This program is free software; you can redistribute it and/or modify | |
| 7 | * it under the terms of the GNU General Public License version 2 as | |
| 8 | * published by the Free Software Foundation. | |
| 9 | */ | |
| 10 | ||
| 11 | #include <linux/module.h> | |
| 12 | #include <linux/moduleparam.h> | |
| 13 | #include <linux/init.h> | |
| 14 | #include <linux/device.h> | |
| 15 | #include <linux/errno.h> | |
| 16 | #include <asm/hardware.h> | |
| 17 | #include <asm/io.h> | |
| 18 | #include <asm/irq.h> | |
| 19 | #include <asm/mach/irq.h> | |
| 20 | #include <asm/arch/common.h> | |
| 21 | ||
| 2c130fd5 | 22 | /* Disable interrupt number "irq" in the AVIC */ |
| 52c543f9 QJ |
23 | static void mxc_mask_irq(unsigned int irq) |
| 24 | { | |
| 25 | __raw_writel(irq, AVIC_INTDISNUM); | |
| 26 | } | |
| 27 | ||
| 2c130fd5 | 28 | /* Enable interrupt number "irq" in the AVIC */ |
| 52c543f9 QJ |
29 | static void mxc_unmask_irq(unsigned int irq) |
| 30 | { | |
| 31 | __raw_writel(irq, AVIC_INTENNUM); | |
| 32 | } | |
| 33 | ||
| 34 | static struct irq_chip mxc_avic_chip = { | |
| 35 | .mask_ack = mxc_mask_irq, | |
| 36 | .mask = mxc_mask_irq, | |
| 37 | .unmask = mxc_unmask_irq, | |
| 38 | }; | |
| 39 | ||
| 2c130fd5 | 40 | /* |
| 52c543f9 QJ |
41 | * This function initializes the AVIC hardware and disables all the |
| 42 | * interrupts. It registers the interrupt enable and disable functions | |
| 43 | * to the kernel for each interrupt source. | |
| 44 | */ | |
| 45 | void __init mxc_init_irq(void) | |
| 46 | { | |
| 47 | int i; | |
| 48 | u32 reg; | |
| 49 | ||
| 50 | /* put the AVIC into the reset value with | |
| 51 | * all interrupts disabled | |
| 52 | */ | |
| 53 | __raw_writel(0, AVIC_INTCNTL); | |
| 54 | __raw_writel(0x1f, AVIC_NIMASK); | |
| 55 | ||
| 56 | /* disable all interrupts */ | |
| 57 | __raw_writel(0, AVIC_INTENABLEH); | |
| 58 | __raw_writel(0, AVIC_INTENABLEL); | |
| 59 | ||
| 60 | /* all IRQ no FIQ */ | |
| 61 | __raw_writel(0, AVIC_INTTYPEH); | |
| 62 | __raw_writel(0, AVIC_INTTYPEL); | |
| 63 | for (i = 0; i < MXC_MAX_INT_LINES; i++) { | |
| 64 | set_irq_chip(i, &mxc_avic_chip); | |
| 65 | set_irq_handler(i, handle_level_irq); | |
| 66 | set_irq_flags(i, IRQF_VALID); | |
| 67 | } | |
| 68 | ||
| 69 | /* Set WDOG2's interrupt the highest priority level (bit 28-31) */ | |
| 70 | reg = __raw_readl(AVIC_NIPRIORITY6); | |
| 71 | reg |= (0xF << 28); | |
| 72 | __raw_writel(reg, AVIC_NIPRIORITY6); | |
| 73 | ||
| 74 | printk(KERN_INFO "MXC IRQ initialized\n"); | |
| 75 | } |