Commit | Line | Data |
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28ad94ec | 1 | /* |
a0719f52 | 2 | * linux/arch/arm/plat-nomadik/timer.c |
28ad94ec AR |
3 | * |
4 | * Copyright (C) 2008 STMicroelectronics | |
b102c01f | 5 | * Copyright (C) 2010 Alessandro Rubini |
8fbb97a2 | 6 | * Copyright (C) 2010 Linus Walleij for ST-Ericsson |
28ad94ec AR |
7 | * |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2, as | |
10 | * published by the Free Software Foundation. | |
11 | */ | |
12 | #include <linux/init.h> | |
13 | #include <linux/interrupt.h> | |
14 | #include <linux/irq.h> | |
15 | #include <linux/io.h> | |
16 | #include <linux/clockchips.h> | |
ba327b1e | 17 | #include <linux/clk.h> |
28ad94ec | 18 | #include <linux/jiffies.h> |
ba327b1e | 19 | #include <linux/err.h> |
5e06b649 | 20 | #include <linux/sched.h> |
28ad94ec | 21 | #include <asm/mach/time.h> |
ec05aa13 | 22 | #include <asm/sched_clock.h> |
28ad94ec | 23 | |
59b559d7 | 24 | #include <plat/mtu.h> |
28ad94ec | 25 | |
2f73a068 JA |
26 | static bool clkevt_periodic; |
27 | static u32 clk_prescale; | |
28 | static u32 nmdk_cycle; /* write-once */ | |
29 | ||
8fbb97a2 | 30 | void __iomem *mtu_base; /* Assigned by machine code */ |
2f73a068 | 31 | |
cba13830 | 32 | #ifdef CONFIG_NOMADIK_MTU_SCHED_CLOCK |
2a847513 LW |
33 | /* |
34 | * Override the global weak sched_clock symbol with this | |
35 | * local implementation which uses the clocksource to get some | |
8fbb97a2 | 36 | * better resolution when scheduling the kernel. |
2a847513 | 37 | */ |
ec05aa13 | 38 | static DEFINE_CLOCK_DATA(cd); |
8fbb97a2 | 39 | |
2a847513 LW |
40 | unsigned long long notrace sched_clock(void) |
41 | { | |
ec05aa13 | 42 | u32 cyc; |
8fbb97a2 LW |
43 | |
44 | if (unlikely(!mtu_base)) | |
45 | return 0; | |
46 | ||
ec05aa13 RK |
47 | cyc = -readl(mtu_base + MTU_VAL(0)); |
48 | return cyc_to_sched_clock(&cd, cyc, (u32)~0); | |
8fbb97a2 LW |
49 | } |
50 | ||
ec05aa13 | 51 | static void notrace nomadik_update_sched_clock(void) |
8fbb97a2 | 52 | { |
ec05aa13 RK |
53 | u32 cyc = -readl(mtu_base + MTU_VAL(0)); |
54 | update_sched_clock(&cd, cyc, (u32)~0); | |
2a847513 | 55 | } |
cba13830 | 56 | #endif |
2f73a068 | 57 | |
b102c01f | 58 | /* Clockevent device: use one-shot mode */ |
2f73a068 JA |
59 | static int nmdk_clkevt_next(unsigned long evt, struct clock_event_device *ev) |
60 | { | |
61 | writel(1 << 1, mtu_base + MTU_IMSC); | |
62 | writel(evt, mtu_base + MTU_LR(1)); | |
63 | /* Load highest value, enable device, enable interrupts */ | |
64 | writel(MTU_CRn_ONESHOT | clk_prescale | | |
65 | MTU_CRn_32BITS | MTU_CRn_ENA, | |
66 | mtu_base + MTU_CR(1)); | |
67 | ||
68 | return 0; | |
69 | } | |
70 | ||
71 | static void nmdk_clkevt_reset(void) | |
72 | { | |
73 | if (clkevt_periodic) { | |
74 | ||
75 | /* Timer: configure load and background-load, and fire it up */ | |
76 | writel(nmdk_cycle, mtu_base + MTU_LR(1)); | |
77 | writel(nmdk_cycle, mtu_base + MTU_BGLR(1)); | |
78 | ||
79 | writel(MTU_CRn_PERIODIC | clk_prescale | | |
80 | MTU_CRn_32BITS | MTU_CRn_ENA, | |
81 | mtu_base + MTU_CR(1)); | |
82 | writel(1 << 1, mtu_base + MTU_IMSC); | |
83 | } else { | |
84 | /* Generate an interrupt to start the clockevent again */ | |
85 | (void) nmdk_clkevt_next(nmdk_cycle, NULL); | |
86 | } | |
87 | } | |
88 | ||
28ad94ec AR |
89 | static void nmdk_clkevt_mode(enum clock_event_mode mode, |
90 | struct clock_event_device *dev) | |
91 | { | |
b102c01f | 92 | |
28ad94ec AR |
93 | switch (mode) { |
94 | case CLOCK_EVT_MODE_PERIODIC: | |
2f73a068 JA |
95 | clkevt_periodic = true; |
96 | nmdk_clkevt_reset(); | |
28ad94ec AR |
97 | break; |
98 | case CLOCK_EVT_MODE_ONESHOT: | |
2f73a068 | 99 | clkevt_periodic = false; |
b102c01f | 100 | break; |
28ad94ec AR |
101 | case CLOCK_EVT_MODE_SHUTDOWN: |
102 | case CLOCK_EVT_MODE_UNUSED: | |
b102c01f | 103 | writel(0, mtu_base + MTU_IMSC); |
2917947a | 104 | /* disable timer */ |
2f73a068 | 105 | writel(0, mtu_base + MTU_CR(1)); |
2917947a LW |
106 | /* load some high default value */ |
107 | writel(0xffffffff, mtu_base + MTU_LR(1)); | |
28ad94ec AR |
108 | break; |
109 | case CLOCK_EVT_MODE_RESUME: | |
110 | break; | |
111 | } | |
112 | } | |
113 | ||
114 | static struct clock_event_device nmdk_clkevt = { | |
b102c01f | 115 | .name = "mtu_1", |
2f73a068 | 116 | .features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC, |
b102c01f | 117 | .rating = 200, |
28ad94ec | 118 | .set_mode = nmdk_clkevt_mode, |
b102c01f | 119 | .set_next_event = nmdk_clkevt_next, |
28ad94ec AR |
120 | }; |
121 | ||
122 | /* | |
b102c01f | 123 | * IRQ Handler for timer 1 of the MTU block. |
28ad94ec AR |
124 | */ |
125 | static irqreturn_t nmdk_timer_interrupt(int irq, void *dev_id) | |
126 | { | |
b102c01f | 127 | struct clock_event_device *evdev = dev_id; |
28ad94ec | 128 | |
b102c01f AR |
129 | writel(1 << 1, mtu_base + MTU_ICR); /* Interrupt clear reg */ |
130 | evdev->event_handler(evdev); | |
28ad94ec AR |
131 | return IRQ_HANDLED; |
132 | } | |
133 | ||
28ad94ec AR |
134 | static struct irqaction nmdk_timer_irq = { |
135 | .name = "Nomadik Timer Tick", | |
136 | .flags = IRQF_DISABLED | IRQF_TIMER, | |
137 | .handler = nmdk_timer_interrupt, | |
b102c01f | 138 | .dev_id = &nmdk_clkevt, |
28ad94ec AR |
139 | }; |
140 | ||
2f73a068 JA |
141 | static void nmdk_clksrc_reset(void) |
142 | { | |
143 | /* Disable */ | |
144 | writel(0, mtu_base + MTU_CR(0)); | |
145 | ||
146 | /* ClockSource: configure load and background-load, and fire it up */ | |
147 | writel(nmdk_cycle, mtu_base + MTU_LR(0)); | |
148 | writel(nmdk_cycle, mtu_base + MTU_BGLR(0)); | |
149 | ||
150 | writel(clk_prescale | MTU_CRn_32BITS | MTU_CRn_ENA, | |
151 | mtu_base + MTU_CR(0)); | |
152 | } | |
153 | ||
59b559d7 | 154 | void __init nmdk_timer_init(void) |
28ad94ec | 155 | { |
28ad94ec | 156 | unsigned long rate; |
ba327b1e | 157 | struct clk *clk0; |
ba327b1e LW |
158 | |
159 | clk0 = clk_get_sys("mtu0", NULL); | |
160 | BUG_ON(IS_ERR(clk0)); | |
161 | ||
ba327b1e | 162 | clk_enable(clk0); |
b102c01f AR |
163 | |
164 | /* | |
a0719f52 LW |
165 | * Tick rate is 2.4MHz for Nomadik and 2.4Mhz, 100MHz or 133 MHz |
166 | * for ux500. | |
167 | * Use a divide-by-16 counter if the tick rate is more than 32MHz. | |
168 | * At 32 MHz, the timer (with 32 bit counter) can be programmed | |
169 | * to wake-up at a max 127s a head in time. Dividing a 2.4 MHz timer | |
170 | * with 16 gives too low timer resolution. | |
b102c01f | 171 | */ |
ba327b1e | 172 | rate = clk_get_rate(clk0); |
a0719f52 | 173 | if (rate > 32000000) { |
b102c01f | 174 | rate /= 16; |
2f73a068 | 175 | clk_prescale = MTU_CRn_PRESCALE_16; |
b102c01f | 176 | } else { |
2f73a068 | 177 | clk_prescale = MTU_CRn_PRESCALE_1; |
b102c01f | 178 | } |
28ad94ec | 179 | |
2f73a068 JA |
180 | nmdk_cycle = (rate + HZ/2) / HZ; |
181 | ||
182 | ||
b102c01f | 183 | /* Timer 0 is the free running clocksource */ |
2f73a068 | 184 | nmdk_clksrc_reset(); |
28ad94ec | 185 | |
bfe45e0b RK |
186 | if (clocksource_mmio_init(mtu_base + MTU_VAL(0), "mtu_0", |
187 | rate, 200, 32, clocksource_mmio_readl_down)) | |
b102c01f | 188 | pr_err("timer: failed to initialize clock source %s\n", |
bfe45e0b | 189 | "mtu_0"); |
cba13830 | 190 | #ifdef CONFIG_NOMADIK_MTU_SCHED_CLOCK |
ec05aa13 | 191 | init_sched_clock(&cd, nomadik_update_sched_clock, 32, rate); |
cba13830 | 192 | #endif |
99f76891 LW |
193 | /* Timer 1 is used for events */ |
194 | ||
2917947a LW |
195 | clockevents_calc_mult_shift(&nmdk_clkevt, rate, MTU_MIN_RANGE); |
196 | ||
b102c01f AR |
197 | nmdk_clkevt.max_delta_ns = |
198 | clockevent_delta2ns(0xffffffff, &nmdk_clkevt); | |
199 | nmdk_clkevt.min_delta_ns = | |
200 | clockevent_delta2ns(0x00000002, &nmdk_clkevt); | |
201 | nmdk_clkevt.cpumask = cpumask_of(0); | |
28ad94ec AR |
202 | |
203 | /* Register irq and clockevents */ | |
204 | setup_irq(IRQ_MTU0, &nmdk_timer_irq); | |
28ad94ec AR |
205 | clockevents_register_device(&nmdk_clkevt); |
206 | } |