[deliverable/linux.git] / arch / arm / plat-nomadik / timer.c

/*
 *  linux/arch/arm/plat-nomadik/timer.c
 *
 * Copyright (C) 2008 STMicroelectronics
 * Copyright (C) 2010 Alessandro Rubini
 * Copyright (C) 2010 Linus Walleij for ST-Ericsson
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2, as
 * published by the Free Software Foundation.
 */
#include <linux/init.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/io.h>
#include <linux/clockchips.h>
#include <linux/clk.h>
#include <linux/jiffies.h>
#include <linux/err.h>
#include <linux/sched.h>
#include <asm/mach/time.h>
#include <asm/sched_clock.h>

/*
 * Guaranteed runtime conversion range in seconds for
 * the clocksource and clockevent.
 */
#define MTU_MIN_RANGE 4

/*
 * The MTU device hosts four different counters, with 4 set of
 * registers. These are register names.
 */

#define MTU_IMSC	0x00	/* Interrupt mask set/clear */
#define MTU_RIS		0x04	/* Raw interrupt status */
#define MTU_MIS		0x08	/* Masked interrupt status */
#define MTU_ICR		0x0C	/* Interrupt clear register */

/* per-timer registers take 0..3 as argument */
#define MTU_LR(x)	(0x10 + 0x10 * (x) + 0x00)	/* Load value */
#define MTU_VAL(x)	(0x10 + 0x10 * (x) + 0x04)	/* Current value */
#define MTU_CR(x)	(0x10 + 0x10 * (x) + 0x08)	/* Control reg */
#define MTU_BGLR(x)	(0x10 + 0x10 * (x) + 0x0c)	/* At next overflow */

/* bits for the control register */
#define MTU_CRn_ENA		0x80
#define MTU_CRn_PERIODIC	0x40	/* if 0 = free-running */
#define MTU_CRn_PRESCALE_MASK	0x0c
#define MTU_CRn_PRESCALE_1		0x00
#define MTU_CRn_PRESCALE_16		0x04
#define MTU_CRn_PRESCALE_256		0x08
#define MTU_CRn_32BITS		0x02
#define MTU_CRn_ONESHOT		0x01	/* if 0 = wraps reloading from BGLR*/

/* Other registers are usual amba/primecell registers, currently not used */
#define MTU_ITCR	0xff0
#define MTU_ITOP	0xff4

#define MTU_PERIPH_ID0	0xfe0
#define MTU_PERIPH_ID1	0xfe4
#define MTU_PERIPH_ID2	0xfe8
#define MTU_PERIPH_ID3	0xfeC

#define MTU_PCELL0	0xff0
#define MTU_PCELL1	0xff4
#define MTU_PCELL2	0xff8
#define MTU_PCELL3	0xffC

static bool clkevt_periodic;
static u32 clk_prescale;
static u32 nmdk_cycle;		/* write-once */

void __iomem *mtu_base; /* Assigned by machine code */

#ifdef CONFIG_NOMADIK_MTU_SCHED_CLOCK
/*
 * Override the global weak sched_clock symbol with this
 * local implementation which uses the clocksource to get some
 * better resolution when scheduling the kernel.
 */
static DEFINE_CLOCK_DATA(cd);

unsigned long long notrace sched_clock(void)
{
	u32 cyc;

	if (unlikely(!mtu_base))
		return 0;

	cyc = -readl(mtu_base + MTU_VAL(0));
	return cyc_to_sched_clock(&cd, cyc, (u32)~0);
}

static void notrace nomadik_update_sched_clock(void)
{
	u32 cyc = -readl(mtu_base + MTU_VAL(0));
	update_sched_clock(&cd, cyc, (u32)~0);
}
#endif

/* Clockevent device: use one-shot mode */
static int nmdk_clkevt_next(unsigned long evt, struct clock_event_device *ev)
{
	writel(1 << 1, mtu_base + MTU_IMSC);
	writel(evt, mtu_base + MTU_LR(1));
	/* Load highest value, enable device, enable interrupts */
	writel(MTU_CRn_ONESHOT | clk_prescale |
	       MTU_CRn_32BITS | MTU_CRn_ENA,
	       mtu_base + MTU_CR(1));

	return 0;
}

void nmdk_clkevt_reset(void)
{
	if (clkevt_periodic) {

		/* Timer: configure load and background-load, and fire it up */
		writel(nmdk_cycle, mtu_base + MTU_LR(1));
		writel(nmdk_cycle, mtu_base + MTU_BGLR(1));

		writel(MTU_CRn_PERIODIC | clk_prescale |
		       MTU_CRn_32BITS | MTU_CRn_ENA,
		       mtu_base + MTU_CR(1));
		writel(1 << 1, mtu_base + MTU_IMSC);
	} else {
		/* Generate an interrupt to start the clockevent again */
		(void) nmdk_clkevt_next(nmdk_cycle, NULL);
	}
}

static void nmdk_clkevt_mode(enum clock_event_mode mode,
			     struct clock_event_device *dev)
{

	switch (mode) {
	case CLOCK_EVT_MODE_PERIODIC:
		clkevt_periodic = true;
		nmdk_clkevt_reset();
		break;
	case CLOCK_EVT_MODE_ONESHOT:
		clkevt_periodic = false;
		break;
	case CLOCK_EVT_MODE_SHUTDOWN:
	case CLOCK_EVT_MODE_UNUSED:
		writel(0, mtu_base + MTU_IMSC);
		/* disable timer */
		writel(0, mtu_base + MTU_CR(1));
		/* load some high default value */
		writel(0xffffffff, mtu_base + MTU_LR(1));
		break;
	case CLOCK_EVT_MODE_RESUME:
		break;
	}
}

static struct clock_event_device nmdk_clkevt = {
	.name		= "mtu_1",
	.features	= CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC,
	.rating		= 200,
	.set_mode	= nmdk_clkevt_mode,
	.set_next_event	= nmdk_clkevt_next,
};

/*
 * IRQ Handler for timer 1 of the MTU block.
 */
static irqreturn_t nmdk_timer_interrupt(int irq, void *dev_id)
{
	struct clock_event_device *evdev = dev_id;

	writel(1 << 1, mtu_base + MTU_ICR); /* Interrupt clear reg */
	evdev->event_handler(evdev);
	return IRQ_HANDLED;
}

static struct irqaction nmdk_timer_irq = {
	.name		= "Nomadik Timer Tick",
	.flags		= IRQF_DISABLED | IRQF_TIMER,
	.handler	= nmdk_timer_interrupt,
	.dev_id		= &nmdk_clkevt,
};

void nmdk_clksrc_reset(void)
{
	/* Disable */
	writel(0, mtu_base + MTU_CR(0));

	/* ClockSource: configure load and background-load, and fire it up */
	writel(nmdk_cycle, mtu_base + MTU_LR(0));
	writel(nmdk_cycle, mtu_base + MTU_BGLR(0));

	writel(clk_prescale | MTU_CRn_32BITS | MTU_CRn_ENA,
	       mtu_base + MTU_CR(0));
}

void __init nmdk_timer_init(void)
{
	unsigned long rate;
	struct clk *clk0;

	clk0 = clk_get_sys("mtu0", NULL);
	BUG_ON(IS_ERR(clk0));

	clk_enable(clk0);

	/*
	 * Tick rate is 2.4MHz for Nomadik and 2.4Mhz, 100MHz or 133 MHz
	 * for ux500.
	 * Use a divide-by-16 counter if the tick rate is more than 32MHz.
	 * At 32 MHz, the timer (with 32 bit counter) can be programmed
	 * to wake-up at a max 127s a head in time. Dividing a 2.4 MHz timer
	 * with 16 gives too low timer resolution.
	 */
	rate = clk_get_rate(clk0);
	if (rate > 32000000) {
		rate /= 16;
		clk_prescale = MTU_CRn_PRESCALE_16;
	} else {
		clk_prescale = MTU_CRn_PRESCALE_1;
	}

	nmdk_cycle = (rate + HZ/2) / HZ;


	/* Timer 0 is the free running clocksource */
	nmdk_clksrc_reset();

	if (clocksource_mmio_init(mtu_base + MTU_VAL(0), "mtu_0",
			rate, 200, 32, clocksource_mmio_readl_down))
		pr_err("timer: failed to initialize clock source %s\n",
		       "mtu_0");
#ifdef CONFIG_NOMADIK_MTU_SCHED_CLOCK
	init_sched_clock(&cd, nomadik_update_sched_clock, 32, rate);
#endif
	/* Timer 1 is used for events */

	clockevents_calc_mult_shift(&nmdk_clkevt, rate, MTU_MIN_RANGE);

	nmdk_clkevt.max_delta_ns =
		clockevent_delta2ns(0xffffffff, &nmdk_clkevt);
	nmdk_clkevt.min_delta_ns =
		clockevent_delta2ns(0x00000002, &nmdk_clkevt);
	nmdk_clkevt.cpumask	= cpumask_of(0);

	/* Register irq and clockevents */
	setup_irq(IRQ_MTU0, &nmdk_timer_irq);
	clockevents_register_device(&nmdk_clkevt);
}
Commit	Line	Data
28ad94ec	1	/*
a0719f52	2	* linux/arch/arm/plat-nomadik/timer.c
28ad94ec AR	3	*
28ad94ec AR	4	* Copyright (C) 2008 STMicroelectronics
b102c01f	5	* Copyright (C) 2010 Alessandro Rubini
8fbb97a2	6	* Copyright (C) 2010 Linus Walleij for ST-Ericsson
28ad94ec AR	7	*
	8	* This program is free software; you can redistribute it and/or modify
	9	* it under the terms of the GNU General Public License version 2, as
	10	* published by the Free Software Foundation.
	11	*/
	12	#include <linux/init.h>
	13	#include <linux/interrupt.h>
	14	#include <linux/irq.h>
	15	#include <linux/io.h>
	16	#include <linux/clockchips.h>
ba327b1e	17	#include <linux/clk.h>
28ad94ec	18	#include <linux/jiffies.h>
ba327b1e	19	#include <linux/err.h>
5e06b649	20	#include <linux/sched.h>
28ad94ec	21	#include <asm/mach/time.h>
ec05aa13	22	#include <asm/sched_clock.h>
28ad94ec	23
05387a9f JA	24	/*
	25	* Guaranteed runtime conversion range in seconds for
	26	* the clocksource and clockevent.
	27	*/
	28	#define MTU_MIN_RANGE 4
	29
	30	/*
	31	* The MTU device hosts four different counters, with 4 set of
	32	* registers. These are register names.
	33	*/
	34
	35	#define MTU_IMSC 0x00 /* Interrupt mask set/clear */
	36	#define MTU_RIS 0x04 /* Raw interrupt status */
	37	#define MTU_MIS 0x08 /* Masked interrupt status */
	38	#define MTU_ICR 0x0C /* Interrupt clear register */
	39
	40	/* per-timer registers take 0..3 as argument */
	41	#define MTU_LR(x) (0x10 + 0x10 * (x) + 0x00) /* Load value */
	42	#define MTU_VAL(x) (0x10 + 0x10 * (x) + 0x04) /* Current value */
	43	#define MTU_CR(x) (0x10 + 0x10 * (x) + 0x08) /* Control reg */
	44	#define MTU_BGLR(x) (0x10 + 0x10 * (x) + 0x0c) /* At next overflow */
	45
	46	/* bits for the control register */
	47	#define MTU_CRn_ENA 0x80
	48	#define MTU_CRn_PERIODIC 0x40 /* if 0 = free-running */
	49	#define MTU_CRn_PRESCALE_MASK 0x0c
	50	#define MTU_CRn_PRESCALE_1 0x00
	51	#define MTU_CRn_PRESCALE_16 0x04
	52	#define MTU_CRn_PRESCALE_256 0x08
	53	#define MTU_CRn_32BITS 0x02
	54	#define MTU_CRn_ONESHOT 0x01 /* if 0 = wraps reloading from BGLR*/
	55
	56	/* Other registers are usual amba/primecell registers, currently not used */
	57	#define MTU_ITCR 0xff0
	58	#define MTU_ITOP 0xff4
	59
	60	#define MTU_PERIPH_ID0 0xfe0
	61	#define MTU_PERIPH_ID1 0xfe4
	62	#define MTU_PERIPH_ID2 0xfe8
	63	#define MTU_PERIPH_ID3 0xfeC
	64
	65	#define MTU_PCELL0 0xff0
	66	#define MTU_PCELL1 0xff4
	67	#define MTU_PCELL2 0xff8
	68	#define MTU_PCELL3 0xffC
28ad94ec	69
2f73a068 JA	70	static bool clkevt_periodic;
	71	static u32 clk_prescale;
	72	static u32 nmdk_cycle; /* write-once */
	73
8fbb97a2	74	void __iomem mtu_base; / Assigned by machine code */
2f73a068	75
cba13830	76	#ifdef CONFIG_NOMADIK_MTU_SCHED_CLOCK
2a847513 LW	77	/*
	78	* Override the global weak sched_clock symbol with this
	79	* local implementation which uses the clocksource to get some
8fbb97a2	80	* better resolution when scheduling the kernel.
2a847513	81	*/
ec05aa13	82	static DEFINE_CLOCK_DATA(cd);
8fbb97a2	83
2a847513 LW	84	unsigned long long notrace sched_clock(void)
2a847513 LW	85	{
ec05aa13	86	u32 cyc;
8fbb97a2 LW	87
	88	if (unlikely(!mtu_base))
	89	return 0;
	90
ec05aa13 RK	91	cyc = -readl(mtu_base + MTU_VAL(0));
ec05aa13 RK	92	return cyc_to_sched_clock(&cd, cyc, (u32)~0);
8fbb97a2 LW	93	}
8fbb97a2 LW	94
ec05aa13	95	static void notrace nomadik_update_sched_clock(void)
8fbb97a2	96	{
ec05aa13 RK	97	u32 cyc = -readl(mtu_base + MTU_VAL(0));
ec05aa13 RK	98	update_sched_clock(&cd, cyc, (u32)~0);
2a847513	99	}
cba13830	100	#endif
2f73a068	101
b102c01f	102	/* Clockevent device: use one-shot mode */
2f73a068 JA	103	static int nmdk_clkevt_next(unsigned long evt, struct clock_event_device *ev)
	104	{
	105	writel(1 << 1, mtu_base + MTU_IMSC);
	106	writel(evt, mtu_base + MTU_LR(1));
	107	/* Load highest value, enable device, enable interrupts */
	108	writel(MTU_CRn_ONESHOT \| clk_prescale \|
	109	MTU_CRn_32BITS \| MTU_CRn_ENA,
	110	mtu_base + MTU_CR(1));
	111
	112	return 0;
	113	}
	114
05387a9f	115	void nmdk_clkevt_reset(void)
2f73a068 JA	116	{
	117	if (clkevt_periodic) {
	118
	119	/* Timer: configure load and background-load, and fire it up */
	120	writel(nmdk_cycle, mtu_base + MTU_LR(1));
	121	writel(nmdk_cycle, mtu_base + MTU_BGLR(1));
	122
	123	writel(MTU_CRn_PERIODIC \| clk_prescale \|
	124	MTU_CRn_32BITS \| MTU_CRn_ENA,
	125	mtu_base + MTU_CR(1));
	126	writel(1 << 1, mtu_base + MTU_IMSC);
	127	} else {
	128	/* Generate an interrupt to start the clockevent again */
	129	(void) nmdk_clkevt_next(nmdk_cycle, NULL);
	130	}
	131	}
	132
28ad94ec AR	133	static void nmdk_clkevt_mode(enum clock_event_mode mode,
	134	struct clock_event_device *dev)
	135	{
b102c01f	136
28ad94ec AR	137	switch (mode) {
28ad94ec AR	138	case CLOCK_EVT_MODE_PERIODIC:
2f73a068 JA	139	clkevt_periodic = true;
2f73a068 JA	140	nmdk_clkevt_reset();
28ad94ec AR	141	break;
28ad94ec AR	142	case CLOCK_EVT_MODE_ONESHOT:
2f73a068	143	clkevt_periodic = false;
b102c01f	144	break;
28ad94ec AR	145	case CLOCK_EVT_MODE_SHUTDOWN:
28ad94ec AR	146	case CLOCK_EVT_MODE_UNUSED:
b102c01f	147	writel(0, mtu_base + MTU_IMSC);
2917947a	148	/* disable timer */
2f73a068	149	writel(0, mtu_base + MTU_CR(1));
2917947a LW	150	/* load some high default value */
2917947a LW	151	writel(0xffffffff, mtu_base + MTU_LR(1));
28ad94ec AR	152	break;
	153	case CLOCK_EVT_MODE_RESUME:
	154	break;
	155	}
	156	}
	157
	158	static struct clock_event_device nmdk_clkevt = {
b102c01f	159	.name = "mtu_1",
2f73a068	160	.features = CLOCK_EVT_FEAT_ONESHOT \| CLOCK_EVT_FEAT_PERIODIC,
b102c01f	161	.rating = 200,
28ad94ec	162	.set_mode = nmdk_clkevt_mode,
b102c01f	163	.set_next_event = nmdk_clkevt_next,
28ad94ec AR	164	};
	165
	166	/*
b102c01f	167	* IRQ Handler for timer 1 of the MTU block.
28ad94ec AR	168	*/
	169	static irqreturn_t nmdk_timer_interrupt(int irq, void *dev_id)
	170	{
b102c01f	171	struct clock_event_device *evdev = dev_id;
28ad94ec	172
b102c01f AR	173	writel(1 << 1, mtu_base + MTU_ICR); /* Interrupt clear reg */
b102c01f AR	174	evdev->event_handler(evdev);
28ad94ec AR	175	return IRQ_HANDLED;
	176	}
	177
28ad94ec AR	178	static struct irqaction nmdk_timer_irq = {
	179	.name = "Nomadik Timer Tick",
	180	.flags = IRQF_DISABLED \| IRQF_TIMER,
	181	.handler = nmdk_timer_interrupt,
b102c01f	182	.dev_id = &nmdk_clkevt,
28ad94ec AR	183	};
28ad94ec AR	184
05387a9f	185	void nmdk_clksrc_reset(void)
2f73a068 JA	186	{
	187	/* Disable */
	188	writel(0, mtu_base + MTU_CR(0));
	189
	190	/* ClockSource: configure load and background-load, and fire it up */
	191	writel(nmdk_cycle, mtu_base + MTU_LR(0));
	192	writel(nmdk_cycle, mtu_base + MTU_BGLR(0));
	193
	194	writel(clk_prescale \| MTU_CRn_32BITS \| MTU_CRn_ENA,
	195	mtu_base + MTU_CR(0));
	196	}
	197
59b559d7	198	void __init nmdk_timer_init(void)
28ad94ec	199	{
28ad94ec	200	unsigned long rate;
ba327b1e	201	struct clk *clk0;
ba327b1e LW	202
	203	clk0 = clk_get_sys("mtu0", NULL);
	204	BUG_ON(IS_ERR(clk0));
	205
ba327b1e	206	clk_enable(clk0);
b102c01f AR	207
b102c01f AR	208	/*
a0719f52 LW	209	* Tick rate is 2.4MHz for Nomadik and 2.4Mhz, 100MHz or 133 MHz
	210	* for ux500.
	211	* Use a divide-by-16 counter if the tick rate is more than 32MHz.
	212	* At 32 MHz, the timer (with 32 bit counter) can be programmed
	213	* to wake-up at a max 127s a head in time. Dividing a 2.4 MHz timer
	214	* with 16 gives too low timer resolution.
b102c01f	215	*/
ba327b1e	216	rate = clk_get_rate(clk0);
a0719f52	217	if (rate > 32000000) {
b102c01f	218	rate /= 16;
2f73a068	219	clk_prescale = MTU_CRn_PRESCALE_16;
b102c01f	220	} else {
2f73a068	221	clk_prescale = MTU_CRn_PRESCALE_1;
b102c01f	222	}
28ad94ec	223
2f73a068 JA	224	nmdk_cycle = (rate + HZ/2) / HZ;
	225
	226
b102c01f	227	/* Timer 0 is the free running clocksource */
2f73a068	228	nmdk_clksrc_reset();
28ad94ec	229
bfe45e0b RK	230	if (clocksource_mmio_init(mtu_base + MTU_VAL(0), "mtu_0",
bfe45e0b RK	231	rate, 200, 32, clocksource_mmio_readl_down))
b102c01f	232	pr_err("timer: failed to initialize clock source %s\n",
bfe45e0b	233	"mtu_0");
cba13830	234	#ifdef CONFIG_NOMADIK_MTU_SCHED_CLOCK
ec05aa13	235	init_sched_clock(&cd, nomadik_update_sched_clock, 32, rate);
cba13830	236	#endif
99f76891 LW	237	/* Timer 1 is used for events */
99f76891 LW	238
2917947a LW	239	clockevents_calc_mult_shift(&nmdk_clkevt, rate, MTU_MIN_RANGE);
2917947a LW	240
b102c01f AR	241	nmdk_clkevt.max_delta_ns =
	242	clockevent_delta2ns(0xffffffff, &nmdk_clkevt);
	243	nmdk_clkevt.min_delta_ns =
	244	clockevent_delta2ns(0x00000002, &nmdk_clkevt);
	245	nmdk_clkevt.cpumask = cpumask_of(0);
28ad94ec AR	246
	247	/* Register irq and clockevents */
	248	setup_irq(IRQ_MTU0, &nmdk_timer_irq);
28ad94ec AR	249	clockevents_register_device(&nmdk_clkevt);
28ad94ec AR	250	}