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omap: headers: Move remaining headers from include/mach to include/plat
[deliverable/linux.git] / arch / arm / plat-omap / dma.c
CommitLineData
5e1c5ff4
TL		 1/*
2 * linux/arch/arm/plat-omap/dma.c
3 *
97b7f715 4 * Copyright (C) 2003 - 2008 Nokia Corporation
96de0e25 5 * Author: Juha Yrjölä <juha.yrjola@nokia.com>
5e1c5ff4
TL		 6 * DMA channel linking for 1610 by Samuel Ortiz <samuel.ortiz@nokia.com>
7 * Graphics DMA and LCD DMA graphics tranformations
8 * by Imre Deak <imre.deak@nokia.com>
f8151e5c 9 * OMAP2/3 support Copyright (C) 2004-2007 Texas Instruments, Inc.
1a8bfa1e 10 * Merged to support both OMAP1 and OMAP2 by Tony Lindgren <tony@atomide.com>
5e1c5ff4
TL		 11 * Some functions based on earlier dma-omap.c Copyright (C) 2001 RidgeRun, Inc.
12 *
44169075
SS		 13 * Copyright (C) 2009 Texas Instruments
14 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
15 *
5e1c5ff4
TL		 16 * Support functions for the OMAP internal DMA channels.
17 *
18 * This program is free software; you can redistribute it and/or modify
19 * it under the terms of the GNU General Public License version 2 as
20 * published by the Free Software Foundation.
21 *
22 */
23
24#include <linux/module.h>
25#include <linux/init.h>
26#include <linux/sched.h>
27#include <linux/spinlock.h>
28#include <linux/errno.h>
29#include <linux/interrupt.h>
418ca1f0 30#include <linux/irq.h>
97b7f715 31#include <linux/io.h>
5e1c5ff4
TL		 32
33#include <asm/system.h>
a09e64fb 34#include <mach/hardware.h>
ce491cf8 35#include <plat/dma.h>
5e1c5ff4 36
ce491cf8 37#include <plat/tc.h>
5e1c5ff4 38
f8151e5c
AG		 39#undef DEBUG
40
41#ifndef CONFIG_ARCH_OMAP1
42enum { DMA_CH_ALLOC_DONE, DMA_CH_PARAMS_SET_DONE, DMA_CH_STARTED,
43 DMA_CH_QUEUED, DMA_CH_NOTSTARTED, DMA_CH_PAUSED, DMA_CH_LINK_ENABLED
44};
45
46enum { DMA_CHAIN_STARTED, DMA_CHAIN_NOTSTARTED };
1a8bfa1e 47#endif
5e1c5ff4 48
97b7f715
TL		 49#define OMAP_DMA_ACTIVE 0x01
50#define OMAP_DMA_CCR_EN (1 << 7)
7ff879db 51#define OMAP2_DMA_CSR_CLEAR_MASK 0xffe
5e1c5ff4 52
97b7f715 53#define OMAP_FUNC_MUX_ARM_BASE (0xfffe1000 + 0xec)
5e1c5ff4 54
97b7f715 55static int enable_1510_mode;
5e1c5ff4
TL		 56
57struct omap_dma_lch {
58 int next_lch;
59 int dev_id;
60 u16 saved_csr;
61 u16 enabled_irqs;
62 const char *dev_name;
97b7f715 63 void (*callback)(int lch, u16 ch_status, void *data);
5e1c5ff4 64 void *data;
f8151e5c
AG		 65
66#ifndef CONFIG_ARCH_OMAP1
67 /* required for Dynamic chaining */
68 int prev_linked_ch;
69 int next_linked_ch;
70 int state;
71 int chain_id;
72
73 int status;
74#endif
5e1c5ff4
TL		 75 long flags;
76};
77
f8151e5c
AG		 78struct dma_link_info {
79 int *linked_dmach_q;
80 int no_of_lchs_linked;
81
82 int q_count;
83 int q_tail;
84 int q_head;
85
86 int chain_state;
87 int chain_mode;
88
89};
90
4d96372e
TL		 91static struct dma_link_info *dma_linked_lch;
92
93#ifndef CONFIG_ARCH_OMAP1
f8151e5c
AG		 94
95/* Chain handling macros */
96#define OMAP_DMA_CHAIN_QINIT(chain_id) \
97 do { \
98 dma_linked_lch[chain_id].q_head = \
99 dma_linked_lch[chain_id].q_tail = \
100 dma_linked_lch[chain_id].q_count = 0; \
101 } while (0)
102#define OMAP_DMA_CHAIN_QFULL(chain_id) \
103 (dma_linked_lch[chain_id].no_of_lchs_linked == \
104 dma_linked_lch[chain_id].q_count)
105#define OMAP_DMA_CHAIN_QLAST(chain_id) \
106 do { \
107 ((dma_linked_lch[chain_id].no_of_lchs_linked-1) == \
108 dma_linked_lch[chain_id].q_count) \
109 } while (0)
110#define OMAP_DMA_CHAIN_QEMPTY(chain_id) \
111 (0 == dma_linked_lch[chain_id].q_count)
112#define __OMAP_DMA_CHAIN_INCQ(end) \
113 ((end) = ((end)+1) % dma_linked_lch[chain_id].no_of_lchs_linked)
114#define OMAP_DMA_CHAIN_INCQHEAD(chain_id) \
115 do { \
116 __OMAP_DMA_CHAIN_INCQ(dma_linked_lch[chain_id].q_head); \
117 dma_linked_lch[chain_id].q_count--; \
118 } while (0)
119
120#define OMAP_DMA_CHAIN_INCQTAIL(chain_id) \
121 do { \
122 __OMAP_DMA_CHAIN_INCQ(dma_linked_lch[chain_id].q_tail); \
123 dma_linked_lch[chain_id].q_count++; \
124 } while (0)
125#endif
4d96372e
TL		 126
127static int dma_lch_count;
5e1c5ff4 128static int dma_chan_count;
2263f022 129static int omap_dma_reserve_channels;
5e1c5ff4
TL		 130
131static spinlock_t dma_chan_lock;
4d96372e 132static struct omap_dma_lch *dma_chan;
0499bdeb 133static void __iomem *omap_dma_base;
5e1c5ff4 134
4d96372e 135static const u8 omap1_dma_irq[OMAP1_LOGICAL_DMA_CH_COUNT] = {
5e1c5ff4
TL		 136 INT_DMA_CH0_6, INT_DMA_CH1_7, INT_DMA_CH2_8, INT_DMA_CH3,
137 INT_DMA_CH4, INT_DMA_CH5, INT_1610_DMA_CH6, INT_1610_DMA_CH7,
138 INT_1610_DMA_CH8, INT_1610_DMA_CH9, INT_1610_DMA_CH10,
139 INT_1610_DMA_CH11, INT_1610_DMA_CH12, INT_1610_DMA_CH13,
140 INT_1610_DMA_CH14, INT_1610_DMA_CH15, INT_DMA_LCD
141};
142
f8151e5c
AG		 143static inline void disable_lnk(int lch);
144static void omap_disable_channel_irq(int lch);
145static inline void omap_enable_channel_irq(int lch);
146
1a8bfa1e 147#define REVISIT_24XX() printk(KERN_ERR "FIXME: no %s on 24xx\n", \
8e86f427 148 __func__);
1a8bfa1e 149
0499bdeb
TL		 150#define dma_read(reg) \
151({ \
152 u32 __val; \
153 if (cpu_class_is_omap1()) \
154 __val = __raw_readw(omap_dma_base + OMAP1_DMA_##reg); \
155 else \
156 __val = __raw_readl(omap_dma_base + OMAP_DMA4_##reg); \
157 __val; \
158})
159
160#define dma_write(val, reg) \
161({ \
162 if (cpu_class_is_omap1()) \
163 __raw_writew((u16)(val), omap_dma_base + OMAP1_DMA_##reg); \
164 else \
165 __raw_writel((val), omap_dma_base + OMAP_DMA4_##reg); \
166})
167
1a8bfa1e
TL		 168#ifdef CONFIG_ARCH_OMAP15XX
169/* Returns 1 if the DMA module is in OMAP1510-compatible mode, 0 otherwise */
170int omap_dma_in_1510_mode(void)
171{
172 return enable_1510_mode;
173}
174#else
175#define omap_dma_in_1510_mode() 0
176#endif
177
178#ifdef CONFIG_ARCH_OMAP1
5e1c5ff4
TL		 179static inline int get_gdma_dev(int req)
180{
181 u32 reg = OMAP_FUNC_MUX_ARM_BASE + ((req - 1) / 5) * 4;
182 int shift = ((req - 1) % 5) * 6;
183
184 return ((omap_readl(reg) >> shift) & 0x3f) + 1;
185}
186
187static inline void set_gdma_dev(int req, int dev)
188{
189 u32 reg = OMAP_FUNC_MUX_ARM_BASE + ((req - 1) / 5) * 4;
190 int shift = ((req - 1) % 5) * 6;
191 u32 l;
192
193 l = omap_readl(reg);
194 l &= ~(0x3f << shift);
195 l |= (dev - 1) << shift;
196 omap_writel(l, reg);
197}
1a8bfa1e
TL		 198#else
199#define set_gdma_dev(req, dev) do {} while (0)
200#endif
5e1c5ff4 201
0499bdeb 202/* Omap1 only */
5e1c5ff4
TL		 203static void clear_lch_regs(int lch)
204{
205 int i;
0499bdeb 206 void __iomem *lch_base = omap_dma_base + OMAP1_DMA_CH_BASE(lch);
5e1c5ff4
TL		 207
208 for (i = 0; i < 0x2c; i += 2)
0499bdeb 209 __raw_writew(0, lch_base + i);
5e1c5ff4
TL		 210}
211
709eb3e5 212void omap_set_dma_priority(int lch, int dst_port, int priority)
5e1c5ff4
TL		 213{
214 unsigned long reg;
215 u32 l;
216
709eb3e5
TL		 217 if (cpu_class_is_omap1()) {
218 switch (dst_port) {
219 case OMAP_DMA_PORT_OCP_T1: /* FFFECC00 */
220 reg = OMAP_TC_OCPT1_PRIOR;
221 break;
222 case OMAP_DMA_PORT_OCP_T2: /* FFFECCD0 */
223 reg = OMAP_TC_OCPT2_PRIOR;
224 break;
225 case OMAP_DMA_PORT_EMIFF: /* FFFECC08 */
226 reg = OMAP_TC_EMIFF_PRIOR;
227 break;
228 case OMAP_DMA_PORT_EMIFS: /* FFFECC04 */
229 reg = OMAP_TC_EMIFS_PRIOR;
230 break;
231 default:
232 BUG();
233 return;
234 }
235 l = omap_readl(reg);
236 l &= ~(0xf << 8);
237 l |= (priority & 0xf) << 8;
238 omap_writel(l, reg);
239 }
240
f8151e5c 241 if (cpu_class_is_omap2()) {
0499bdeb
TL		 242 u32 ccr;
243
244 ccr = dma_read(CCR(lch));
709eb3e5 245 if (priority)
0499bdeb 246 ccr |= (1 << 6);
709eb3e5 247 else
0499bdeb
TL		 248 ccr &= ~(1 << 6);
249 dma_write(ccr, CCR(lch));
5e1c5ff4 250 }
5e1c5ff4 251}
97b7f715 252EXPORT_SYMBOL(omap_set_dma_priority);
5e1c5ff4
TL		 253
254void omap_set_dma_transfer_params(int lch, int data_type, int elem_count,
1a8bfa1e
TL		 255 int frame_count, int sync_mode,
256 int dma_trigger, int src_or_dst_synch)
5e1c5ff4 257{
0499bdeb
TL		 258 u32 l;
259
260 l = dma_read(CSDP(lch));
261 l &= ~0x03;
262 l |= data_type;
263 dma_write(l, CSDP(lch));
5e1c5ff4 264
1a8bfa1e 265 if (cpu_class_is_omap1()) {
0499bdeb
TL		 266 u16 ccr;
267
268 ccr = dma_read(CCR(lch));
269 ccr &= ~(1 << 5);
1a8bfa1e 270 if (sync_mode == OMAP_DMA_SYNC_FRAME)
0499bdeb
TL		 271 ccr |= 1 << 5;
272 dma_write(ccr, CCR(lch));
1a8bfa1e 273
0499bdeb
TL		 274 ccr = dma_read(CCR2(lch));
275 ccr &= ~(1 << 2);
1a8bfa1e 276 if (sync_mode == OMAP_DMA_SYNC_BLOCK)
0499bdeb
TL		 277 ccr |= 1 << 2;
278 dma_write(ccr, CCR2(lch));
1a8bfa1e
TL		 279 }
280
f8151e5c 281 if (cpu_class_is_omap2() && dma_trigger) {
0499bdeb 282 u32 val;
1a8bfa1e 283
0499bdeb 284 val = dma_read(CCR(lch));
4b3cf448
AG		 285
286 /* DMA_SYNCHRO_CONTROL_UPPER depends on the channel number */
287 val &= ~((3 << 19) | 0x1f);
288 val |= (dma_trigger & ~0x1f) << 14;
289 val |= dma_trigger & 0x1f;
5e1c5ff4 290
1a8bfa1e
TL		 291 if (sync_mode & OMAP_DMA_SYNC_FRAME)
292 val |= 1 << 5;
eca9e56e
PU		 293 else
294 val &= ~(1 << 5);
5e1c5ff4 295
1a8bfa1e
TL		 296 if (sync_mode & OMAP_DMA_SYNC_BLOCK)
297 val |= 1 << 18;
eca9e56e
PU		 298 else
299 val &= ~(1 << 18);
5e1c5ff4 300
1a8bfa1e
TL		 301 if (src_or_dst_synch)
302 val |= 1 << 24; /* source synch */
303 else
304 val &= ~(1 << 24); /* dest synch */
305
0499bdeb 306 dma_write(val, CCR(lch));
1a8bfa1e
TL		 307 }
308
0499bdeb
TL		 309 dma_write(elem_count, CEN(lch));
310 dma_write(frame_count, CFN(lch));
5e1c5ff4 311}
97b7f715 312EXPORT_SYMBOL(omap_set_dma_transfer_params);
1a8bfa1e 313
5e1c5ff4
TL		 314void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode, u32 color)
315{
5e1c5ff4
TL		 316 BUG_ON(omap_dma_in_1510_mode());
317
0815f8ea
TV		 318 if (cpu_class_is_omap1()) {
319 u16 w;
1a8bfa1e 320
0815f8ea
TV		 321 w = dma_read(CCR2(lch));
322 w &= ~0x03;
323
324 switch (mode) {
325 case OMAP_DMA_CONSTANT_FILL:
326 w |= 0x01;
327 break;
328 case OMAP_DMA_TRANSPARENT_COPY:
329 w |= 0x02;
330 break;
331 case OMAP_DMA_COLOR_DIS:
332 break;
333 default:
334 BUG();
335 }
336 dma_write(w, CCR2(lch));
337
338 w = dma_read(LCH_CTRL(lch));
339 w &= ~0x0f;
340 /* Default is channel type 2D */
341 if (mode) {
342 dma_write((u16)color, COLOR_L(lch));
343 dma_write((u16)(color >> 16), COLOR_U(lch));
344 w |= 1; /* Channel type G */
345 }
346 dma_write(w, LCH_CTRL(lch));
5e1c5ff4 347 }
0815f8ea
TV		 348
349 if (cpu_class_is_omap2()) {
350 u32 val;
351
352 val = dma_read(CCR(lch));
353 val &= ~((1 << 17) | (1 << 16));
354
355 switch (mode) {
356 case OMAP_DMA_CONSTANT_FILL:
357 val |= 1 << 16;
358 break;
359 case OMAP_DMA_TRANSPARENT_COPY:
360 val |= 1 << 17;
361 break;
362 case OMAP_DMA_COLOR_DIS:
363 break;
364 default:
365 BUG();
366 }
367 dma_write(val, CCR(lch));
368
369 color &= 0xffffff;
370 dma_write(color, COLOR(lch));
5e1c5ff4 371 }
5e1c5ff4 372}
97b7f715 373EXPORT_SYMBOL(omap_set_dma_color_mode);
5e1c5ff4 374
709eb3e5
TL		 375void omap_set_dma_write_mode(int lch, enum omap_dma_write_mode mode)
376{
f8151e5c 377 if (cpu_class_is_omap2()) {
0499bdeb
TL		 378 u32 csdp;
379
380 csdp = dma_read(CSDP(lch));
381 csdp &= ~(0x3 << 16);
382 csdp |= (mode << 16);
383 dma_write(csdp, CSDP(lch));
709eb3e5
TL		 384 }
385}
97b7f715 386EXPORT_SYMBOL(omap_set_dma_write_mode);
709eb3e5 387
0499bdeb
TL		 388void omap_set_dma_channel_mode(int lch, enum omap_dma_channel_mode mode)
389{
390 if (cpu_class_is_omap1() && !cpu_is_omap15xx()) {
391 u32 l;
392
393 l = dma_read(LCH_CTRL(lch));
394 l &= ~0x7;
395 l |= mode;
396 dma_write(l, LCH_CTRL(lch));
397 }
398}
399EXPORT_SYMBOL(omap_set_dma_channel_mode);
400
1a8bfa1e 401/* Note that src_port is only for omap1 */
5e1c5ff4 402void omap_set_dma_src_params(int lch, int src_port, int src_amode,
1a8bfa1e
TL		 403 unsigned long src_start,
404 int src_ei, int src_fi)
5e1c5ff4 405{
97b7f715
TL		 406 u32 l;
407
1a8bfa1e 408 if (cpu_class_is_omap1()) {
0499bdeb 409 u16 w;
1a8bfa1e 410
0499bdeb
TL		 411 w = dma_read(CSDP(lch));
412 w &= ~(0x1f << 2);
413 w |= src_port << 2;
414 dma_write(w, CSDP(lch));
97b7f715 415 }
1a8bfa1e 416
97b7f715
TL		 417 l = dma_read(CCR(lch));
418 l &= ~(0x03 << 12);
419 l |= src_amode << 12;
420 dma_write(l, CCR(lch));
0499bdeb 421
97b7f715 422 if (cpu_class_is_omap1()) {
0499bdeb
TL		 423 dma_write(src_start >> 16, CSSA_U(lch));
424 dma_write((u16)src_start, CSSA_L(lch));
1a8bfa1e 425 }
5e1c5ff4 426
97b7f715 427 if (cpu_class_is_omap2())
0499bdeb 428 dma_write(src_start, CSSA(lch));
97b7f715
TL		 429
430 dma_write(src_ei, CSEI(lch));
431 dma_write(src_fi, CSFI(lch));
1a8bfa1e 432}
97b7f715 433EXPORT_SYMBOL(omap_set_dma_src_params);
5e1c5ff4 434
97b7f715 435void omap_set_dma_params(int lch, struct omap_dma_channel_params *params)
1a8bfa1e
TL		 436{
437 omap_set_dma_transfer_params(lch, params->data_type,
438 params->elem_count, params->frame_count,
439 params->sync_mode, params->trigger,
440 params->src_or_dst_synch);
441 omap_set_dma_src_params(lch, params->src_port,
442 params->src_amode, params->src_start,
443 params->src_ei, params->src_fi);
444
445 omap_set_dma_dest_params(lch, params->dst_port,
446 params->dst_amode, params->dst_start,
447 params->dst_ei, params->dst_fi);
f8151e5c
AG		 448 if (params->read_prio || params->write_prio)
449 omap_dma_set_prio_lch(lch, params->read_prio,
450 params->write_prio);
5e1c5ff4 451}
97b7f715 452EXPORT_SYMBOL(omap_set_dma_params);
5e1c5ff4
TL		 453
454void omap_set_dma_src_index(int lch, int eidx, int fidx)
455{
97b7f715 456 if (cpu_class_is_omap2())
1a8bfa1e 457 return;
97b7f715 458
0499bdeb
TL		 459 dma_write(eidx, CSEI(lch));
460 dma_write(fidx, CSFI(lch));
5e1c5ff4 461}
97b7f715 462EXPORT_SYMBOL(omap_set_dma_src_index);
5e1c5ff4
TL		 463
464void omap_set_dma_src_data_pack(int lch, int enable)
465{
0499bdeb
TL		 466 u32 l;
467
468 l = dma_read(CSDP(lch));
469 l &= ~(1 << 6);
1a8bfa1e 470 if (enable)
0499bdeb
TL		 471 l |= (1 << 6);
472 dma_write(l, CSDP(lch));
5e1c5ff4 473}
97b7f715 474EXPORT_SYMBOL(omap_set_dma_src_data_pack);
5e1c5ff4
TL		 475
476void omap_set_dma_src_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
477{
6dc3c8f2 478 unsigned int burst = 0;
0499bdeb
TL		 479 u32 l;
480
481 l = dma_read(CSDP(lch));
482 l &= ~(0x03 << 7);
5e1c5ff4 483
5e1c5ff4
TL		 484 switch (burst_mode) {
485 case OMAP_DMA_DATA_BURST_DIS:
486 break;
487 case OMAP_DMA_DATA_BURST_4:
f8151e5c 488 if (cpu_class_is_omap2())
6dc3c8f2
KP		 489 burst = 0x1;
490 else
491 burst = 0x2;
5e1c5ff4
TL		 492 break;
493 case OMAP_DMA_DATA_BURST_8:
f8151e5c 494 if (cpu_class_is_omap2()) {
6dc3c8f2
KP		 495 burst = 0x2;
496 break;
497 }
498 /* not supported by current hardware on OMAP1
5e1c5ff4
TL		 499 * w |= (0x03 << 7);
500 * fall through
501 */
6dc3c8f2 502 case OMAP_DMA_DATA_BURST_16:
f8151e5c 503 if (cpu_class_is_omap2()) {
6dc3c8f2
KP		 504 burst = 0x3;
505 break;
506 }
507 /* OMAP1 don't support burst 16
508 * fall through
509 */
5e1c5ff4
TL		 510 default:
511 BUG();
512 }
0499bdeb
TL		 513
514 l |= (burst << 7);
515 dma_write(l, CSDP(lch));
5e1c5ff4 516}
97b7f715 517EXPORT_SYMBOL(omap_set_dma_src_burst_mode);
5e1c5ff4 518
1a8bfa1e 519/* Note that dest_port is only for OMAP1 */
5e1c5ff4 520void omap_set_dma_dest_params(int lch, int dest_port, int dest_amode,
1a8bfa1e
TL		 521 unsigned long dest_start,
522 int dst_ei, int dst_fi)
5e1c5ff4 523{
0499bdeb
TL		 524 u32 l;
525
1a8bfa1e 526 if (cpu_class_is_omap1()) {
0499bdeb
TL		 527 l = dma_read(CSDP(lch));
528 l &= ~(0x1f << 9);
529 l |= dest_port << 9;
530 dma_write(l, CSDP(lch));
1a8bfa1e 531 }
5e1c5ff4 532
0499bdeb
TL		 533 l = dma_read(CCR(lch));
534 l &= ~(0x03 << 14);
535 l |= dest_amode << 14;
536 dma_write(l, CCR(lch));
1a8bfa1e
TL		 537
538 if (cpu_class_is_omap1()) {
0499bdeb
TL		 539 dma_write(dest_start >> 16, CDSA_U(lch));
540 dma_write(dest_start, CDSA_L(lch));
1a8bfa1e 541 }
5e1c5ff4 542
f8151e5c 543 if (cpu_class_is_omap2())
0499bdeb 544 dma_write(dest_start, CDSA(lch));
5e1c5ff4 545
0499bdeb
TL		 546 dma_write(dst_ei, CDEI(lch));
547 dma_write(dst_fi, CDFI(lch));
5e1c5ff4 548}
97b7f715 549EXPORT_SYMBOL(omap_set_dma_dest_params);
5e1c5ff4
TL		 550
551void omap_set_dma_dest_index(int lch, int eidx, int fidx)
552{
97b7f715 553 if (cpu_class_is_omap2())
1a8bfa1e 554 return;
97b7f715 555
0499bdeb
TL		 556 dma_write(eidx, CDEI(lch));
557 dma_write(fidx, CDFI(lch));
5e1c5ff4 558}
97b7f715 559EXPORT_SYMBOL(omap_set_dma_dest_index);
5e1c5ff4
TL		 560
561void omap_set_dma_dest_data_pack(int lch, int enable)
562{
0499bdeb
TL		 563 u32 l;
564
565 l = dma_read(CSDP(lch));
566 l &= ~(1 << 13);
1a8bfa1e 567 if (enable)
0499bdeb
TL		 568 l |= 1 << 13;
569 dma_write(l, CSDP(lch));
5e1c5ff4 570}
97b7f715 571EXPORT_SYMBOL(omap_set_dma_dest_data_pack);
5e1c5ff4
TL		 572
573void omap_set_dma_dest_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
574{
6dc3c8f2 575 unsigned int burst = 0;
0499bdeb
TL		 576 u32 l;
577
578 l = dma_read(CSDP(lch));
579 l &= ~(0x03 << 14);
5e1c5ff4 580
5e1c5ff4
TL		 581 switch (burst_mode) {
582 case OMAP_DMA_DATA_BURST_DIS:
583 break;
584 case OMAP_DMA_DATA_BURST_4:
f8151e5c 585 if (cpu_class_is_omap2())
6dc3c8f2
KP		 586 burst = 0x1;
587 else
588 burst = 0x2;
5e1c5ff4
TL		 589 break;
590 case OMAP_DMA_DATA_BURST_8:
f8151e5c 591 if (cpu_class_is_omap2())
6dc3c8f2
KP		 592 burst = 0x2;
593 else
594 burst = 0x3;
5e1c5ff4 595 break;
6dc3c8f2 596 case OMAP_DMA_DATA_BURST_16:
f8151e5c 597 if (cpu_class_is_omap2()) {
6dc3c8f2
KP		 598 burst = 0x3;
599 break;
600 }
601 /* OMAP1 don't support burst 16
602 * fall through
603 */
5e1c5ff4
TL		 604 default:
605 printk(KERN_ERR "Invalid DMA burst mode\n");
606 BUG();
607 return;
608 }
0499bdeb
TL		 609 l |= (burst << 14);
610 dma_write(l, CSDP(lch));
5e1c5ff4 611}
97b7f715 612EXPORT_SYMBOL(omap_set_dma_dest_burst_mode);
5e1c5ff4 613
1a8bfa1e 614static inline void omap_enable_channel_irq(int lch)
5e1c5ff4 615{
1a8bfa1e 616 u32 status;
5e1c5ff4 617
7ff879db
TL		 618 /* Clear CSR */
619 if (cpu_class_is_omap1())
0499bdeb 620 status = dma_read(CSR(lch));
f8151e5c 621 else if (cpu_class_is_omap2())
0499bdeb 622 dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR(lch));
1a8bfa1e 623
5e1c5ff4 624 /* Enable some nice interrupts. */
0499bdeb 625 dma_write(dma_chan[lch].enabled_irqs, CICR(lch));
5e1c5ff4
TL		 626}
627
1a8bfa1e 628static void omap_disable_channel_irq(int lch)
5e1c5ff4 629{
f8151e5c 630 if (cpu_class_is_omap2())
0499bdeb 631 dma_write(0, CICR(lch));
1a8bfa1e
TL		 632}
633
634void omap_enable_dma_irq(int lch, u16 bits)
635{
636 dma_chan[lch].enabled_irqs |= bits;
637}
97b7f715 638EXPORT_SYMBOL(omap_enable_dma_irq);
5e1c5ff4 639
1a8bfa1e
TL		 640void omap_disable_dma_irq(int lch, u16 bits)
641{
642 dma_chan[lch].enabled_irqs &= ~bits;
643}
97b7f715 644EXPORT_SYMBOL(omap_disable_dma_irq);
1a8bfa1e
TL		 645
646static inline void enable_lnk(int lch)
647{
0499bdeb
TL		 648 u32 l;
649
650 l = dma_read(CLNK_CTRL(lch));
651
1a8bfa1e 652 if (cpu_class_is_omap1())
0499bdeb 653 l &= ~(1 << 14);
5e1c5ff4 654
1a8bfa1e 655 /* Set the ENABLE_LNK bits */
5e1c5ff4 656 if (dma_chan[lch].next_lch != -1)
0499bdeb 657 l = dma_chan[lch].next_lch | (1 << 15);
f8151e5c
AG		 658
659#ifndef CONFIG_ARCH_OMAP1
97b7f715
TL		 660 if (cpu_class_is_omap2())
661 if (dma_chan[lch].next_linked_ch != -1)
662 l = dma_chan[lch].next_linked_ch | (1 << 15);
f8151e5c 663#endif
0499bdeb
TL		 664
665 dma_write(l, CLNK_CTRL(lch));
5e1c5ff4
TL		 666}
667
668static inline void disable_lnk(int lch)
669{
0499bdeb
TL		 670 u32 l;
671
672 l = dma_read(CLNK_CTRL(lch));
673
5e1c5ff4 674 /* Disable interrupts */
1a8bfa1e 675 if (cpu_class_is_omap1()) {
0499bdeb 676 dma_write(0, CICR(lch));
1a8bfa1e 677 /* Set the STOP_LNK bit */
0499bdeb 678 l |= 1 << 14;
1a8bfa1e 679 }
5e1c5ff4 680
f8151e5c 681 if (cpu_class_is_omap2()) {
1a8bfa1e
TL		 682 omap_disable_channel_irq(lch);
683 /* Clear the ENABLE_LNK bit */
0499bdeb 684 l &= ~(1 << 15);
1a8bfa1e 685 }
5e1c5ff4 686
0499bdeb 687 dma_write(l, CLNK_CTRL(lch));
5e1c5ff4
TL		 688 dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE;
689}
690
1a8bfa1e 691static inline void omap2_enable_irq_lch(int lch)
5e1c5ff4 692{
1a8bfa1e
TL		 693 u32 val;
694
f8151e5c 695 if (!cpu_class_is_omap2())
1a8bfa1e
TL		 696 return;
697
0499bdeb 698 val = dma_read(IRQENABLE_L0);
1a8bfa1e 699 val |= 1 << lch;
0499bdeb 700 dma_write(val, IRQENABLE_L0);
1a8bfa1e
TL		 701}
702
703int omap_request_dma(int dev_id, const char *dev_name,
97b7f715 704 void (*callback)(int lch, u16 ch_status, void *data),
1a8bfa1e
TL		 705 void *data, int *dma_ch_out)
706{
707 int ch, free_ch = -1;
708 unsigned long flags;
709 struct omap_dma_lch *chan;
710
711 spin_lock_irqsave(&dma_chan_lock, flags);
712 for (ch = 0; ch < dma_chan_count; ch++) {
713 if (free_ch == -1 && dma_chan[ch].dev_id == -1) {
714 free_ch = ch;
715 if (dev_id == 0)
716 break;
717 }
718 }
719 if (free_ch == -1) {
720 spin_unlock_irqrestore(&dma_chan_lock, flags);
721 return -EBUSY;
722 }
723 chan = dma_chan + free_ch;
724 chan->dev_id = dev_id;
725
726 if (cpu_class_is_omap1())
727 clear_lch_regs(free_ch);
5e1c5ff4 728
f8151e5c 729 if (cpu_class_is_omap2())
1a8bfa1e
TL		 730 omap_clear_dma(free_ch);
731
732 spin_unlock_irqrestore(&dma_chan_lock, flags);
733
734 chan->dev_name = dev_name;
735 chan->callback = callback;
736 chan->data = data;
a92fda19 737 chan->flags = 0;
97b7f715 738
f8151e5c 739#ifndef CONFIG_ARCH_OMAP1
97b7f715
TL		 740 if (cpu_class_is_omap2()) {
741 chan->chain_id = -1;
742 chan->next_linked_ch = -1;
743 }
f8151e5c 744#endif
97b7f715 745
7ff879db 746 chan->enabled_irqs = OMAP_DMA_DROP_IRQ | OMAP_DMA_BLOCK_IRQ;
1a8bfa1e 747
7ff879db
TL		 748 if (cpu_class_is_omap1())
749 chan->enabled_irqs |= OMAP1_DMA_TOUT_IRQ;
f8151e5c 750 else if (cpu_class_is_omap2())
7ff879db
TL		 751 chan->enabled_irqs |= OMAP2_DMA_MISALIGNED_ERR_IRQ |
752 OMAP2_DMA_TRANS_ERR_IRQ;
1a8bfa1e
TL		 753
754 if (cpu_is_omap16xx()) {
755 /* If the sync device is set, configure it dynamically. */
756 if (dev_id != 0) {
757 set_gdma_dev(free_ch + 1, dev_id);
758 dev_id = free_ch + 1;
759 }
97b7f715
TL		 760 /*
761 * Disable the 1510 compatibility mode and set the sync device
762 * id.
763 */
0499bdeb 764 dma_write(dev_id | (1 << 10), CCR(free_ch));
557096fe 765 } else if (cpu_is_omap7xx() || cpu_is_omap15xx()) {
0499bdeb 766 dma_write(dev_id, CCR(free_ch));
1a8bfa1e
TL		 767 }
768
f8151e5c 769 if (cpu_class_is_omap2()) {
1a8bfa1e 770 omap2_enable_irq_lch(free_ch);
1a8bfa1e
TL		 771 omap_enable_channel_irq(free_ch);
772 /* Clear the CSR register and IRQ status register */
0499bdeb
TL		 773 dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR(free_ch));
774 dma_write(1 << free_ch, IRQSTATUS_L0);
1a8bfa1e
TL		 775 }
776
777 *dma_ch_out = free_ch;
778
779 return 0;
780}
97b7f715 781EXPORT_SYMBOL(omap_request_dma);
1a8bfa1e
TL		 782
783void omap_free_dma(int lch)
784{
785 unsigned long flags;
786
1a8bfa1e 787 if (dma_chan[lch].dev_id == -1) {
97b7f715 788 pr_err("omap_dma: trying to free unallocated DMA channel %d\n",
1a8bfa1e 789 lch);
1a8bfa1e
TL		 790 return;
791 }
97b7f715 792
1a8bfa1e
TL		 793 if (cpu_class_is_omap1()) {
794 /* Disable all DMA interrupts for the channel. */
0499bdeb 795 dma_write(0, CICR(lch));
1a8bfa1e 796 /* Make sure the DMA transfer is stopped. */
0499bdeb 797 dma_write(0, CCR(lch));
1a8bfa1e
TL		 798 }
799
f8151e5c 800 if (cpu_class_is_omap2()) {
1a8bfa1e
TL		 801 u32 val;
802 /* Disable interrupts */
0499bdeb 803 val = dma_read(IRQENABLE_L0);
1a8bfa1e 804 val &= ~(1 << lch);
0499bdeb 805 dma_write(val, IRQENABLE_L0);
1a8bfa1e
TL		 806
807 /* Clear the CSR register and IRQ status register */
0499bdeb
TL		 808 dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR(lch));
809 dma_write(1 << lch, IRQSTATUS_L0);
1a8bfa1e
TL		 810
811 /* Disable all DMA interrupts for the channel. */
0499bdeb 812 dma_write(0, CICR(lch));
1a8bfa1e
TL		 813
814 /* Make sure the DMA transfer is stopped. */
0499bdeb 815 dma_write(0, CCR(lch));
1a8bfa1e
TL		 816 omap_clear_dma(lch);
817 }
da1b94e6
SS		 818
819 spin_lock_irqsave(&dma_chan_lock, flags);
820 dma_chan[lch].dev_id = -1;
821 dma_chan[lch].next_lch = -1;
822 dma_chan[lch].callback = NULL;
823 spin_unlock_irqrestore(&dma_chan_lock, flags);
1a8bfa1e 824}
97b7f715 825EXPORT_SYMBOL(omap_free_dma);
1a8bfa1e 826
f8151e5c
AG		 827/**
828 * @brief omap_dma_set_global_params : Set global priority settings for dma
829 *
830 * @param arb_rate
831 * @param max_fifo_depth
70cf644c
AA		 832 * @param tparams - Number of threads to reserve : DMA_THREAD_RESERVE_NORM
833 * DMA_THREAD_RESERVE_ONET
834 * DMA_THREAD_RESERVE_TWOT
835 * DMA_THREAD_RESERVE_THREET
f8151e5c
AG		 836 */
837void
838omap_dma_set_global_params(int arb_rate, int max_fifo_depth, int tparams)
839{
840 u32 reg;
841
842 if (!cpu_class_is_omap2()) {
8e86f427 843 printk(KERN_ERR "FIXME: no %s on 15xx/16xx\n", __func__);
f8151e5c
AG		 844 return;
845 }
846
70cf644c
AA		 847 if (max_fifo_depth == 0)
848 max_fifo_depth = 1;
f8151e5c
AG		 849 if (arb_rate == 0)
850 arb_rate = 1;
851
70cf644c
AA		 852 reg = 0xff & max_fifo_depth;
853 reg |= (0x3 & tparams) << 12;
854 reg |= (arb_rate & 0xff) << 16;
f8151e5c 855
0499bdeb 856 dma_write(reg, GCR);
f8151e5c
AG		 857}
858EXPORT_SYMBOL(omap_dma_set_global_params);
859
860/**
861 * @brief omap_dma_set_prio_lch : Set channel wise priority settings
862 *
863 * @param lch
864 * @param read_prio - Read priority
865 * @param write_prio - Write priority
866 * Both of the above can be set with one of the following values :
867 * DMA_CH_PRIO_HIGH/DMA_CH_PRIO_LOW
868 */
869int
870omap_dma_set_prio_lch(int lch, unsigned char read_prio,
871 unsigned char write_prio)
872{
0499bdeb 873 u32 l;
f8151e5c 874
4d96372e 875 if (unlikely((lch < 0 || lch >= dma_lch_count))) {
f8151e5c
AG		 876 printk(KERN_ERR "Invalid channel id\n");
877 return -EINVAL;
878 }
0499bdeb
TL		 879 l = dma_read(CCR(lch));
880 l &= ~((1 << 6) | (1 << 26));
44169075 881 if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx())
0499bdeb 882 l |= ((read_prio & 0x1) << 6) | ((write_prio & 0x1) << 26);
f8151e5c 883 else
0499bdeb
TL		 884 l |= ((read_prio & 0x1) << 6);
885
886 dma_write(l, CCR(lch));
f8151e5c 887
f8151e5c
AG		 888 return 0;
889}
890EXPORT_SYMBOL(omap_dma_set_prio_lch);
891
1a8bfa1e
TL		 892/*
893 * Clears any DMA state so the DMA engine is ready to restart with new buffers
894 * through omap_start_dma(). Any buffers in flight are discarded.
895 */
896void omap_clear_dma(int lch)
897{
898 unsigned long flags;
899
900 local_irq_save(flags);
901
902 if (cpu_class_is_omap1()) {
0499bdeb
TL		 903 u32 l;
904
905 l = dma_read(CCR(lch));
906 l &= ~OMAP_DMA_CCR_EN;
907 dma_write(l, CCR(lch));
1a8bfa1e
TL		 908
909 /* Clear pending interrupts */
0499bdeb 910 l = dma_read(CSR(lch));
1a8bfa1e
TL		 911 }
912
f8151e5c 913 if (cpu_class_is_omap2()) {
1a8bfa1e 914 int i;
0499bdeb 915 void __iomem *lch_base = omap_dma_base + OMAP_DMA4_CH_BASE(lch);
1a8bfa1e 916 for (i = 0; i < 0x44; i += 4)
0499bdeb 917 __raw_writel(0, lch_base + i);
1a8bfa1e
TL		 918 }
919
920 local_irq_restore(flags);
921}
97b7f715 922EXPORT_SYMBOL(omap_clear_dma);
1a8bfa1e
TL		 923
924void omap_start_dma(int lch)
925{
0499bdeb
TL		 926 u32 l;
927
5e1c5ff4
TL		 928 if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) {
929 int next_lch, cur_lch;
4d96372e 930 char dma_chan_link_map[OMAP_DMA4_LOGICAL_DMA_CH_COUNT];
5e1c5ff4
TL		 931
932 dma_chan_link_map[lch] = 1;
933 /* Set the link register of the first channel */
934 enable_lnk(lch);
935
936 memset(dma_chan_link_map, 0, sizeof(dma_chan_link_map));
937 cur_lch = dma_chan[lch].next_lch;
938 do {
939 next_lch = dma_chan[cur_lch].next_lch;
940
1a8bfa1e 941 /* The loop case: we've been here already */
5e1c5ff4
TL		 942 if (dma_chan_link_map[cur_lch])
943 break;
944 /* Mark the current channel */
945 dma_chan_link_map[cur_lch] = 1;
946
947 enable_lnk(cur_lch);
1a8bfa1e 948 omap_enable_channel_irq(cur_lch);
5e1c5ff4
TL		 949
950 cur_lch = next_lch;
951 } while (next_lch != -1);
284119c4
VP		 952 } else if (cpu_is_omap242x() ||
953 (cpu_is_omap243x() && omap_type() <= OMAP2430_REV_ES1_0)) {
954
1a8bfa1e 955 /* Errata: Need to write lch even if not using chaining */
0499bdeb 956 dma_write(lch, CLNK_CTRL(lch));
5e1c5ff4
TL		 957 }
958
1a8bfa1e
TL		 959 omap_enable_channel_irq(lch);
960
0499bdeb
TL		 961 l = dma_read(CCR(lch));
962
97b7f715
TL		 963 /*
964 * Errata: On ES2.0 BUFFERING disable must be set.
965 * This will always fail on ES1.0
966 */
0499bdeb
TL		 967 if (cpu_is_omap24xx())
968 l |= OMAP_DMA_CCR_EN;
1a8bfa1e 969
0499bdeb
TL		 970 l |= OMAP_DMA_CCR_EN;
971 dma_write(l, CCR(lch));
5e1c5ff4 972
5e1c5ff4
TL		 973 dma_chan[lch].flags |= OMAP_DMA_ACTIVE;
974}
97b7f715 975EXPORT_SYMBOL(omap_start_dma);
5e1c5ff4
TL		 976
977void omap_stop_dma(int lch)
978{
0499bdeb
TL		 979 u32 l;
980
5e1c5ff4
TL		 981 if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) {
982 int next_lch, cur_lch = lch;
4d96372e 983 char dma_chan_link_map[OMAP_DMA4_LOGICAL_DMA_CH_COUNT];
5e1c5ff4
TL		 984
985 memset(dma_chan_link_map, 0, sizeof(dma_chan_link_map));
986 do {
987 /* The loop case: we've been here already */
988 if (dma_chan_link_map[cur_lch])
989 break;
990 /* Mark the current channel */
991 dma_chan_link_map[cur_lch] = 1;
992
993 disable_lnk(cur_lch);
994
995 next_lch = dma_chan[cur_lch].next_lch;
996 cur_lch = next_lch;
997 } while (next_lch != -1);
998
999 return;
1000 }
1a8bfa1e 1001
5e1c5ff4 1002 /* Disable all interrupts on the channel */
1a8bfa1e 1003 if (cpu_class_is_omap1())
0499bdeb
TL		 1004 dma_write(0, CICR(lch));
1005
1006 l = dma_read(CCR(lch));
1007 l &= ~OMAP_DMA_CCR_EN;
1008 dma_write(l, CCR(lch));
5e1c5ff4 1009
5e1c5ff4
TL		 1010 dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE;
1011}
97b7f715 1012EXPORT_SYMBOL(omap_stop_dma);
5e1c5ff4 1013
709eb3e5
TL		 1014/*
1015 * Allows changing the DMA callback function or data. This may be needed if
1016 * the driver shares a single DMA channel for multiple dma triggers.
1017 */
1018int omap_set_dma_callback(int lch,
97b7f715 1019 void (*callback)(int lch, u16 ch_status, void *data),
709eb3e5
TL		 1020 void *data)
1021{
1022 unsigned long flags;
1023
1024 if (lch < 0)
1025 return -ENODEV;
1026
1027 spin_lock_irqsave(&dma_chan_lock, flags);
1028 if (dma_chan[lch].dev_id == -1) {
1029 printk(KERN_ERR "DMA callback for not set for free channel\n");
1030 spin_unlock_irqrestore(&dma_chan_lock, flags);
1031 return -EINVAL;
1032 }
1033 dma_chan[lch].callback = callback;
1034 dma_chan[lch].data = data;
1035 spin_unlock_irqrestore(&dma_chan_lock, flags);
1036
1037 return 0;
1038}
97b7f715 1039EXPORT_SYMBOL(omap_set_dma_callback);
709eb3e5 1040
1a8bfa1e
TL		 1041/*
1042 * Returns current physical source address for the given DMA channel.
1043 * If the channel is running the caller must disable interrupts prior calling
1044 * this function and process the returned value before re-enabling interrupt to
1045 * prevent races with the interrupt handler. Note that in continuous mode there
1046 * is a chance for CSSA_L register overflow inbetween the two reads resulting
1047 * in incorrect return value.
1048 */
1049dma_addr_t omap_get_dma_src_pos(int lch)
5e1c5ff4 1050{
0695de32 1051 dma_addr_t offset = 0;
5e1c5ff4 1052
0499bdeb
TL		 1053 if (cpu_is_omap15xx())
1054 offset = dma_read(CPC(lch));
1055 else
1056 offset = dma_read(CSAC(lch));
5e1c5ff4 1057
0499bdeb
TL		 1058 /*
1059 * omap 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is
1060 * read before the DMA controller finished disabling the channel.
1061 */
1062 if (!cpu_is_omap15xx() && offset == 0)
1063 offset = dma_read(CSAC(lch));
1064
1065 if (cpu_class_is_omap1())
1066 offset |= (dma_read(CSSA_U(lch)) << 16);
5e1c5ff4 1067
1a8bfa1e 1068 return offset;
5e1c5ff4 1069}
97b7f715 1070EXPORT_SYMBOL(omap_get_dma_src_pos);
5e1c5ff4 1071
1a8bfa1e
TL		 1072/*
1073 * Returns current physical destination address for the given DMA channel.
1074 * If the channel is running the caller must disable interrupts prior calling
1075 * this function and process the returned value before re-enabling interrupt to
1076 * prevent races with the interrupt handler. Note that in continuous mode there
1077 * is a chance for CDSA_L register overflow inbetween the two reads resulting
1078 * in incorrect return value.
1079 */
1080dma_addr_t omap_get_dma_dst_pos(int lch)
5e1c5ff4 1081{
0695de32 1082 dma_addr_t offset = 0;
5e1c5ff4 1083
0499bdeb
TL		 1084 if (cpu_is_omap15xx())
1085 offset = dma_read(CPC(lch));
1086 else
1087 offset = dma_read(CDAC(lch));
5e1c5ff4 1088
0499bdeb
TL		 1089 /*
1090 * omap 3.2/3.3 erratum: sometimes 0 is returned if CSAC/CDAC is
1091 * read before the DMA controller finished disabling the channel.
1092 */
1093 if (!cpu_is_omap15xx() && offset == 0)
1094 offset = dma_read(CDAC(lch));
1095
1096 if (cpu_class_is_omap1())
1097 offset |= (dma_read(CDSA_U(lch)) << 16);
5e1c5ff4 1098
1a8bfa1e 1099 return offset;
5e1c5ff4 1100}
97b7f715 1101EXPORT_SYMBOL(omap_get_dma_dst_pos);
0499bdeb
TL		 1102
1103int omap_get_dma_active_status(int lch)
1104{
1105 return (dma_read(CCR(lch)) & OMAP_DMA_CCR_EN) != 0;
5e1c5ff4 1106}
0499bdeb 1107EXPORT_SYMBOL(omap_get_dma_active_status);
5e1c5ff4 1108
1a8bfa1e 1109int omap_dma_running(void)
5e1c5ff4 1110{
1a8bfa1e 1111 int lch;
5e1c5ff4 1112
1a8bfa1e
TL		 1113 /* Check if LCD DMA is running */
1114 if (cpu_is_omap16xx())
1115 if (omap_readw(OMAP1610_DMA_LCD_CCR) & OMAP_DMA_CCR_EN)
1116 return 1;
5e1c5ff4 1117
1a8bfa1e 1118 for (lch = 0; lch < dma_chan_count; lch++)
0499bdeb 1119 if (dma_read(CCR(lch)) & OMAP_DMA_CCR_EN)
1a8bfa1e 1120 return 1;
5e1c5ff4 1121
1a8bfa1e 1122 return 0;
5e1c5ff4
TL		 1123}
1124
1125/*
1126 * lch_queue DMA will start right after lch_head one is finished.
1127 * For this DMA link to start, you still need to start (see omap_start_dma)
1128 * the first one. That will fire up the entire queue.
1129 */
97b7f715 1130void omap_dma_link_lch(int lch_head, int lch_queue)
5e1c5ff4
TL		 1131{
1132 if (omap_dma_in_1510_mode()) {
9f0f4ae5
JK		 1133 if (lch_head == lch_queue) {
1134 dma_write(dma_read(CCR(lch_head)) | (3 << 8),
1135 CCR(lch_head));
1136 return;
1137 }
5e1c5ff4
TL		 1138 printk(KERN_ERR "DMA linking is not supported in 1510 mode\n");
1139 BUG();
1140 return;
1141 }
1142
1143 if ((dma_chan[lch_head].dev_id == -1) ||
1144 (dma_chan[lch_queue].dev_id == -1)) {
1a8bfa1e
TL		 1145 printk(KERN_ERR "omap_dma: trying to link "
1146 "non requested channels\n");
5e1c5ff4
TL		 1147 dump_stack();
1148 }
1149
1150 dma_chan[lch_head].next_lch = lch_queue;
1151}
97b7f715 1152EXPORT_SYMBOL(omap_dma_link_lch);
5e1c5ff4
TL		 1153
1154/*
1155 * Once the DMA queue is stopped, we can destroy it.
1156 */
97b7f715 1157void omap_dma_unlink_lch(int lch_head, int lch_queue)
5e1c5ff4
TL		 1158{
1159 if (omap_dma_in_1510_mode()) {
9f0f4ae5
JK		 1160 if (lch_head == lch_queue) {
1161 dma_write(dma_read(CCR(lch_head)) & ~(3 << 8),
1162 CCR(lch_head));
1163 return;
1164 }
5e1c5ff4
TL		 1165 printk(KERN_ERR "DMA linking is not supported in 1510 mode\n");
1166 BUG();
1167 return;
1168 }
1169
1170 if (dma_chan[lch_head].next_lch != lch_queue ||
1171 dma_chan[lch_head].next_lch == -1) {
1a8bfa1e
TL		 1172 printk(KERN_ERR "omap_dma: trying to unlink "
1173 "non linked channels\n");
5e1c5ff4
TL		 1174 dump_stack();
1175 }
1176
5e1c5ff4
TL		 1177 if ((dma_chan[lch_head].flags & OMAP_DMA_ACTIVE) ||
1178 (dma_chan[lch_head].flags & OMAP_DMA_ACTIVE)) {
1a8bfa1e
TL		 1179 printk(KERN_ERR "omap_dma: You need to stop the DMA channels "
1180 "before unlinking\n");
5e1c5ff4
TL		 1181 dump_stack();
1182 }
1183
1184 dma_chan[lch_head].next_lch = -1;
1185}
97b7f715
TL		 1186EXPORT_SYMBOL(omap_dma_unlink_lch);
1187
1188/*----------------------------------------------------------------------------*/
5e1c5ff4 1189
f8151e5c
AG		 1190#ifndef CONFIG_ARCH_OMAP1
1191/* Create chain of DMA channesls */
1192static void create_dma_lch_chain(int lch_head, int lch_queue)
1193{
0499bdeb 1194 u32 l;
f8151e5c
AG		 1195
1196 /* Check if this is the first link in chain */
1197 if (dma_chan[lch_head].next_linked_ch == -1) {
1198 dma_chan[lch_head].next_linked_ch = lch_queue;
1199 dma_chan[lch_head].prev_linked_ch = lch_queue;
1200 dma_chan[lch_queue].next_linked_ch = lch_head;
1201 dma_chan[lch_queue].prev_linked_ch = lch_head;
1202 }
1203
1204 /* a link exists, link the new channel in circular chain */
1205 else {
1206 dma_chan[lch_queue].next_linked_ch =
1207 dma_chan[lch_head].next_linked_ch;
1208 dma_chan[lch_queue].prev_linked_ch = lch_head;
1209 dma_chan[lch_head].next_linked_ch = lch_queue;
1210 dma_chan[dma_chan[lch_queue].next_linked_ch].prev_linked_ch =
1211 lch_queue;
1212 }
1213
0499bdeb
TL		 1214 l = dma_read(CLNK_CTRL(lch_head));
1215 l &= ~(0x1f);
1216 l |= lch_queue;
1217 dma_write(l, CLNK_CTRL(lch_head));
f8151e5c 1218
0499bdeb
TL		 1219 l = dma_read(CLNK_CTRL(lch_queue));
1220 l &= ~(0x1f);
1221 l |= (dma_chan[lch_queue].next_linked_ch);
1222 dma_write(l, CLNK_CTRL(lch_queue));
f8151e5c
AG		 1223}
1224
1225/**
1226 * @brief omap_request_dma_chain : Request a chain of DMA channels
1227 *
1228 * @param dev_id - Device id using the dma channel
1229 * @param dev_name - Device name
1230 * @param callback - Call back function
1231 * @chain_id -
1232 * @no_of_chans - Number of channels requested
1233 * @chain_mode - Dynamic or static chaining : OMAP_DMA_STATIC_CHAIN
1234 * OMAP_DMA_DYNAMIC_CHAIN
1235 * @params - Channel parameters
1236 *
1237 * @return - Succes : 0
1238 * Failure: -EINVAL/-ENOMEM
1239 */
1240int omap_request_dma_chain(int dev_id, const char *dev_name,
279b918d 1241 void (*callback) (int lch, u16 ch_status,
f8151e5c
AG		 1242 void *data),
1243 int *chain_id, int no_of_chans, int chain_mode,
1244 struct omap_dma_channel_params params)
1245{
1246 int *channels;
1247 int i, err;
1248
1249 /* Is the chain mode valid ? */
1250 if (chain_mode != OMAP_DMA_STATIC_CHAIN
1251 && chain_mode != OMAP_DMA_DYNAMIC_CHAIN) {
1252 printk(KERN_ERR "Invalid chain mode requested\n");
1253 return -EINVAL;
1254 }
1255
1256 if (unlikely((no_of_chans < 1
4d96372e 1257 || no_of_chans > dma_lch_count))) {
f8151e5c
AG		 1258 printk(KERN_ERR "Invalid Number of channels requested\n");
1259 return -EINVAL;
1260 }
1261
1262 /* Allocate a queue to maintain the status of the channels
1263 * in the chain */
1264 channels = kmalloc(sizeof(*channels) * no_of_chans, GFP_KERNEL);
1265 if (channels == NULL) {
1266 printk(KERN_ERR "omap_dma: No memory for channel queue\n");
1267 return -ENOMEM;
1268 }
1269
1270 /* request and reserve DMA channels for the chain */
1271 for (i = 0; i < no_of_chans; i++) {
1272 err = omap_request_dma(dev_id, dev_name,
c0fc18c5 1273 callback, NULL, &channels[i]);
f8151e5c
AG		 1274 if (err < 0) {
1275 int j;
1276 for (j = 0; j < i; j++)
1277 omap_free_dma(channels[j]);
1278 kfree(channels);
1279 printk(KERN_ERR "omap_dma: Request failed %d\n", err);
1280 return err;
1281 }
f8151e5c
AG		 1282 dma_chan[channels[i]].prev_linked_ch = -1;
1283 dma_chan[channels[i]].state = DMA_CH_NOTSTARTED;
1284
1285 /*
1286 * Allowing client drivers to set common parameters now,
1287 * so that later only relevant (src_start, dest_start
1288 * and element count) can be set
1289 */
1290 omap_set_dma_params(channels[i], &params);
1291 }
1292
1293 *chain_id = channels[0];
1294 dma_linked_lch[*chain_id].linked_dmach_q = channels;
1295 dma_linked_lch[*chain_id].chain_mode = chain_mode;
1296 dma_linked_lch[*chain_id].chain_state = DMA_CHAIN_NOTSTARTED;
1297 dma_linked_lch[*chain_id].no_of_lchs_linked = no_of_chans;
1298
1299 for (i = 0; i < no_of_chans; i++)
1300 dma_chan[channels[i]].chain_id = *chain_id;
1301
1302 /* Reset the Queue pointers */
1303 OMAP_DMA_CHAIN_QINIT(*chain_id);
1304
1305 /* Set up the chain */
1306 if (no_of_chans == 1)
1307 create_dma_lch_chain(channels[0], channels[0]);
1308 else {
1309 for (i = 0; i < (no_of_chans - 1); i++)
1310 create_dma_lch_chain(channels[i], channels[i + 1]);
1311 }
97b7f715 1312
f8151e5c
AG		 1313 return 0;
1314}
1315EXPORT_SYMBOL(omap_request_dma_chain);
1316
1317/**
1318 * @brief omap_modify_dma_chain_param : Modify the chain's params - Modify the
1319 * params after setting it. Dont do this while dma is running!!
1320 *
1321 * @param chain_id - Chained logical channel id.
1322 * @param params
1323 *
1324 * @return - Success : 0
1325 * Failure : -EINVAL
1326 */
1327int omap_modify_dma_chain_params(int chain_id,
1328 struct omap_dma_channel_params params)
1329{
1330 int *channels;
1331 u32 i;
1332
1333 /* Check for input params */
1334 if (unlikely((chain_id < 0
4d96372e 1335 || chain_id >= dma_lch_count))) {
f8151e5c
AG		 1336 printk(KERN_ERR "Invalid chain id\n");
1337 return -EINVAL;
1338 }
1339
1340 /* Check if the chain exists */
1341 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1342 printk(KERN_ERR "Chain doesn't exists\n");
1343 return -EINVAL;
1344 }
1345 channels = dma_linked_lch[chain_id].linked_dmach_q;
1346
1347 for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) {
1348 /*
1349 * Allowing client drivers to set common parameters now,
1350 * so that later only relevant (src_start, dest_start
1351 * and element count) can be set
1352 */
1353 omap_set_dma_params(channels[i], &params);
1354 }
97b7f715 1355
f8151e5c
AG		 1356 return 0;
1357}
1358EXPORT_SYMBOL(omap_modify_dma_chain_params);
1359
1360/**
1361 * @brief omap_free_dma_chain - Free all the logical channels in a chain.
1362 *
1363 * @param chain_id
1364 *
1365 * @return - Success : 0
1366 * Failure : -EINVAL
1367 */
1368int omap_free_dma_chain(int chain_id)
1369{
1370 int *channels;
1371 u32 i;
1372
1373 /* Check for input params */
4d96372e 1374 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
f8151e5c
AG		 1375 printk(KERN_ERR "Invalid chain id\n");
1376 return -EINVAL;
1377 }
1378
1379 /* Check if the chain exists */
1380 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1381 printk(KERN_ERR "Chain doesn't exists\n");
1382 return -EINVAL;
1383 }
1384
1385 channels = dma_linked_lch[chain_id].linked_dmach_q;
1386 for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) {
1387 dma_chan[channels[i]].next_linked_ch = -1;
1388 dma_chan[channels[i]].prev_linked_ch = -1;
1389 dma_chan[channels[i]].chain_id = -1;
1390 dma_chan[channels[i]].state = DMA_CH_NOTSTARTED;
1391 omap_free_dma(channels[i]);
1392 }
1393
1394 kfree(channels);
1395
1396 dma_linked_lch[chain_id].linked_dmach_q = NULL;
1397 dma_linked_lch[chain_id].chain_mode = -1;
1398 dma_linked_lch[chain_id].chain_state = -1;
97b7f715 1399
f8151e5c
AG		 1400 return (0);
1401}
1402EXPORT_SYMBOL(omap_free_dma_chain);
1403
1404/**
1405 * @brief omap_dma_chain_status - Check if the chain is in
1406 * active / inactive state.
1407 * @param chain_id
1408 *
1409 * @return - Success : OMAP_DMA_CHAIN_ACTIVE/OMAP_DMA_CHAIN_INACTIVE
1410 * Failure : -EINVAL
1411 */
1412int omap_dma_chain_status(int chain_id)
1413{
1414 /* Check for input params */
4d96372e 1415 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
f8151e5c
AG		 1416 printk(KERN_ERR "Invalid chain id\n");
1417 return -EINVAL;
1418 }
1419
1420 /* Check if the chain exists */
1421 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1422 printk(KERN_ERR "Chain doesn't exists\n");
1423 return -EINVAL;
1424 }
1425 pr_debug("CHAINID=%d, qcnt=%d\n", chain_id,
1426 dma_linked_lch[chain_id].q_count);
1427
1428 if (OMAP_DMA_CHAIN_QEMPTY(chain_id))
1429 return OMAP_DMA_CHAIN_INACTIVE;
97b7f715 1430
f8151e5c
AG		 1431 return OMAP_DMA_CHAIN_ACTIVE;
1432}
1433EXPORT_SYMBOL(omap_dma_chain_status);
1434
1435/**
1436 * @brief omap_dma_chain_a_transfer - Get a free channel from a chain,
1437 * set the params and start the transfer.
1438 *
1439 * @param chain_id
1440 * @param src_start - buffer start address
1441 * @param dest_start - Dest address
1442 * @param elem_count
1443 * @param frame_count
1444 * @param callbk_data - channel callback parameter data.
1445 *
f4b6a7ef 1446 * @return - Success : 0
f8151e5c
AG		 1447 * Failure: -EINVAL/-EBUSY
1448 */
1449int omap_dma_chain_a_transfer(int chain_id, int src_start, int dest_start,
1450 int elem_count, int frame_count, void *callbk_data)
1451{
1452 int *channels;
0499bdeb 1453 u32 l, lch;
f8151e5c
AG		 1454 int start_dma = 0;
1455
97b7f715
TL		 1456 /*
1457 * if buffer size is less than 1 then there is
1458 * no use of starting the chain
1459 */
f8151e5c
AG		 1460 if (elem_count < 1) {
1461 printk(KERN_ERR "Invalid buffer size\n");
1462 return -EINVAL;
1463 }
1464
1465 /* Check for input params */
1466 if (unlikely((chain_id < 0
4d96372e 1467 || chain_id >= dma_lch_count))) {
f8151e5c
AG		 1468 printk(KERN_ERR "Invalid chain id\n");
1469 return -EINVAL;
1470 }
1471
1472 /* Check if the chain exists */
1473 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1474 printk(KERN_ERR "Chain doesn't exist\n");
1475 return -EINVAL;
1476 }
1477
1478 /* Check if all the channels in chain are in use */
1479 if (OMAP_DMA_CHAIN_QFULL(chain_id))
1480 return -EBUSY;
1481
1482 /* Frame count may be negative in case of indexed transfers */
1483 channels = dma_linked_lch[chain_id].linked_dmach_q;
1484
1485 /* Get a free channel */
1486 lch = channels[dma_linked_lch[chain_id].q_tail];
1487
1488 /* Store the callback data */
1489 dma_chan[lch].data = callbk_data;
1490
1491 /* Increment the q_tail */
1492 OMAP_DMA_CHAIN_INCQTAIL(chain_id);
1493
1494 /* Set the params to the free channel */
1495 if (src_start != 0)
0499bdeb 1496 dma_write(src_start, CSSA(lch));
f8151e5c 1497 if (dest_start != 0)
0499bdeb 1498 dma_write(dest_start, CDSA(lch));
f8151e5c
AG		 1499
1500 /* Write the buffer size */
0499bdeb
TL		 1501 dma_write(elem_count, CEN(lch));
1502 dma_write(frame_count, CFN(lch));
f8151e5c 1503
97b7f715
TL		 1504 /*
1505 * If the chain is dynamically linked,
1506 * then we may have to start the chain if its not active
1507 */
f8151e5c
AG		 1508 if (dma_linked_lch[chain_id].chain_mode == OMAP_DMA_DYNAMIC_CHAIN) {
1509
97b7f715
TL		 1510 /*
1511 * In Dynamic chain, if the chain is not started,
1512 * queue the channel
1513 */
f8151e5c
AG		 1514 if (dma_linked_lch[chain_id].chain_state ==
1515 DMA_CHAIN_NOTSTARTED) {
1516 /* Enable the link in previous channel */
1517 if (dma_chan[dma_chan[lch].prev_linked_ch].state ==
1518 DMA_CH_QUEUED)
1519 enable_lnk(dma_chan[lch].prev_linked_ch);
1520 dma_chan[lch].state = DMA_CH_QUEUED;
1521 }
1522
97b7f715
TL		 1523 /*
1524 * Chain is already started, make sure its active,
1525 * if not then start the chain
1526 */
f8151e5c
AG		 1527 else {
1528 start_dma = 1;
1529
1530 if (dma_chan[dma_chan[lch].prev_linked_ch].state ==
1531 DMA_CH_STARTED) {
1532 enable_lnk(dma_chan[lch].prev_linked_ch);
1533 dma_chan[lch].state = DMA_CH_QUEUED;
1534 start_dma = 0;
0499bdeb
TL		 1535 if (0 == ((1 << 7) & dma_read(
1536 CCR(dma_chan[lch].prev_linked_ch)))) {
f8151e5c
AG		 1537 disable_lnk(dma_chan[lch].
1538 prev_linked_ch);
1539 pr_debug("\n prev ch is stopped\n");
1540 start_dma = 1;
1541 }
1542 }
1543
1544 else if (dma_chan[dma_chan[lch].prev_linked_ch].state
1545 == DMA_CH_QUEUED) {
1546 enable_lnk(dma_chan[lch].prev_linked_ch);
1547 dma_chan[lch].state = DMA_CH_QUEUED;
1548 start_dma = 0;
1549 }
1550 omap_enable_channel_irq(lch);
1551
0499bdeb 1552 l = dma_read(CCR(lch));
f8151e5c 1553
0499bdeb
TL		 1554 if ((0 == (l & (1 << 24))))
1555 l &= ~(1 << 25);
f8151e5c 1556 else
0499bdeb 1557 l |= (1 << 25);
f8151e5c 1558 if (start_dma == 1) {
0499bdeb
TL		 1559 if (0 == (l & (1 << 7))) {
1560 l |= (1 << 7);
f8151e5c
AG		 1561 dma_chan[lch].state = DMA_CH_STARTED;
1562 pr_debug("starting %d\n", lch);
0499bdeb 1563 dma_write(l, CCR(lch));
f8151e5c
AG		 1564 } else
1565 start_dma = 0;
1566 } else {
0499bdeb
TL		 1567 if (0 == (l & (1 << 7)))
1568 dma_write(l, CCR(lch));
f8151e5c
AG		 1569 }
1570 dma_chan[lch].flags |= OMAP_DMA_ACTIVE;
1571 }
1572 }
97b7f715 1573
f4b6a7ef 1574 return 0;
f8151e5c
AG		 1575}
1576EXPORT_SYMBOL(omap_dma_chain_a_transfer);
1577
1578/**
1579 * @brief omap_start_dma_chain_transfers - Start the chain
1580 *
1581 * @param chain_id
1582 *
1583 * @return - Success : 0
1584 * Failure : -EINVAL/-EBUSY
1585 */
1586int omap_start_dma_chain_transfers(int chain_id)
1587{
1588 int *channels;
0499bdeb 1589 u32 l, i;
f8151e5c 1590
4d96372e 1591 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
f8151e5c
AG		 1592 printk(KERN_ERR "Invalid chain id\n");
1593 return -EINVAL;
1594 }
1595
1596 channels = dma_linked_lch[chain_id].linked_dmach_q;
1597
1598 if (dma_linked_lch[channels[0]].chain_state == DMA_CHAIN_STARTED) {
1599 printk(KERN_ERR "Chain is already started\n");
1600 return -EBUSY;
1601 }
1602
1603 if (dma_linked_lch[chain_id].chain_mode == OMAP_DMA_STATIC_CHAIN) {
1604 for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked;
1605 i++) {
1606 enable_lnk(channels[i]);
1607 omap_enable_channel_irq(channels[i]);
1608 }
1609 } else {
1610 omap_enable_channel_irq(channels[0]);
1611 }
1612
0499bdeb
TL		 1613 l = dma_read(CCR(channels[0]));
1614 l |= (1 << 7);
f8151e5c
AG		 1615 dma_linked_lch[chain_id].chain_state = DMA_CHAIN_STARTED;
1616 dma_chan[channels[0]].state = DMA_CH_STARTED;
1617
0499bdeb
TL		 1618 if ((0 == (l & (1 << 24))))
1619 l &= ~(1 << 25);
f8151e5c 1620 else
0499bdeb
TL		 1621 l |= (1 << 25);
1622 dma_write(l, CCR(channels[0]));
f8151e5c
AG		 1623
1624 dma_chan[channels[0]].flags |= OMAP_DMA_ACTIVE;
97b7f715 1625
f8151e5c
AG		 1626 return 0;
1627}
1628EXPORT_SYMBOL(omap_start_dma_chain_transfers);
1629
1630/**
1631 * @brief omap_stop_dma_chain_transfers - Stop the dma transfer of a chain.
1632 *
1633 * @param chain_id
1634 *
1635 * @return - Success : 0
1636 * Failure : EINVAL
1637 */
1638int omap_stop_dma_chain_transfers(int chain_id)
1639{
1640 int *channels;
0499bdeb 1641 u32 l, i;
f8151e5c
AG		 1642 u32 sys_cf;
1643
1644 /* Check for input params */
4d96372e 1645 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
f8151e5c
AG		 1646 printk(KERN_ERR "Invalid chain id\n");
1647 return -EINVAL;
1648 }
1649
1650 /* Check if the chain exists */
1651 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1652 printk(KERN_ERR "Chain doesn't exists\n");
1653 return -EINVAL;
1654 }
1655 channels = dma_linked_lch[chain_id].linked_dmach_q;
1656
97b7f715
TL		 1657 /*
1658 * DMA Errata:
f8151e5c
AG		 1659 * Special programming model needed to disable DMA before end of block
1660 */
0499bdeb
TL		 1661 sys_cf = dma_read(OCP_SYSCONFIG);
1662 l = sys_cf;
f8151e5c 1663 /* Middle mode reg set no Standby */
0499bdeb
TL		 1664 l &= ~((1 << 12)|(1 << 13));
1665 dma_write(l, OCP_SYSCONFIG);
f8151e5c
AG		 1666
1667 for (i = 0; i < dma_linked_lch[chain_id].no_of_lchs_linked; i++) {
1668
1669 /* Stop the Channel transmission */
0499bdeb
TL		 1670 l = dma_read(CCR(channels[i]));
1671 l &= ~(1 << 7);
1672 dma_write(l, CCR(channels[i]));
f8151e5c
AG		 1673
1674 /* Disable the link in all the channels */
1675 disable_lnk(channels[i]);
1676 dma_chan[channels[i]].state = DMA_CH_NOTSTARTED;
1677
1678 }
1679 dma_linked_lch[chain_id].chain_state = DMA_CHAIN_NOTSTARTED;
1680
1681 /* Reset the Queue pointers */
1682 OMAP_DMA_CHAIN_QINIT(chain_id);
1683
1684 /* Errata - put in the old value */
0499bdeb 1685 dma_write(sys_cf, OCP_SYSCONFIG);
97b7f715 1686
f8151e5c
AG		 1687 return 0;
1688}
1689EXPORT_SYMBOL(omap_stop_dma_chain_transfers);
1690
1691/* Get the index of the ongoing DMA in chain */
1692/**
1693 * @brief omap_get_dma_chain_index - Get the element and frame index
1694 * of the ongoing DMA in chain
1695 *
1696 * @param chain_id
1697 * @param ei - Element index
1698 * @param fi - Frame index
1699 *
1700 * @return - Success : 0
1701 * Failure : -EINVAL
1702 */
1703int omap_get_dma_chain_index(int chain_id, int *ei, int *fi)
1704{
1705 int lch;
1706 int *channels;
1707
1708 /* Check for input params */
4d96372e 1709 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
f8151e5c
AG		 1710 printk(KERN_ERR "Invalid chain id\n");
1711 return -EINVAL;
1712 }
1713
1714 /* Check if the chain exists */
1715 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1716 printk(KERN_ERR "Chain doesn't exists\n");
1717 return -EINVAL;
1718 }
1719 if ((!ei) || (!fi))
1720 return -EINVAL;
1721
1722 channels = dma_linked_lch[chain_id].linked_dmach_q;
1723
1724 /* Get the current channel */
1725 lch = channels[dma_linked_lch[chain_id].q_head];
1726
0499bdeb
TL		 1727 *ei = dma_read(CCEN(lch));
1728 *fi = dma_read(CCFN(lch));
f8151e5c
AG		 1729
1730 return 0;
1731}
1732EXPORT_SYMBOL(omap_get_dma_chain_index);
1733
1734/**
1735 * @brief omap_get_dma_chain_dst_pos - Get the destination position of the
1736 * ongoing DMA in chain
1737 *
1738 * @param chain_id
1739 *
1740 * @return - Success : Destination position
1741 * Failure : -EINVAL
1742 */
1743int omap_get_dma_chain_dst_pos(int chain_id)
1744{
1745 int lch;
1746 int *channels;
1747
1748 /* Check for input params */
4d96372e 1749 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
f8151e5c
AG		 1750 printk(KERN_ERR "Invalid chain id\n");
1751 return -EINVAL;
1752 }
1753
1754 /* Check if the chain exists */
1755 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1756 printk(KERN_ERR "Chain doesn't exists\n");
1757 return -EINVAL;
1758 }
1759
1760 channels = dma_linked_lch[chain_id].linked_dmach_q;
1761
1762 /* Get the current channel */
1763 lch = channels[dma_linked_lch[chain_id].q_head];
1764
0499bdeb 1765 return dma_read(CDAC(lch));
f8151e5c
AG		 1766}
1767EXPORT_SYMBOL(omap_get_dma_chain_dst_pos);
1768
1769/**
1770 * @brief omap_get_dma_chain_src_pos - Get the source position
1771 * of the ongoing DMA in chain
1772 * @param chain_id
1773 *
1774 * @return - Success : Destination position
1775 * Failure : -EINVAL
1776 */
1777int omap_get_dma_chain_src_pos(int chain_id)
1778{
1779 int lch;
1780 int *channels;
1781
1782 /* Check for input params */
4d96372e 1783 if (unlikely((chain_id < 0 || chain_id >= dma_lch_count))) {
f8151e5c
AG		 1784 printk(KERN_ERR "Invalid chain id\n");
1785 return -EINVAL;
1786 }
1787
1788 /* Check if the chain exists */
1789 if (dma_linked_lch[chain_id].linked_dmach_q == NULL) {
1790 printk(KERN_ERR "Chain doesn't exists\n");
1791 return -EINVAL;
1792 }
1793
1794 channels = dma_linked_lch[chain_id].linked_dmach_q;
1795
1796 /* Get the current channel */
1797 lch = channels[dma_linked_lch[chain_id].q_head];
1798
0499bdeb 1799 return dma_read(CSAC(lch));
f8151e5c
AG		 1800}
1801EXPORT_SYMBOL(omap_get_dma_chain_src_pos);
97b7f715 1802#endif /* ifndef CONFIG_ARCH_OMAP1 */
f8151e5c 1803
1a8bfa1e
TL		 1804/*----------------------------------------------------------------------------*/
1805
1806#ifdef CONFIG_ARCH_OMAP1
1807
1808static int omap1_dma_handle_ch(int ch)
1809{
0499bdeb 1810 u32 csr;
1a8bfa1e
TL		 1811
1812 if (enable_1510_mode && ch >= 6) {
1813 csr = dma_chan[ch].saved_csr;
1814 dma_chan[ch].saved_csr = 0;
1815 } else
0499bdeb 1816 csr = dma_read(CSR(ch));
1a8bfa1e
TL		 1817 if (enable_1510_mode && ch <= 2 && (csr >> 7) != 0) {
1818 dma_chan[ch + 6].saved_csr = csr >> 7;
1819 csr &= 0x7f;
1820 }
1821 if ((csr & 0x3f) == 0)
1822 return 0;
1823 if (unlikely(dma_chan[ch].dev_id == -1)) {
1824 printk(KERN_WARNING "Spurious interrupt from DMA channel "
1825 "%d (CSR %04x)\n", ch, csr);
1826 return 0;
1827 }
7ff879db 1828 if (unlikely(csr & OMAP1_DMA_TOUT_IRQ))
1a8bfa1e
TL		 1829 printk(KERN_WARNING "DMA timeout with device %d\n",
1830 dma_chan[ch].dev_id);
1831 if (unlikely(csr & OMAP_DMA_DROP_IRQ))
1832 printk(KERN_WARNING "DMA synchronization event drop occurred "
1833 "with device %d\n", dma_chan[ch].dev_id);
1834 if (likely(csr & OMAP_DMA_BLOCK_IRQ))
1835 dma_chan[ch].flags &= ~OMAP_DMA_ACTIVE;
1836 if (likely(dma_chan[ch].callback != NULL))
1837 dma_chan[ch].callback(ch, csr, dma_chan[ch].data);
97b7f715 1838
1a8bfa1e
TL		 1839 return 1;
1840}
1841
0cd61b68 1842static irqreturn_t omap1_dma_irq_handler(int irq, void *dev_id)
1a8bfa1e
TL		 1843{
1844 int ch = ((int) dev_id) - 1;
1845 int handled = 0;
1846
1847 for (;;) {
1848 int handled_now = 0;
1849
1850 handled_now += omap1_dma_handle_ch(ch);
1851 if (enable_1510_mode && dma_chan[ch + 6].saved_csr)
1852 handled_now += omap1_dma_handle_ch(ch + 6);
1853 if (!handled_now)
1854 break;
1855 handled += handled_now;
1856 }
1857
1858 return handled ? IRQ_HANDLED : IRQ_NONE;
1859}
1860
1861#else
1862#define omap1_dma_irq_handler NULL
1863#endif
1864
44169075
SS		 1865#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) || \
1866 defined(CONFIG_ARCH_OMAP4)
1a8bfa1e
TL		 1867
1868static int omap2_dma_handle_ch(int ch)
1869{
0499bdeb 1870 u32 status = dma_read(CSR(ch));
1a8bfa1e 1871
3151369d
JY		 1872 if (!status) {
1873 if (printk_ratelimit())
97b7f715
TL		 1874 printk(KERN_WARNING "Spurious DMA IRQ for lch %d\n",
1875 ch);
0499bdeb 1876 dma_write(1 << ch, IRQSTATUS_L0);
1a8bfa1e 1877 return 0;
3151369d
JY		 1878 }
1879 if (unlikely(dma_chan[ch].dev_id == -1)) {
1880 if (printk_ratelimit())
1881 printk(KERN_WARNING "IRQ %04x for non-allocated DMA"
1882 "channel %d\n", status, ch);
1a8bfa1e 1883 return 0;
3151369d 1884 }
1a8bfa1e
TL		 1885 if (unlikely(status & OMAP_DMA_DROP_IRQ))
1886 printk(KERN_INFO
1887 "DMA synchronization event drop occurred with device "
1888 "%d\n", dma_chan[ch].dev_id);
a50f18c7 1889 if (unlikely(status & OMAP2_DMA_TRANS_ERR_IRQ)) {
1a8bfa1e
TL		 1890 printk(KERN_INFO "DMA transaction error with device %d\n",
1891 dma_chan[ch].dev_id);
a50f18c7
SS		 1892 if (cpu_class_is_omap2()) {
1893 /* Errata: sDMA Channel is not disabled
1894 * after a transaction error. So we explicitely
1895 * disable the channel
1896 */
1897 u32 ccr;
1898
1899 ccr = dma_read(CCR(ch));
1900 ccr &= ~OMAP_DMA_CCR_EN;
1901 dma_write(ccr, CCR(ch));
1902 dma_chan[ch].flags &= ~OMAP_DMA_ACTIVE;
1903 }
1904 }
7ff879db
TL		 1905 if (unlikely(status & OMAP2_DMA_SECURE_ERR_IRQ))
1906 printk(KERN_INFO "DMA secure error with device %d\n",
1907 dma_chan[ch].dev_id);
1908 if (unlikely(status & OMAP2_DMA_MISALIGNED_ERR_IRQ))
1909 printk(KERN_INFO "DMA misaligned error with device %d\n",
1910 dma_chan[ch].dev_id);
1a8bfa1e 1911
0499bdeb
TL		 1912 dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR(ch));
1913 dma_write(1 << ch, IRQSTATUS_L0);
1a8bfa1e 1914
f8151e5c
AG		 1915 /* If the ch is not chained then chain_id will be -1 */
1916 if (dma_chan[ch].chain_id != -1) {
1917 int chain_id = dma_chan[ch].chain_id;
1918 dma_chan[ch].state = DMA_CH_NOTSTARTED;
0499bdeb 1919 if (dma_read(CLNK_CTRL(ch)) & (1 << 15))
f8151e5c
AG		 1920 dma_chan[dma_chan[ch].next_linked_ch].state =
1921 DMA_CH_STARTED;
1922 if (dma_linked_lch[chain_id].chain_mode ==
1923 OMAP_DMA_DYNAMIC_CHAIN)
1924 disable_lnk(ch);
1925
1926 if (!OMAP_DMA_CHAIN_QEMPTY(chain_id))
1927 OMAP_DMA_CHAIN_INCQHEAD(chain_id);
1928
0499bdeb 1929 status = dma_read(CSR(ch));
f8151e5c
AG		 1930 }
1931
320ce6f6
JY		 1932 dma_write(status, CSR(ch));
1933
538528de
JN		 1934 if (likely(dma_chan[ch].callback != NULL))
1935 dma_chan[ch].callback(ch, status, dma_chan[ch].data);
f8151e5c 1936
1a8bfa1e
TL		 1937 return 0;
1938}
1939
1940/* STATUS register count is from 1-32 while our is 0-31 */
0cd61b68 1941static irqreturn_t omap2_dma_irq_handler(int irq, void *dev_id)
1a8bfa1e 1942{
52176e70 1943 u32 val, enable_reg;
1a8bfa1e
TL		 1944 int i;
1945
0499bdeb 1946 val = dma_read(IRQSTATUS_L0);
3151369d
JY		 1947 if (val == 0) {
1948 if (printk_ratelimit())
1949 printk(KERN_WARNING "Spurious DMA IRQ\n");
1950 return IRQ_HANDLED;
1951 }
52176e70
SS		 1952 enable_reg = dma_read(IRQENABLE_L0);
1953 val &= enable_reg; /* Dispatch only relevant interrupts */
4d96372e 1954 for (i = 0; i < dma_lch_count && val != 0; i++) {
3151369d
JY		 1955 if (val & 1)
1956 omap2_dma_handle_ch(i);
1957 val >>= 1;
1a8bfa1e
TL		 1958 }
1959
1960 return IRQ_HANDLED;
1961}
1962
1963static struct irqaction omap24xx_dma_irq = {
1964 .name = "DMA",
1965 .handler = omap2_dma_irq_handler,
52e405ea 1966 .flags = IRQF_DISABLED
1a8bfa1e
TL		 1967};
1968
1969#else
1970static struct irqaction omap24xx_dma_irq;
1971#endif
1972
1973/*----------------------------------------------------------------------------*/
5e1c5ff4
TL		 1974
1975static struct lcd_dma_info {
1976 spinlock_t lock;
1977 int reserved;
97b7f715 1978 void (*callback)(u16 status, void *data);
5e1c5ff4
TL		 1979 void *cb_data;
1980
1981 int active;
1982 unsigned long addr, size;
1983 int rotate, data_type, xres, yres;
1984 int vxres;
1985 int mirror;
1986 int xscale, yscale;
1987 int ext_ctrl;
1988 int src_port;
1989 int single_transfer;
1990} lcd_dma;
1991
1992void omap_set_lcd_dma_b1(unsigned long addr, u16 fb_xres, u16 fb_yres,
1993 int data_type)
1994{
1995 lcd_dma.addr = addr;
1996 lcd_dma.data_type = data_type;
1997 lcd_dma.xres = fb_xres;
1998 lcd_dma.yres = fb_yres;
1999}
97b7f715 2000EXPORT_SYMBOL(omap_set_lcd_dma_b1);
5e1c5ff4
TL		 2001
2002void omap_set_lcd_dma_src_port(int port)
2003{
2004 lcd_dma.src_port = port;
2005}
2006
2007void omap_set_lcd_dma_ext_controller(int external)
2008{
2009 lcd_dma.ext_ctrl = external;
2010}
97b7f715 2011EXPORT_SYMBOL(omap_set_lcd_dma_ext_controller);
5e1c5ff4
TL		 2012
2013void omap_set_lcd_dma_single_transfer(int single)
2014{
2015 lcd_dma.single_transfer = single;
2016}
97b7f715 2017EXPORT_SYMBOL(omap_set_lcd_dma_single_transfer);
5e1c5ff4
TL		 2018
2019void omap_set_lcd_dma_b1_rotation(int rotate)
2020{
2021 if (omap_dma_in_1510_mode()) {
2022 printk(KERN_ERR "DMA rotation is not supported in 1510 mode\n");
2023 BUG();
2024 return;
2025 }
2026 lcd_dma.rotate = rotate;
2027}
97b7f715 2028EXPORT_SYMBOL(omap_set_lcd_dma_b1_rotation);
5e1c5ff4
TL		 2029
2030void omap_set_lcd_dma_b1_mirror(int mirror)
2031{
2032 if (omap_dma_in_1510_mode()) {
2033 printk(KERN_ERR "DMA mirror is not supported in 1510 mode\n");
2034 BUG();
2035 }
2036 lcd_dma.mirror = mirror;
2037}
97b7f715 2038EXPORT_SYMBOL(omap_set_lcd_dma_b1_mirror);
5e1c5ff4
TL		 2039
2040void omap_set_lcd_dma_b1_vxres(unsigned long vxres)
2041{
2042 if (omap_dma_in_1510_mode()) {
2043 printk(KERN_ERR "DMA virtual resulotion is not supported "
2044 "in 1510 mode\n");
2045 BUG();
2046 }
2047 lcd_dma.vxres = vxres;
2048}
97b7f715 2049EXPORT_SYMBOL(omap_set_lcd_dma_b1_vxres);
5e1c5ff4
TL		 2050
2051void omap_set_lcd_dma_b1_scale(unsigned int xscale, unsigned int yscale)
2052{
2053 if (omap_dma_in_1510_mode()) {
2054 printk(KERN_ERR "DMA scale is not supported in 1510 mode\n");
2055 BUG();
2056 }
2057 lcd_dma.xscale = xscale;
2058 lcd_dma.yscale = yscale;
2059}
97b7f715 2060EXPORT_SYMBOL(omap_set_lcd_dma_b1_scale);
5e1c5ff4
TL		 2061
2062static void set_b1_regs(void)
2063{
2064 unsigned long top, bottom;
2065 int es;
2066 u16 w;
2067 unsigned long en, fn;
2068 long ei, fi;
2069 unsigned long vxres;
2070 unsigned int xscale, yscale;
2071
2072 switch (lcd_dma.data_type) {
2073 case OMAP_DMA_DATA_TYPE_S8:
2074 es = 1;
2075 break;
2076 case OMAP_DMA_DATA_TYPE_S16:
2077 es = 2;
2078 break;
2079 case OMAP_DMA_DATA_TYPE_S32:
2080 es = 4;
2081 break;
2082 default:
2083 BUG();
2084 return;
2085 }
2086
2087 vxres = lcd_dma.vxres ? lcd_dma.vxres : lcd_dma.xres;
2088 xscale = lcd_dma.xscale ? lcd_dma.xscale : 1;
2089 yscale = lcd_dma.yscale ? lcd_dma.yscale : 1;
2090 BUG_ON(vxres < lcd_dma.xres);
97b7f715
TL		 2091
2092#define PIXADDR(x, y) (lcd_dma.addr + \
2093 ((y) * vxres * yscale + (x) * xscale) * es)
5e1c5ff4 2094#define PIXSTEP(sx, sy, dx, dy) (PIXADDR(dx, dy) - PIXADDR(sx, sy) - es + 1)
97b7f715 2095
5e1c5ff4
TL		 2096 switch (lcd_dma.rotate) {
2097 case 0:
2098 if (!lcd_dma.mirror) {
2099 top = PIXADDR(0, 0);
2100 bottom = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1);
2101 /* 1510 DMA requires the bottom address to be 2 more
2102 * than the actual last memory access location. */
2103 if (omap_dma_in_1510_mode() &&
97b7f715
TL		 2104 lcd_dma.data_type == OMAP_DMA_DATA_TYPE_S32)
2105 bottom += 2;
5e1c5ff4
TL		 2106 ei = PIXSTEP(0, 0, 1, 0);
2107 fi = PIXSTEP(lcd_dma.xres - 1, 0, 0, 1);
2108 } else {
2109 top = PIXADDR(lcd_dma.xres - 1, 0);
2110 bottom = PIXADDR(0, lcd_dma.yres - 1);
2111 ei = PIXSTEP(1, 0, 0, 0);
2112 fi = PIXSTEP(0, 0, lcd_dma.xres - 1, 1);
2113 }
2114 en = lcd_dma.xres;
2115 fn = lcd_dma.yres;
2116 break;
2117 case 90:
2118 if (!lcd_dma.mirror) {
2119 top = PIXADDR(0, lcd_dma.yres - 1);
2120 bottom = PIXADDR(lcd_dma.xres - 1, 0);
2121 ei = PIXSTEP(0, 1, 0, 0);
2122 fi = PIXSTEP(0, 0, 1, lcd_dma.yres - 1);
2123 } else {
2124 top = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1);
2125 bottom = PIXADDR(0, 0);
2126 ei = PIXSTEP(0, 1, 0, 0);
2127 fi = PIXSTEP(1, 0, 0, lcd_dma.yres - 1);
2128 }
2129 en = lcd_dma.yres;
2130 fn = lcd_dma.xres;
2131 break;
2132 case 180:
2133 if (!lcd_dma.mirror) {
2134 top = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1);
2135 bottom = PIXADDR(0, 0);
2136 ei = PIXSTEP(1, 0, 0, 0);
2137 fi = PIXSTEP(0, 1, lcd_dma.xres - 1, 0);
2138 } else {
2139 top = PIXADDR(0, lcd_dma.yres - 1);
2140 bottom = PIXADDR(lcd_dma.xres - 1, 0);
2141 ei = PIXSTEP(0, 0, 1, 0);
2142 fi = PIXSTEP(lcd_dma.xres - 1, 1, 0, 0);
2143 }
2144 en = lcd_dma.xres;
2145 fn = lcd_dma.yres;
2146 break;
2147 case 270:
2148 if (!lcd_dma.mirror) {
2149 top = PIXADDR(lcd_dma.xres - 1, 0);
2150 bottom = PIXADDR(0, lcd_dma.yres - 1);
2151 ei = PIXSTEP(0, 0, 0, 1);
2152 fi = PIXSTEP(1, lcd_dma.yres - 1, 0, 0);
2153 } else {
2154 top = PIXADDR(0, 0);
2155 bottom = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1);
2156 ei = PIXSTEP(0, 0, 0, 1);
2157 fi = PIXSTEP(0, lcd_dma.yres - 1, 1, 0);
2158 }
2159 en = lcd_dma.yres;
2160 fn = lcd_dma.xres;
2161 break;
2162 default:
2163 BUG();
6cbdc8c5 2164 return; /* Suppress warning about uninitialized vars */
5e1c5ff4
TL		 2165 }
2166
2167 if (omap_dma_in_1510_mode()) {
2168 omap_writew(top >> 16, OMAP1510_DMA_LCD_TOP_F1_U);
2169 omap_writew(top, OMAP1510_DMA_LCD_TOP_F1_L);
2170 omap_writew(bottom >> 16, OMAP1510_DMA_LCD_BOT_F1_U);
2171 omap_writew(bottom, OMAP1510_DMA_LCD_BOT_F1_L);
2172
2173 return;
2174 }
2175
2176 /* 1610 regs */
2177 omap_writew(top >> 16, OMAP1610_DMA_LCD_TOP_B1_U);
2178 omap_writew(top, OMAP1610_DMA_LCD_TOP_B1_L);
2179 omap_writew(bottom >> 16, OMAP1610_DMA_LCD_BOT_B1_U);
2180 omap_writew(bottom, OMAP1610_DMA_LCD_BOT_B1_L);
2181
2182 omap_writew(en, OMAP1610_DMA_LCD_SRC_EN_B1);
2183 omap_writew(fn, OMAP1610_DMA_LCD_SRC_FN_B1);
2184
2185 w = omap_readw(OMAP1610_DMA_LCD_CSDP);
2186 w &= ~0x03;
2187 w |= lcd_dma.data_type;
2188 omap_writew(w, OMAP1610_DMA_LCD_CSDP);
2189
2190 w = omap_readw(OMAP1610_DMA_LCD_CTRL);
2191 /* Always set the source port as SDRAM for now*/
2192 w &= ~(0x03 << 6);
5e1c5ff4 2193 if (lcd_dma.callback != NULL)
1a8bfa1e 2194 w |= 1 << 1; /* Block interrupt enable */
5e1c5ff4
TL		 2195 else
2196 w &= ~(1 << 1);
2197 omap_writew(w, OMAP1610_DMA_LCD_CTRL);
2198
2199 if (!(lcd_dma.rotate || lcd_dma.mirror ||
2200 lcd_dma.vxres || lcd_dma.xscale || lcd_dma.yscale))
2201 return;
2202
2203 w = omap_readw(OMAP1610_DMA_LCD_CCR);
2204 /* Set the double-indexed addressing mode */
2205 w |= (0x03 << 12);
2206 omap_writew(w, OMAP1610_DMA_LCD_CCR);
2207
2208 omap_writew(ei, OMAP1610_DMA_LCD_SRC_EI_B1);
2209 omap_writew(fi >> 16, OMAP1610_DMA_LCD_SRC_FI_B1_U);
2210 omap_writew(fi, OMAP1610_DMA_LCD_SRC_FI_B1_L);
2211}
2212
0cd61b68 2213static irqreturn_t lcd_dma_irq_handler(int irq, void *dev_id)
5e1c5ff4
TL		 2214{
2215 u16 w;
2216
2217 w = omap_readw(OMAP1610_DMA_LCD_CTRL);
2218 if (unlikely(!(w & (1 << 3)))) {
2219 printk(KERN_WARNING "Spurious LCD DMA IRQ\n");
2220 return IRQ_NONE;
2221 }
2222 /* Ack the IRQ */
2223 w |= (1 << 3);
2224 omap_writew(w, OMAP1610_DMA_LCD_CTRL);
2225 lcd_dma.active = 0;
2226 if (lcd_dma.callback != NULL)
2227 lcd_dma.callback(w, lcd_dma.cb_data);
2228
2229 return IRQ_HANDLED;
2230}
2231
97b7f715 2232int omap_request_lcd_dma(void (*callback)(u16 status, void *data),
5e1c5ff4
TL		 2233 void *data)
2234{
2235 spin_lock_irq(&lcd_dma.lock);
2236 if (lcd_dma.reserved) {
2237 spin_unlock_irq(&lcd_dma.lock);
2238 printk(KERN_ERR "LCD DMA channel already reserved\n");
2239 BUG();
2240 return -EBUSY;
2241 }
2242 lcd_dma.reserved = 1;
2243 spin_unlock_irq(&lcd_dma.lock);
2244 lcd_dma.callback = callback;
2245 lcd_dma.cb_data = data;
2246 lcd_dma.active = 0;
2247 lcd_dma.single_transfer = 0;
2248 lcd_dma.rotate = 0;
2249 lcd_dma.vxres = 0;
2250 lcd_dma.mirror = 0;
2251 lcd_dma.xscale = 0;
2252 lcd_dma.yscale = 0;
2253 lcd_dma.ext_ctrl = 0;
2254 lcd_dma.src_port = 0;
2255
2256 return 0;
2257}
97b7f715 2258EXPORT_SYMBOL(omap_request_lcd_dma);
5e1c5ff4
TL		 2259
2260void omap_free_lcd_dma(void)
2261{
2262 spin_lock(&lcd_dma.lock);
2263 if (!lcd_dma.reserved) {
2264 spin_unlock(&lcd_dma.lock);
2265 printk(KERN_ERR "LCD DMA is not reserved\n");
2266 BUG();
2267 return;
2268 }
2269 if (!enable_1510_mode)
1a8bfa1e
TL		 2270 omap_writew(omap_readw(OMAP1610_DMA_LCD_CCR) & ~1,
2271 OMAP1610_DMA_LCD_CCR);
5e1c5ff4
TL		 2272 lcd_dma.reserved = 0;
2273 spin_unlock(&lcd_dma.lock);
2274}
97b7f715 2275EXPORT_SYMBOL(omap_free_lcd_dma);
5e1c5ff4
TL		 2276
2277void omap_enable_lcd_dma(void)
2278{
2279 u16 w;
2280
97b7f715
TL		 2281 /*
2282 * Set the Enable bit only if an external controller is
5e1c5ff4
TL		 2283 * connected. Otherwise the OMAP internal controller will
2284 * start the transfer when it gets enabled.
2285 */
2286 if (enable_1510_mode || !lcd_dma.ext_ctrl)
2287 return;
bb13b5fd
TL		 2288
2289 w = omap_readw(OMAP1610_DMA_LCD_CTRL);
2290 w |= 1 << 8;
2291 omap_writew(w, OMAP1610_DMA_LCD_CTRL);
2292
92105bb7
TL		 2293 lcd_dma.active = 1;
2294
5e1c5ff4
TL		 2295 w = omap_readw(OMAP1610_DMA_LCD_CCR);
2296 w |= 1 << 7;
2297 omap_writew(w, OMAP1610_DMA_LCD_CCR);
5e1c5ff4 2298}
97b7f715 2299EXPORT_SYMBOL(omap_enable_lcd_dma);
5e1c5ff4
TL		 2300
2301void omap_setup_lcd_dma(void)
2302{
2303 BUG_ON(lcd_dma.active);
2304 if (!enable_1510_mode) {
2305 /* Set some reasonable defaults */
2306 omap_writew(0x5440, OMAP1610_DMA_LCD_CCR);
2307 omap_writew(0x9102, OMAP1610_DMA_LCD_CSDP);
2308 omap_writew(0x0004, OMAP1610_DMA_LCD_LCH_CTRL);
2309 }
2310 set_b1_regs();
2311 if (!enable_1510_mode) {
2312 u16 w;
2313
2314 w = omap_readw(OMAP1610_DMA_LCD_CCR);
97b7f715
TL		 2315 /*
2316 * If DMA was already active set the end_prog bit to have
5e1c5ff4
TL		 2317 * the programmed register set loaded into the active
2318 * register set.
2319 */
2320 w |= 1 << 11; /* End_prog */
2321 if (!lcd_dma.single_transfer)
97b7f715 2322 w |= (3 << 8); /* Auto_init, repeat */
5e1c5ff4
TL		 2323 omap_writew(w, OMAP1610_DMA_LCD_CCR);
2324 }
2325}
97b7f715 2326EXPORT_SYMBOL(omap_setup_lcd_dma);
5e1c5ff4
TL		 2327
2328void omap_stop_lcd_dma(void)
2329{
bb13b5fd
TL		 2330 u16 w;
2331
5e1c5ff4 2332 lcd_dma.active = 0;
bb13b5fd
TL		 2333 if (enable_1510_mode || !lcd_dma.ext_ctrl)
2334 return;
2335
2336 w = omap_readw(OMAP1610_DMA_LCD_CCR);
2337 w &= ~(1 << 7);
2338 omap_writew(w, OMAP1610_DMA_LCD_CCR);
2339
2340 w = omap_readw(OMAP1610_DMA_LCD_CTRL);
2341 w &= ~(1 << 8);
2342 omap_writew(w, OMAP1610_DMA_LCD_CTRL);
5e1c5ff4 2343}
97b7f715 2344EXPORT_SYMBOL(omap_stop_lcd_dma);
5e1c5ff4 2345
1a8bfa1e 2346/*----------------------------------------------------------------------------*/
bb13b5fd 2347
5e1c5ff4
TL		 2348static int __init omap_init_dma(void)
2349{
7e9bf847 2350 unsigned long base;
5e1c5ff4
TL		 2351 int ch, r;
2352
0499bdeb 2353 if (cpu_class_is_omap1()) {
7e9bf847 2354 base = OMAP1_DMA_BASE;
4d96372e 2355 dma_lch_count = OMAP1_LOGICAL_DMA_CH_COUNT;
0499bdeb 2356 } else if (cpu_is_omap24xx()) {
7e9bf847 2357 base = OMAP24XX_DMA4_BASE;
4d96372e 2358 dma_lch_count = OMAP_DMA4_LOGICAL_DMA_CH_COUNT;
0499bdeb 2359 } else if (cpu_is_omap34xx()) {
7e9bf847 2360 base = OMAP34XX_DMA4_BASE;
0499bdeb 2361 dma_lch_count = OMAP_DMA4_LOGICAL_DMA_CH_COUNT;
44169075 2362 } else if (cpu_is_omap44xx()) {
7e9bf847 2363 base = OMAP44XX_DMA4_BASE;
44169075 2364 dma_lch_count = OMAP_DMA4_LOGICAL_DMA_CH_COUNT;
0499bdeb
TL		 2365 } else {
2366 pr_err("DMA init failed for unsupported omap\n");
2367 return -ENODEV;
2368 }
4d96372e 2369
7e9bf847
TL		 2370 omap_dma_base = ioremap(base, SZ_4K);
2371 BUG_ON(!omap_dma_base);
2372
2263f022
SS		 2373 if (cpu_class_is_omap2() && omap_dma_reserve_channels
2374 && (omap_dma_reserve_channels <= dma_lch_count))
2375 dma_lch_count = omap_dma_reserve_channels;
2376
4d96372e
TL		 2377 dma_chan = kzalloc(sizeof(struct omap_dma_lch) * dma_lch_count,
2378 GFP_KERNEL);
7e9bf847
TL		 2379 if (!dma_chan) {
2380 r = -ENOMEM;
2381 goto out_unmap;
2382 }
4d96372e
TL		 2383
2384 if (cpu_class_is_omap2()) {
2385 dma_linked_lch = kzalloc(sizeof(struct dma_link_info) *
2386 dma_lch_count, GFP_KERNEL);
2387 if (!dma_linked_lch) {
7e9bf847
TL		 2388 r = -ENOMEM;
2389 goto out_free;
4d96372e
TL		 2390 }
2391 }
2392
1a8bfa1e
TL		 2393 if (cpu_is_omap15xx()) {
2394 printk(KERN_INFO "DMA support for OMAP15xx initialized\n");
5e1c5ff4
TL		 2395 dma_chan_count = 9;
2396 enable_1510_mode = 1;
557096fe 2397 } else if (cpu_is_omap16xx() || cpu_is_omap7xx()) {
5e1c5ff4 2398 printk(KERN_INFO "OMAP DMA hardware version %d\n",
0499bdeb 2399 dma_read(HW_ID));
5e1c5ff4 2400 printk(KERN_INFO "DMA capabilities: %08x:%08x:%04x:%04x:%04x\n",
0499bdeb
TL		 2401 (dma_read(CAPS_0_U) << 16) |
2402 dma_read(CAPS_0_L),
2403 (dma_read(CAPS_1_U) << 16) |
2404 dma_read(CAPS_1_L),
2405 dma_read(CAPS_2), dma_read(CAPS_3),
2406 dma_read(CAPS_4));
5e1c5ff4
TL		 2407 if (!enable_1510_mode) {
2408 u16 w;
2409
2410 /* Disable OMAP 3.0/3.1 compatibility mode. */
0499bdeb 2411 w = dma_read(GSCR);
5e1c5ff4 2412 w |= 1 << 3;
0499bdeb 2413 dma_write(w, GSCR);
5e1c5ff4
TL		 2414 dma_chan_count = 16;
2415 } else
2416 dma_chan_count = 9;
b5beef5d
ID		 2417 if (cpu_is_omap16xx()) {
2418 u16 w;
2419
2420 /* this would prevent OMAP sleep */
2421 w = omap_readw(OMAP1610_DMA_LCD_CTRL);
2422 w &= ~(1 << 8);
2423 omap_writew(w, OMAP1610_DMA_LCD_CTRL);
2424 }
f8151e5c 2425 } else if (cpu_class_is_omap2()) {
0499bdeb 2426 u8 revision = dma_read(REVISION) & 0xff;
1a8bfa1e
TL		 2427 printk(KERN_INFO "OMAP DMA hardware revision %d.%d\n",
2428 revision >> 4, revision & 0xf);
2263f022 2429 dma_chan_count = dma_lch_count;
5e1c5ff4
TL		 2430 } else {
2431 dma_chan_count = 0;
2432 return 0;
2433 }
2434
5e1c5ff4
TL		 2435 spin_lock_init(&lcd_dma.lock);
2436 spin_lock_init(&dma_chan_lock);
5e1c5ff4
TL		 2437
2438 for (ch = 0; ch < dma_chan_count; ch++) {
1a8bfa1e 2439 omap_clear_dma(ch);
5e1c5ff4
TL		 2440 dma_chan[ch].dev_id = -1;
2441 dma_chan[ch].next_lch = -1;
2442
2443 if (ch >= 6 && enable_1510_mode)
2444 continue;
2445
1a8bfa1e 2446 if (cpu_class_is_omap1()) {
97b7f715
TL		 2447 /*
2448 * request_irq() doesn't like dev_id (ie. ch) being
2449 * zero, so we have to kludge around this.
2450 */
1a8bfa1e
TL		 2451 r = request_irq(omap1_dma_irq[ch],
2452 omap1_dma_irq_handler, 0, "DMA",
2453 (void *) (ch + 1));
2454 if (r != 0) {
2455 int i;
2456
2457 printk(KERN_ERR "unable to request IRQ %d "
2458 "for DMA (error %d)\n",
2459 omap1_dma_irq[ch], r);
2460 for (i = 0; i < ch; i++)
2461 free_irq(omap1_dma_irq[i],
2462 (void *) (i + 1));
7e9bf847 2463 goto out_free;
1a8bfa1e
TL		 2464 }
2465 }
2466 }
2467
44169075 2468 if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx())
f8151e5c
AG		 2469 omap_dma_set_global_params(DMA_DEFAULT_ARB_RATE,
2470 DMA_DEFAULT_FIFO_DEPTH, 0);
2471
44169075
SS		 2472 if (cpu_class_is_omap2()) {
2473 int irq;
2474 if (cpu_is_omap44xx())
2475 irq = INT_44XX_SDMA_IRQ0;
2476 else
2477 irq = INT_24XX_SDMA_IRQ0;
2478 setup_irq(irq, &omap24xx_dma_irq);
2479 }
1a8bfa1e 2480
aecedb94
KJ		 2481 /* Enable smartidle idlemodes and autoidle */
2482 if (cpu_is_omap34xx()) {
2483 u32 v = dma_read(OCP_SYSCONFIG);
2484 v &= ~(DMA_SYSCONFIG_MIDLEMODE_MASK |
2485 DMA_SYSCONFIG_SIDLEMODE_MASK |
2486 DMA_SYSCONFIG_AUTOIDLE);
2487 v |= (DMA_SYSCONFIG_MIDLEMODE(DMA_IDLEMODE_SMARTIDLE) |
2488 DMA_SYSCONFIG_SIDLEMODE(DMA_IDLEMODE_SMARTIDLE) |
2489 DMA_SYSCONFIG_AUTOIDLE);
2490 dma_write(v , OCP_SYSCONFIG);
2491 }
2492
2493
1a8bfa1e
TL		 2494 /* FIXME: Update LCD DMA to work on 24xx */
2495 if (cpu_class_is_omap1()) {
2496 r = request_irq(INT_DMA_LCD, lcd_dma_irq_handler, 0,
2497 "LCD DMA", NULL);
5e1c5ff4
TL		 2498 if (r != 0) {
2499 int i;
2500
1a8bfa1e
TL		 2501 printk(KERN_ERR "unable to request IRQ for LCD DMA "
2502 "(error %d)\n", r);
2503 for (i = 0; i < dma_chan_count; i++)
2504 free_irq(omap1_dma_irq[i], (void *) (i + 1));
7e9bf847 2505 goto out_free;
5e1c5ff4
TL		 2506 }
2507 }
5e1c5ff4 2508
5e1c5ff4 2509 return 0;
7e9bf847
TL		 2510
2511out_free:
2512 kfree(dma_chan);
2513
2514out_unmap:
2515 iounmap(omap_dma_base);
2516
2517 return r;
5e1c5ff4
TL		 2518}
2519
2520arch_initcall(omap_init_dma);
2521
2263f022
SS		 2522/*
2523 * Reserve the omap SDMA channels using cmdline bootarg
2524 * "omap_dma_reserve_ch=". The valid range is 1 to 32
2525 */
2526static int __init omap_dma_cmdline_reserve_ch(char *str)
2527{
2528 if (get_option(&str, &omap_dma_reserve_channels) != 1)
2529 omap_dma_reserve_channels = 0;
2530 return 1;
2531}
2532
2533__setup("omap_dma_reserve_ch=", omap_dma_cmdline_reserve_ch);
2534
5e1c5ff4 2535
Linux kernel - Deliverables
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