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ARM: OMAP: use gpio_to_irq
[deliverable/linux.git] / arch / arm / plat-omap / gpio.c
CommitLineData
5e1c5ff4
TL		 1/*
2 * linux/arch/arm/plat-omap/gpio.c
3 *
4 * Support functions for OMAP GPIO
5 *
92105bb7 6 * Copyright (C) 2003-2005 Nokia Corporation
96de0e25 7 * Written by Juha Yrjölä <juha.yrjola@nokia.com>
5e1c5ff4
TL		 8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
5e1c5ff4
TL		 14#include <linux/init.h>
15#include <linux/module.h>
5e1c5ff4 16#include <linux/interrupt.h>
92105bb7
TL		 17#include <linux/sysdev.h>
18#include <linux/err.h>
f8ce2547 19#include <linux/clk.h>
fced80c7 20#include <linux/io.h>
5e1c5ff4 21
a09e64fb 22#include <mach/hardware.h>
5e1c5ff4 23#include <asm/irq.h>
a09e64fb
RK		 24#include <mach/irqs.h>
25#include <mach/gpio.h>
5e1c5ff4
TL		 26#include <asm/mach/irq.h>
27
5e1c5ff4
TL		 28/*
29 * OMAP1510 GPIO registers
30 */
7c7095aa 31#define OMAP1510_GPIO_BASE IO_ADDRESS(0xfffce000)
5e1c5ff4
TL		 32#define OMAP1510_GPIO_DATA_INPUT 0x00
33#define OMAP1510_GPIO_DATA_OUTPUT 0x04
34#define OMAP1510_GPIO_DIR_CONTROL 0x08
35#define OMAP1510_GPIO_INT_CONTROL 0x0c
36#define OMAP1510_GPIO_INT_MASK 0x10
37#define OMAP1510_GPIO_INT_STATUS 0x14
38#define OMAP1510_GPIO_PIN_CONTROL 0x18
39
40#define OMAP1510_IH_GPIO_BASE 64
41
42/*
43 * OMAP1610 specific GPIO registers
44 */
7c7095aa
RK		 45#define OMAP1610_GPIO1_BASE IO_ADDRESS(0xfffbe400)
46#define OMAP1610_GPIO2_BASE IO_ADDRESS(0xfffbec00)
47#define OMAP1610_GPIO3_BASE IO_ADDRESS(0xfffbb400)
48#define OMAP1610_GPIO4_BASE IO_ADDRESS(0xfffbbc00)
5e1c5ff4
TL		 49#define OMAP1610_GPIO_REVISION 0x0000
50#define OMAP1610_GPIO_SYSCONFIG 0x0010
51#define OMAP1610_GPIO_SYSSTATUS 0x0014
52#define OMAP1610_GPIO_IRQSTATUS1 0x0018
53#define OMAP1610_GPIO_IRQENABLE1 0x001c
92105bb7 54#define OMAP1610_GPIO_WAKEUPENABLE 0x0028
5e1c5ff4
TL		 55#define OMAP1610_GPIO_DATAIN 0x002c
56#define OMAP1610_GPIO_DATAOUT 0x0030
57#define OMAP1610_GPIO_DIRECTION 0x0034
58#define OMAP1610_GPIO_EDGE_CTRL1 0x0038
59#define OMAP1610_GPIO_EDGE_CTRL2 0x003c
60#define OMAP1610_GPIO_CLEAR_IRQENABLE1 0x009c
92105bb7 61#define OMAP1610_GPIO_CLEAR_WAKEUPENA 0x00a8
5e1c5ff4
TL		 62#define OMAP1610_GPIO_CLEAR_DATAOUT 0x00b0
63#define OMAP1610_GPIO_SET_IRQENABLE1 0x00dc
92105bb7 64#define OMAP1610_GPIO_SET_WAKEUPENA 0x00e8
5e1c5ff4
TL		 65#define OMAP1610_GPIO_SET_DATAOUT 0x00f0
66
67/*
68 * OMAP730 specific GPIO registers
69 */
7c7095aa
RK		 70#define OMAP730_GPIO1_BASE IO_ADDRESS(0xfffbc000)
71#define OMAP730_GPIO2_BASE IO_ADDRESS(0xfffbc800)
72#define OMAP730_GPIO3_BASE IO_ADDRESS(0xfffbd000)
73#define OMAP730_GPIO4_BASE IO_ADDRESS(0xfffbd800)
74#define OMAP730_GPIO5_BASE IO_ADDRESS(0xfffbe000)
75#define OMAP730_GPIO6_BASE IO_ADDRESS(0xfffbe800)
5e1c5ff4
TL		 76#define OMAP730_GPIO_DATA_INPUT 0x00
77#define OMAP730_GPIO_DATA_OUTPUT 0x04
78#define OMAP730_GPIO_DIR_CONTROL 0x08
79#define OMAP730_GPIO_INT_CONTROL 0x0c
80#define OMAP730_GPIO_INT_MASK 0x10
81#define OMAP730_GPIO_INT_STATUS 0x14
82
92105bb7
TL		 83/*
84 * omap24xx specific GPIO registers
85 */
7c7095aa
RK		 86#define OMAP242X_GPIO1_BASE IO_ADDRESS(0x48018000)
87#define OMAP242X_GPIO2_BASE IO_ADDRESS(0x4801a000)
88#define OMAP242X_GPIO3_BASE IO_ADDRESS(0x4801c000)
89#define OMAP242X_GPIO4_BASE IO_ADDRESS(0x4801e000)
56a25641 90
7c7095aa
RK		 91#define OMAP243X_GPIO1_BASE IO_ADDRESS(0x4900C000)
92#define OMAP243X_GPIO2_BASE IO_ADDRESS(0x4900E000)
93#define OMAP243X_GPIO3_BASE IO_ADDRESS(0x49010000)
94#define OMAP243X_GPIO4_BASE IO_ADDRESS(0x49012000)
95#define OMAP243X_GPIO5_BASE IO_ADDRESS(0x480B6000)
56a25641 96
92105bb7
TL		 97#define OMAP24XX_GPIO_REVISION 0x0000
98#define OMAP24XX_GPIO_SYSCONFIG 0x0010
99#define OMAP24XX_GPIO_SYSSTATUS 0x0014
100#define OMAP24XX_GPIO_IRQSTATUS1 0x0018
bee7930f
HD		 101#define OMAP24XX_GPIO_IRQSTATUS2 0x0028
102#define OMAP24XX_GPIO_IRQENABLE2 0x002c
92105bb7 103#define OMAP24XX_GPIO_IRQENABLE1 0x001c
723fdb78 104#define OMAP24XX_GPIO_WAKE_EN 0x0020
92105bb7
TL		 105#define OMAP24XX_GPIO_CTRL 0x0030
106#define OMAP24XX_GPIO_OE 0x0034
107#define OMAP24XX_GPIO_DATAIN 0x0038
108#define OMAP24XX_GPIO_DATAOUT 0x003c
109#define OMAP24XX_GPIO_LEVELDETECT0 0x0040
110#define OMAP24XX_GPIO_LEVELDETECT1 0x0044
111#define OMAP24XX_GPIO_RISINGDETECT 0x0048
112#define OMAP24XX_GPIO_FALLINGDETECT 0x004c
5eb3bb9c
KH		 113#define OMAP24XX_GPIO_DEBOUNCE_EN 0x0050
114#define OMAP24XX_GPIO_DEBOUNCE_VAL 0x0054
92105bb7
TL		 115#define OMAP24XX_GPIO_CLEARIRQENABLE1 0x0060
116#define OMAP24XX_GPIO_SETIRQENABLE1 0x0064
117#define OMAP24XX_GPIO_CLEARWKUENA 0x0080
118#define OMAP24XX_GPIO_SETWKUENA 0x0084
119#define OMAP24XX_GPIO_CLEARDATAOUT 0x0090
120#define OMAP24XX_GPIO_SETDATAOUT 0x0094
121
5492fb1a
SMK		 122/*
123 * omap34xx specific GPIO registers
124 */
125
7c7095aa
RK		 126#define OMAP34XX_GPIO1_BASE IO_ADDRESS(0x48310000)
127#define OMAP34XX_GPIO2_BASE IO_ADDRESS(0x49050000)
128#define OMAP34XX_GPIO3_BASE IO_ADDRESS(0x49052000)
129#define OMAP34XX_GPIO4_BASE IO_ADDRESS(0x49054000)
130#define OMAP34XX_GPIO5_BASE IO_ADDRESS(0x49056000)
131#define OMAP34XX_GPIO6_BASE IO_ADDRESS(0x49058000)
5492fb1a 132
7c7095aa 133#define OMAP_MPUIO_VBASE IO_ADDRESS(OMAP_MPUIO_BASE)
5492fb1a 134
5e1c5ff4 135struct gpio_bank {
92105bb7 136 void __iomem *base;
5e1c5ff4
TL		 137 u16 irq;
138 u16 virtual_irq_start;
92105bb7 139 int method;
5492fb1a 140#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
92105bb7
TL		 141 u32 suspend_wakeup;
142 u32 saved_wakeup;
3ac4fa99 143#endif
5492fb1a 144#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
3ac4fa99
JY		 145 u32 non_wakeup_gpios;
146 u32 enabled_non_wakeup_gpios;
147
148 u32 saved_datain;
149 u32 saved_fallingdetect;
150 u32 saved_risingdetect;
151#endif
b144ff6f 152 u32 level_mask;
5e1c5ff4 153 spinlock_t lock;
52e31344 154 struct gpio_chip chip;
89db9482 155 struct clk *dbck;
5e1c5ff4
TL		 156};
157
158#define METHOD_MPUIO 0
159#define METHOD_GPIO_1510 1
160#define METHOD_GPIO_1610 2
161#define METHOD_GPIO_730 3
92105bb7 162#define METHOD_GPIO_24XX 4
5e1c5ff4 163
92105bb7 164#ifdef CONFIG_ARCH_OMAP16XX
5e1c5ff4 165static struct gpio_bank gpio_bank_1610[5] = {
7c7095aa 166 { OMAP_MPUIO_VBASE, INT_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO},
5e1c5ff4
TL		 167 { OMAP1610_GPIO1_BASE, INT_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_1610 },
168 { OMAP1610_GPIO2_BASE, INT_1610_GPIO_BANK2, IH_GPIO_BASE + 16, METHOD_GPIO_1610 },
169 { OMAP1610_GPIO3_BASE, INT_1610_GPIO_BANK3, IH_GPIO_BASE + 32, METHOD_GPIO_1610 },
170 { OMAP1610_GPIO4_BASE, INT_1610_GPIO_BANK4, IH_GPIO_BASE + 48, METHOD_GPIO_1610 },
171};
172#endif
173
1a8bfa1e 174#ifdef CONFIG_ARCH_OMAP15XX
5e1c5ff4 175static struct gpio_bank gpio_bank_1510[2] = {
7c7095aa 176 { OMAP_MPUIO_VBASE, INT_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO },
5e1c5ff4
TL		 177 { OMAP1510_GPIO_BASE, INT_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_1510 }
178};
179#endif
180
181#ifdef CONFIG_ARCH_OMAP730
182static struct gpio_bank gpio_bank_730[7] = {
7c7095aa 183 { OMAP_MPUIO_VBASE, INT_730_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO },
5e1c5ff4
TL		 184 { OMAP730_GPIO1_BASE, INT_730_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_730 },
185 { OMAP730_GPIO2_BASE, INT_730_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_730 },
186 { OMAP730_GPIO3_BASE, INT_730_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_730 },
187 { OMAP730_GPIO4_BASE, INT_730_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_730 },
188 { OMAP730_GPIO5_BASE, INT_730_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_730 },
189 { OMAP730_GPIO6_BASE, INT_730_GPIO_BANK6, IH_GPIO_BASE + 160, METHOD_GPIO_730 },
190};
191#endif
192
92105bb7 193#ifdef CONFIG_ARCH_OMAP24XX
56a25641
SMK		 194
195static struct gpio_bank gpio_bank_242x[4] = {
196 { OMAP242X_GPIO1_BASE, INT_24XX_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_24XX },
197 { OMAP242X_GPIO2_BASE, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_24XX },
198 { OMAP242X_GPIO3_BASE, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_24XX },
199 { OMAP242X_GPIO4_BASE, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_24XX },
92105bb7 200};
56a25641
SMK		 201
202static struct gpio_bank gpio_bank_243x[5] = {
203 { OMAP243X_GPIO1_BASE, INT_24XX_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_24XX },
204 { OMAP243X_GPIO2_BASE, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_24XX },
205 { OMAP243X_GPIO3_BASE, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_24XX },
206 { OMAP243X_GPIO4_BASE, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_24XX },
207 { OMAP243X_GPIO5_BASE, INT_24XX_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_24XX },
208};
209
92105bb7
TL		 210#endif
211
5492fb1a
SMK		 212#ifdef CONFIG_ARCH_OMAP34XX
213static struct gpio_bank gpio_bank_34xx[6] = {
214 { OMAP34XX_GPIO1_BASE, INT_34XX_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_24XX },
215 { OMAP34XX_GPIO2_BASE, INT_34XX_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_24XX },
216 { OMAP34XX_GPIO3_BASE, INT_34XX_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_24XX },
217 { OMAP34XX_GPIO4_BASE, INT_34XX_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_24XX },
218 { OMAP34XX_GPIO5_BASE, INT_34XX_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_24XX },
219 { OMAP34XX_GPIO6_BASE, INT_34XX_GPIO_BANK6, IH_GPIO_BASE + 160, METHOD_GPIO_24XX },
220};
221
222#endif
223
5e1c5ff4
TL		 224static struct gpio_bank *gpio_bank;
225static int gpio_bank_count;
226
227static inline struct gpio_bank *get_gpio_bank(int gpio)
228{
6e60e79a 229 if (cpu_is_omap15xx()) {
5e1c5ff4
TL		 230 if (OMAP_GPIO_IS_MPUIO(gpio))
231 return &gpio_bank[0];
232 return &gpio_bank[1];
233 }
5e1c5ff4
TL		 234 if (cpu_is_omap16xx()) {
235 if (OMAP_GPIO_IS_MPUIO(gpio))
236 return &gpio_bank[0];
237 return &gpio_bank[1 + (gpio >> 4)];
238 }
5e1c5ff4
TL		 239 if (cpu_is_omap730()) {
240 if (OMAP_GPIO_IS_MPUIO(gpio))
241 return &gpio_bank[0];
242 return &gpio_bank[1 + (gpio >> 5)];
243 }
92105bb7
TL		 244 if (cpu_is_omap24xx())
245 return &gpio_bank[gpio >> 5];
5492fb1a
SMK		 246 if (cpu_is_omap34xx())
247 return &gpio_bank[gpio >> 5];
5e1c5ff4
TL		 248}
249
250static inline int get_gpio_index(int gpio)
251{
252 if (cpu_is_omap730())
253 return gpio & 0x1f;
92105bb7
TL		 254 if (cpu_is_omap24xx())
255 return gpio & 0x1f;
5492fb1a
SMK		 256 if (cpu_is_omap34xx())
257 return gpio & 0x1f;
92105bb7 258 return gpio & 0x0f;
5e1c5ff4
TL		 259}
260
261static inline int gpio_valid(int gpio)
262{
263 if (gpio < 0)
264 return -1;
d11ac979 265 if (cpu_class_is_omap1() && OMAP_GPIO_IS_MPUIO(gpio)) {
193e68be 266 if (gpio >= OMAP_MAX_GPIO_LINES + 16)
5e1c5ff4
TL		 267 return -1;
268 return 0;
269 }
6e60e79a 270 if (cpu_is_omap15xx() && gpio < 16)
5e1c5ff4 271 return 0;
5e1c5ff4
TL		 272 if ((cpu_is_omap16xx()) && gpio < 64)
273 return 0;
5e1c5ff4
TL		 274 if (cpu_is_omap730() && gpio < 192)
275 return 0;
92105bb7
TL		 276 if (cpu_is_omap24xx() && gpio < 128)
277 return 0;
5492fb1a
SMK		 278 if (cpu_is_omap34xx() && gpio < 160)
279 return 0;
5e1c5ff4
TL		 280 return -1;
281}
282
283static int check_gpio(int gpio)
284{
285 if (unlikely(gpio_valid(gpio)) < 0) {
286 printk(KERN_ERR "omap-gpio: invalid GPIO %d\n", gpio);
287 dump_stack();
288 return -1;
289 }
290 return 0;
291}
292
293static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input)
294{
92105bb7 295 void __iomem *reg = bank->base;
5e1c5ff4
TL		 296 u32 l;
297
298 switch (bank->method) {
e5c56ed3 299#ifdef CONFIG_ARCH_OMAP1
5e1c5ff4
TL		 300 case METHOD_MPUIO:
301 reg += OMAP_MPUIO_IO_CNTL;
302 break;
e5c56ed3
DB		 303#endif
304#ifdef CONFIG_ARCH_OMAP15XX
5e1c5ff4
TL		 305 case METHOD_GPIO_1510:
306 reg += OMAP1510_GPIO_DIR_CONTROL;
307 break;
e5c56ed3
DB		 308#endif
309#ifdef CONFIG_ARCH_OMAP16XX
5e1c5ff4
TL		 310 case METHOD_GPIO_1610:
311 reg += OMAP1610_GPIO_DIRECTION;
312 break;
e5c56ed3
DB		 313#endif
314#ifdef CONFIG_ARCH_OMAP730
5e1c5ff4
TL		 315 case METHOD_GPIO_730:
316 reg += OMAP730_GPIO_DIR_CONTROL;
317 break;
e5c56ed3 318#endif
5492fb1a 319#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
92105bb7
TL		 320 case METHOD_GPIO_24XX:
321 reg += OMAP24XX_GPIO_OE;
322 break;
e5c56ed3
DB		 323#endif
324 default:
325 WARN_ON(1);
326 return;
5e1c5ff4
TL		 327 }
328 l = __raw_readl(reg);
329 if (is_input)
330 l |= 1 << gpio;
331 else
332 l &= ~(1 << gpio);
333 __raw_writel(l, reg);
334}
335
5e1c5ff4
TL		 336static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable)
337{
92105bb7 338 void __iomem *reg = bank->base;
5e1c5ff4
TL		 339 u32 l = 0;
340
341 switch (bank->method) {
e5c56ed3 342#ifdef CONFIG_ARCH_OMAP1
5e1c5ff4
TL		 343 case METHOD_MPUIO:
344 reg += OMAP_MPUIO_OUTPUT;
345 l = __raw_readl(reg);
346 if (enable)
347 l |= 1 << gpio;
348 else
349 l &= ~(1 << gpio);
350 break;
e5c56ed3
DB		 351#endif
352#ifdef CONFIG_ARCH_OMAP15XX
5e1c5ff4
TL		 353 case METHOD_GPIO_1510:
354 reg += OMAP1510_GPIO_DATA_OUTPUT;
355 l = __raw_readl(reg);
356 if (enable)
357 l |= 1 << gpio;
358 else
359 l &= ~(1 << gpio);
360 break;
e5c56ed3
DB		 361#endif
362#ifdef CONFIG_ARCH_OMAP16XX
5e1c5ff4
TL		 363 case METHOD_GPIO_1610:
364 if (enable)
365 reg += OMAP1610_GPIO_SET_DATAOUT;
366 else
367 reg += OMAP1610_GPIO_CLEAR_DATAOUT;
368 l = 1 << gpio;
369 break;
e5c56ed3
DB		 370#endif
371#ifdef CONFIG_ARCH_OMAP730
5e1c5ff4
TL		 372 case METHOD_GPIO_730:
373 reg += OMAP730_GPIO_DATA_OUTPUT;
374 l = __raw_readl(reg);
375 if (enable)
376 l |= 1 << gpio;
377 else
378 l &= ~(1 << gpio);
379 break;
e5c56ed3 380#endif
5492fb1a 381#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
92105bb7
TL		 382 case METHOD_GPIO_24XX:
383 if (enable)
384 reg += OMAP24XX_GPIO_SETDATAOUT;
385 else
386 reg += OMAP24XX_GPIO_CLEARDATAOUT;
387 l = 1 << gpio;
388 break;
e5c56ed3 389#endif
5e1c5ff4 390 default:
e5c56ed3 391 WARN_ON(1);
5e1c5ff4
TL		 392 return;
393 }
394 __raw_writel(l, reg);
395}
396
0b84b5ca 397static int __omap_get_gpio_datain(int gpio)
5e1c5ff4
TL		 398{
399 struct gpio_bank *bank;
92105bb7 400 void __iomem *reg;
5e1c5ff4
TL		 401
402 if (check_gpio(gpio) < 0)
e5c56ed3 403 return -EINVAL;
5e1c5ff4
TL		 404 bank = get_gpio_bank(gpio);
405 reg = bank->base;
406 switch (bank->method) {
e5c56ed3 407#ifdef CONFIG_ARCH_OMAP1
5e1c5ff4
TL		 408 case METHOD_MPUIO:
409 reg += OMAP_MPUIO_INPUT_LATCH;
410 break;
e5c56ed3
DB		 411#endif
412#ifdef CONFIG_ARCH_OMAP15XX
5e1c5ff4
TL		 413 case METHOD_GPIO_1510:
414 reg += OMAP1510_GPIO_DATA_INPUT;
415 break;
e5c56ed3
DB		 416#endif
417#ifdef CONFIG_ARCH_OMAP16XX
5e1c5ff4
TL		 418 case METHOD_GPIO_1610:
419 reg += OMAP1610_GPIO_DATAIN;
420 break;
e5c56ed3
DB		 421#endif
422#ifdef CONFIG_ARCH_OMAP730
5e1c5ff4
TL		 423 case METHOD_GPIO_730:
424 reg += OMAP730_GPIO_DATA_INPUT;
425 break;
e5c56ed3 426#endif
5492fb1a 427#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
92105bb7
TL		 428 case METHOD_GPIO_24XX:
429 reg += OMAP24XX_GPIO_DATAIN;
430 break;
e5c56ed3 431#endif
5e1c5ff4 432 default:
e5c56ed3 433 return -EINVAL;
5e1c5ff4 434 }
92105bb7
TL		 435 return (__raw_readl(reg)
436 & (1 << get_gpio_index(gpio))) != 0;
5e1c5ff4
TL		 437}
438
92105bb7
TL		 439#define MOD_REG_BIT(reg, bit_mask, set) \
440do { \
441 int l = __raw_readl(base + reg); \
442 if (set) l |= bit_mask; \
443 else l &= ~bit_mask; \
444 __raw_writel(l, base + reg); \
445} while(0)
446
5eb3bb9c
KH		 447void omap_set_gpio_debounce(int gpio, int enable)
448{
449 struct gpio_bank *bank;
450 void __iomem *reg;
451 u32 val, l = 1 << get_gpio_index(gpio);
452
453 if (cpu_class_is_omap1())
454 return;
455
456 bank = get_gpio_bank(gpio);
457 reg = bank->base;
458
459 reg += OMAP24XX_GPIO_DEBOUNCE_EN;
460 val = __raw_readl(reg);
461
89db9482 462 if (enable && !(val & l))
5eb3bb9c 463 val |= l;
89db9482 464 else if (!enable && val & l)
5eb3bb9c 465 val &= ~l;
89db9482
JH		 466 else
467 return;
468
469 if (cpu_is_omap34xx())
470 enable ? clk_enable(bank->dbck) : clk_disable(bank->dbck);
5eb3bb9c
KH		 471
472 __raw_writel(val, reg);
473}
474EXPORT_SYMBOL(omap_set_gpio_debounce);
475
476void omap_set_gpio_debounce_time(int gpio, int enc_time)
477{
478 struct gpio_bank *bank;
479 void __iomem *reg;
480
481 if (cpu_class_is_omap1())
482 return;
483
484 bank = get_gpio_bank(gpio);
485 reg = bank->base;
486
487 enc_time &= 0xff;
488 reg += OMAP24XX_GPIO_DEBOUNCE_VAL;
489 __raw_writel(enc_time, reg);
490}
491EXPORT_SYMBOL(omap_set_gpio_debounce_time);
492
5492fb1a 493#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
5eb3bb9c
KH		 494static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio,
495 int trigger)
5e1c5ff4 496{
3ac4fa99 497 void __iomem *base = bank->base;
92105bb7
TL		 498 u32 gpio_bit = 1 << gpio;
499
500 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT0, gpio_bit,
6cab4860 501 trigger & IRQ_TYPE_LEVEL_LOW);
92105bb7 502 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT1, gpio_bit,
6cab4860 503 trigger & IRQ_TYPE_LEVEL_HIGH);
92105bb7 504 MOD_REG_BIT(OMAP24XX_GPIO_RISINGDETECT, gpio_bit,
6cab4860 505 trigger & IRQ_TYPE_EDGE_RISING);
92105bb7 506 MOD_REG_BIT(OMAP24XX_GPIO_FALLINGDETECT, gpio_bit,
6cab4860 507 trigger & IRQ_TYPE_EDGE_FALLING);
5eb3bb9c 508
3ac4fa99
JY		 509 if (likely(!(bank->non_wakeup_gpios & gpio_bit))) {
510 if (trigger != 0)
5eb3bb9c
KH		 511 __raw_writel(1 << gpio, bank->base
512 + OMAP24XX_GPIO_SETWKUENA);
3ac4fa99 513 else
5eb3bb9c
KH		 514 __raw_writel(1 << gpio, bank->base
515 + OMAP24XX_GPIO_CLEARWKUENA);
3ac4fa99
JY		 516 } else {
517 if (trigger != 0)
518 bank->enabled_non_wakeup_gpios |= gpio_bit;
519 else
520 bank->enabled_non_wakeup_gpios &= ~gpio_bit;
521 }
5eb3bb9c 522
b144ff6f
KH		 523 bank->level_mask =
524 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0) |
525 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
92105bb7 526}
3ac4fa99 527#endif
92105bb7
TL		 528
529static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
530{
531 void __iomem *reg = bank->base;
532 u32 l = 0;
5e1c5ff4
TL		 533
534 switch (bank->method) {
e5c56ed3 535#ifdef CONFIG_ARCH_OMAP1
5e1c5ff4
TL		 536 case METHOD_MPUIO:
537 reg += OMAP_MPUIO_GPIO_INT_EDGE;
538 l = __raw_readl(reg);
6cab4860 539 if (trigger & IRQ_TYPE_EDGE_RISING)
5e1c5ff4 540 l |= 1 << gpio;
6cab4860 541 else if (trigger & IRQ_TYPE_EDGE_FALLING)
5e1c5ff4 542 l &= ~(1 << gpio);
92105bb7
TL		 543 else
544 goto bad;
5e1c5ff4 545 break;
e5c56ed3
DB		 546#endif
547#ifdef CONFIG_ARCH_OMAP15XX
5e1c5ff4
TL		 548 case METHOD_GPIO_1510:
549 reg += OMAP1510_GPIO_INT_CONTROL;
550 l = __raw_readl(reg);
6cab4860 551 if (trigger & IRQ_TYPE_EDGE_RISING)
5e1c5ff4 552 l |= 1 << gpio;
6cab4860 553 else if (trigger & IRQ_TYPE_EDGE_FALLING)
5e1c5ff4 554 l &= ~(1 << gpio);
92105bb7
TL		 555 else
556 goto bad;
5e1c5ff4 557 break;
e5c56ed3 558#endif
3ac4fa99 559#ifdef CONFIG_ARCH_OMAP16XX
5e1c5ff4 560 case METHOD_GPIO_1610:
5e1c5ff4
TL		 561 if (gpio & 0x08)
562 reg += OMAP1610_GPIO_EDGE_CTRL2;
563 else
564 reg += OMAP1610_GPIO_EDGE_CTRL1;
565 gpio &= 0x07;
566 l = __raw_readl(reg);
567 l &= ~(3 << (gpio << 1));
6cab4860 568 if (trigger & IRQ_TYPE_EDGE_RISING)
6e60e79a 569 l |= 2 << (gpio << 1);
6cab4860 570 if (trigger & IRQ_TYPE_EDGE_FALLING)
6e60e79a 571 l |= 1 << (gpio << 1);
3ac4fa99
JY		 572 if (trigger)
573 /* Enable wake-up during idle for dynamic tick */
574 __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_SET_WAKEUPENA);
575 else
576 __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA);
5e1c5ff4 577 break;
3ac4fa99
JY		 578#endif
579#ifdef CONFIG_ARCH_OMAP730
5e1c5ff4
TL		 580 case METHOD_GPIO_730:
581 reg += OMAP730_GPIO_INT_CONTROL;
582 l = __raw_readl(reg);
6cab4860 583 if (trigger & IRQ_TYPE_EDGE_RISING)
5e1c5ff4 584 l |= 1 << gpio;
6cab4860 585 else if (trigger & IRQ_TYPE_EDGE_FALLING)
5e1c5ff4 586 l &= ~(1 << gpio);
92105bb7
TL		 587 else
588 goto bad;
589 break;
3ac4fa99 590#endif
5492fb1a 591#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
92105bb7 592 case METHOD_GPIO_24XX:
3ac4fa99 593 set_24xx_gpio_triggering(bank, gpio, trigger);
5e1c5ff4 594 break;
3ac4fa99 595#endif
5e1c5ff4 596 default:
92105bb7 597 goto bad;
5e1c5ff4 598 }
92105bb7
TL		 599 __raw_writel(l, reg);
600 return 0;
601bad:
602 return -EINVAL;
5e1c5ff4
TL		 603}
604
92105bb7 605static int gpio_irq_type(unsigned irq, unsigned type)
5e1c5ff4
TL		 606{
607 struct gpio_bank *bank;
92105bb7
TL		 608 unsigned gpio;
609 int retval;
a6472533 610 unsigned long flags;
92105bb7 611
5492fb1a 612 if (!cpu_class_is_omap2() && irq > IH_MPUIO_BASE)
92105bb7
TL		 613 gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
614 else
615 gpio = irq - IH_GPIO_BASE;
5e1c5ff4
TL		 616
617 if (check_gpio(gpio) < 0)
92105bb7
TL		 618 return -EINVAL;
619
e5c56ed3 620 if (type & ~IRQ_TYPE_SENSE_MASK)
6e60e79a 621 return -EINVAL;
e5c56ed3
DB		 622
623 /* OMAP1 allows only only edge triggering */
5492fb1a 624 if (!cpu_class_is_omap2()
e5c56ed3 625 && (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH)))
92105bb7
TL		 626 return -EINVAL;
627
58781016 628 bank = get_irq_chip_data(irq);
a6472533 629 spin_lock_irqsave(&bank->lock, flags);
92105bb7 630 retval = _set_gpio_triggering(bank, get_gpio_index(gpio), type);
b9772a22
DB		 631 if (retval == 0) {
632 irq_desc[irq].status &= ~IRQ_TYPE_SENSE_MASK;
633 irq_desc[irq].status |= type;
634 }
a6472533 635 spin_unlock_irqrestore(&bank->lock, flags);
672e302e
KH		 636
637 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
638 __set_irq_handler_unlocked(irq, handle_level_irq);
639 else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
640 __set_irq_handler_unlocked(irq, handle_edge_irq);
641
92105bb7 642 return retval;
5e1c5ff4
TL		 643}
644
645static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
646{
92105bb7 647 void __iomem *reg = bank->base;
5e1c5ff4
TL		 648
649 switch (bank->method) {
e5c56ed3 650#ifdef CONFIG_ARCH_OMAP1
5e1c5ff4
TL		 651 case METHOD_MPUIO:
652 /* MPUIO irqstatus is reset by reading the status register,
653 * so do nothing here */
654 return;
e5c56ed3
DB		 655#endif
656#ifdef CONFIG_ARCH_OMAP15XX
5e1c5ff4
TL		 657 case METHOD_GPIO_1510:
658 reg += OMAP1510_GPIO_INT_STATUS;
659 break;
e5c56ed3
DB		 660#endif
661#ifdef CONFIG_ARCH_OMAP16XX
5e1c5ff4
TL		 662 case METHOD_GPIO_1610:
663 reg += OMAP1610_GPIO_IRQSTATUS1;
664 break;
e5c56ed3
DB		 665#endif
666#ifdef CONFIG_ARCH_OMAP730
5e1c5ff4
TL		 667 case METHOD_GPIO_730:
668 reg += OMAP730_GPIO_INT_STATUS;
669 break;
e5c56ed3 670#endif
5492fb1a 671#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
92105bb7
TL		 672 case METHOD_GPIO_24XX:
673 reg += OMAP24XX_GPIO_IRQSTATUS1;
674 break;
e5c56ed3 675#endif
5e1c5ff4 676 default:
e5c56ed3 677 WARN_ON(1);
5e1c5ff4
TL		 678 return;
679 }
680 __raw_writel(gpio_mask, reg);
bee7930f
HD		 681
682 /* Workaround for clearing DSP GPIO interrupts to allow retention */
5492fb1a
SMK		 683#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
684 if (cpu_is_omap24xx() || cpu_is_omap34xx())
bee7930f 685 __raw_writel(gpio_mask, bank->base + OMAP24XX_GPIO_IRQSTATUS2);
5492fb1a 686#endif
5e1c5ff4
TL		 687}
688
689static inline void _clear_gpio_irqstatus(struct gpio_bank *bank, int gpio)
690{
691 _clear_gpio_irqbank(bank, 1 << get_gpio_index(gpio));
692}
693
ea6dedd7
ID		 694static u32 _get_gpio_irqbank_mask(struct gpio_bank *bank)
695{
696 void __iomem *reg = bank->base;
99c47707
ID		 697 int inv = 0;
698 u32 l;
699 u32 mask;
ea6dedd7
ID		 700
701 switch (bank->method) {
e5c56ed3 702#ifdef CONFIG_ARCH_OMAP1
ea6dedd7
ID		 703 case METHOD_MPUIO:
704 reg += OMAP_MPUIO_GPIO_MASKIT;
99c47707
ID		 705 mask = 0xffff;
706 inv = 1;
ea6dedd7 707 break;
e5c56ed3
DB		 708#endif
709#ifdef CONFIG_ARCH_OMAP15XX
ea6dedd7
ID		 710 case METHOD_GPIO_1510:
711 reg += OMAP1510_GPIO_INT_MASK;
99c47707
ID		 712 mask = 0xffff;
713 inv = 1;
ea6dedd7 714 break;
e5c56ed3
DB		 715#endif
716#ifdef CONFIG_ARCH_OMAP16XX
ea6dedd7
ID		 717 case METHOD_GPIO_1610:
718 reg += OMAP1610_GPIO_IRQENABLE1;
99c47707 719 mask = 0xffff;
ea6dedd7 720 break;
e5c56ed3
DB		 721#endif
722#ifdef CONFIG_ARCH_OMAP730
ea6dedd7
ID		 723 case METHOD_GPIO_730:
724 reg += OMAP730_GPIO_INT_MASK;
99c47707
ID		 725 mask = 0xffffffff;
726 inv = 1;
ea6dedd7 727 break;
e5c56ed3 728#endif
5492fb1a 729#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
ea6dedd7
ID		 730 case METHOD_GPIO_24XX:
731 reg += OMAP24XX_GPIO_IRQENABLE1;
99c47707 732 mask = 0xffffffff;
ea6dedd7 733 break;
e5c56ed3 734#endif
ea6dedd7 735 default:
e5c56ed3 736 WARN_ON(1);
ea6dedd7
ID		 737 return 0;
738 }
739
99c47707
ID		 740 l = __raw_readl(reg);
741 if (inv)
742 l = ~l;
743 l &= mask;
744 return l;
ea6dedd7
ID		 745}
746
5e1c5ff4
TL		 747static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask, int enable)
748{
92105bb7 749 void __iomem *reg = bank->base;
5e1c5ff4
TL		 750 u32 l;
751
752 switch (bank->method) {
e5c56ed3 753#ifdef CONFIG_ARCH_OMAP1
5e1c5ff4
TL		 754 case METHOD_MPUIO:
755 reg += OMAP_MPUIO_GPIO_MASKIT;
756 l = __raw_readl(reg);
757 if (enable)
758 l &= ~(gpio_mask);
759 else
760 l |= gpio_mask;
761 break;
e5c56ed3
DB		 762#endif
763#ifdef CONFIG_ARCH_OMAP15XX
5e1c5ff4
TL		 764 case METHOD_GPIO_1510:
765 reg += OMAP1510_GPIO_INT_MASK;
766 l = __raw_readl(reg);
767 if (enable)
768 l &= ~(gpio_mask);
769 else
770 l |= gpio_mask;
771 break;
e5c56ed3
DB		 772#endif
773#ifdef CONFIG_ARCH_OMAP16XX
5e1c5ff4
TL		 774 case METHOD_GPIO_1610:
775 if (enable)
776 reg += OMAP1610_GPIO_SET_IRQENABLE1;
777 else
778 reg += OMAP1610_GPIO_CLEAR_IRQENABLE1;
779 l = gpio_mask;
780 break;
e5c56ed3
DB		 781#endif
782#ifdef CONFIG_ARCH_OMAP730
5e1c5ff4
TL		 783 case METHOD_GPIO_730:
784 reg += OMAP730_GPIO_INT_MASK;
785 l = __raw_readl(reg);
786 if (enable)
787 l &= ~(gpio_mask);
788 else
789 l |= gpio_mask;
790 break;
e5c56ed3 791#endif
5492fb1a 792#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
92105bb7
TL		 793 case METHOD_GPIO_24XX:
794 if (enable)
795 reg += OMAP24XX_GPIO_SETIRQENABLE1;
796 else
797 reg += OMAP24XX_GPIO_CLEARIRQENABLE1;
798 l = gpio_mask;
799 break;
e5c56ed3 800#endif
5e1c5ff4 801 default:
e5c56ed3 802 WARN_ON(1);
5e1c5ff4
TL		 803 return;
804 }
805 __raw_writel(l, reg);
806}
807
808static inline void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int enable)
809{
810 _enable_gpio_irqbank(bank, 1 << get_gpio_index(gpio), enable);
811}
812
92105bb7
TL		 813/*
814 * Note that ENAWAKEUP needs to be enabled in GPIO_SYSCONFIG register.
815 * 1510 does not seem to have a wake-up register. If JTAG is connected
816 * to the target, system will wake up always on GPIO events. While
817 * system is running all registered GPIO interrupts need to have wake-up
818 * enabled. When system is suspended, only selected GPIO interrupts need
819 * to have wake-up enabled.
820 */
821static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable)
822{
a6472533
DB		 823 unsigned long flags;
824
92105bb7 825 switch (bank->method) {
3ac4fa99 826#ifdef CONFIG_ARCH_OMAP16XX
11a78b79 827 case METHOD_MPUIO:
92105bb7 828 case METHOD_GPIO_1610:
a6472533 829 spin_lock_irqsave(&bank->lock, flags);
11a78b79 830 if (enable) {
92105bb7 831 bank->suspend_wakeup |= (1 << gpio);
11a78b79
DB		 832 enable_irq_wake(bank->irq);
833 } else {
834 disable_irq_wake(bank->irq);
92105bb7 835 bank->suspend_wakeup &= ~(1 << gpio);
11a78b79 836 }
a6472533 837 spin_unlock_irqrestore(&bank->lock, flags);
92105bb7 838 return 0;
3ac4fa99 839#endif
5492fb1a 840#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
3ac4fa99 841 case METHOD_GPIO_24XX:
11a78b79
DB		 842 if (bank->non_wakeup_gpios & (1 << gpio)) {
843 printk(KERN_ERR "Unable to modify wakeup on "
844 "non-wakeup GPIO%d\n",
845 (bank - gpio_bank) * 32 + gpio);
846 return -EINVAL;
847 }
a6472533 848 spin_lock_irqsave(&bank->lock, flags);
3ac4fa99 849 if (enable) {
3ac4fa99 850 bank->suspend_wakeup |= (1 << gpio);
11a78b79
DB		 851 enable_irq_wake(bank->irq);
852 } else {
853 disable_irq_wake(bank->irq);
3ac4fa99 854 bank->suspend_wakeup &= ~(1 << gpio);
11a78b79 855 }
a6472533 856 spin_unlock_irqrestore(&bank->lock, flags);
3ac4fa99
JY		 857 return 0;
858#endif
92105bb7
TL		 859 default:
860 printk(KERN_ERR "Can't enable GPIO wakeup for method %i\n",
861 bank->method);
862 return -EINVAL;
863 }
864}
865
4196dd6b
TL		 866static void _reset_gpio(struct gpio_bank *bank, int gpio)
867{
868 _set_gpio_direction(bank, get_gpio_index(gpio), 1);
869 _set_gpio_irqenable(bank, gpio, 0);
870 _clear_gpio_irqstatus(bank, gpio);
6cab4860 871 _set_gpio_triggering(bank, get_gpio_index(gpio), IRQ_TYPE_NONE);
4196dd6b
TL		 872}
873
92105bb7
TL		 874/* Use disable_irq_wake() and enable_irq_wake() functions from drivers */
875static int gpio_wake_enable(unsigned int irq, unsigned int enable)
876{
877 unsigned int gpio = irq - IH_GPIO_BASE;
878 struct gpio_bank *bank;
879 int retval;
880
881 if (check_gpio(gpio) < 0)
882 return -ENODEV;
58781016 883 bank = get_irq_chip_data(irq);
92105bb7 884 retval = _set_gpio_wakeup(bank, get_gpio_index(gpio), enable);
92105bb7
TL		 885
886 return retval;
887}
888
5e1c5ff4
TL		 889int omap_request_gpio(int gpio)
890{
891 struct gpio_bank *bank;
a6472533 892 unsigned long flags;
52e31344 893 int status;
5e1c5ff4
TL		 894
895 if (check_gpio(gpio) < 0)
896 return -EINVAL;
897
52e31344
DB		 898 status = gpio_request(gpio, NULL);
899 if (status < 0)
900 return status;
901
5e1c5ff4 902 bank = get_gpio_bank(gpio);
a6472533 903 spin_lock_irqsave(&bank->lock, flags);
92105bb7 904
4196dd6b
TL		 905 /* Set trigger to none. You need to enable the desired trigger with
906 * request_irq() or set_irq_type().
907 */
6cab4860 908 _set_gpio_triggering(bank, get_gpio_index(gpio), IRQ_TYPE_NONE);
92105bb7 909
1a8bfa1e 910#ifdef CONFIG_ARCH_OMAP15XX
5e1c5ff4 911 if (bank->method == METHOD_GPIO_1510) {
92105bb7 912 void __iomem *reg;
5e1c5ff4 913
92105bb7 914 /* Claim the pin for MPU */
5e1c5ff4
TL		 915 reg = bank->base + OMAP1510_GPIO_PIN_CONTROL;
916 __raw_writel(__raw_readl(reg) | (1 << get_gpio_index(gpio)), reg);
917 }
918#endif
a6472533 919 spin_unlock_irqrestore(&bank->lock, flags);
5e1c5ff4
TL		 920
921 return 0;
922}
923
924void omap_free_gpio(int gpio)
925{
926 struct gpio_bank *bank;
a6472533 927 unsigned long flags;
5e1c5ff4
TL		 928
929 if (check_gpio(gpio) < 0)
930 return;
931 bank = get_gpio_bank(gpio);
a6472533 932 spin_lock_irqsave(&bank->lock, flags);
52e31344
DB		 933 if (unlikely(!gpiochip_is_requested(&bank->chip,
934 get_gpio_index(gpio)))) {
935 spin_unlock_irqrestore(&bank->lock, flags);
5e1c5ff4
TL		 936 printk(KERN_ERR "omap-gpio: GPIO %d wasn't reserved!\n", gpio);
937 dump_stack();
5e1c5ff4
TL		 938 return;
939 }
92105bb7
TL		 940#ifdef CONFIG_ARCH_OMAP16XX
941 if (bank->method == METHOD_GPIO_1610) {
942 /* Disable wake-up during idle for dynamic tick */
943 void __iomem *reg = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
944 __raw_writel(1 << get_gpio_index(gpio), reg);
945 }
946#endif
5492fb1a 947#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
92105bb7
TL		 948 if (bank->method == METHOD_GPIO_24XX) {
949 /* Disable wake-up during idle for dynamic tick */
950 void __iomem *reg = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
951 __raw_writel(1 << get_gpio_index(gpio), reg);
952 }
953#endif
4196dd6b 954 _reset_gpio(bank, gpio);
a6472533 955 spin_unlock_irqrestore(&bank->lock, flags);
52e31344 956 gpio_free(gpio);
5e1c5ff4
TL		 957}
958
959/*
960 * We need to unmask the GPIO bank interrupt as soon as possible to
961 * avoid missing GPIO interrupts for other lines in the bank.
962 * Then we need to mask-read-clear-unmask the triggered GPIO lines
963 * in the bank to avoid missing nested interrupts for a GPIO line.
964 * If we wait to unmask individual GPIO lines in the bank after the
965 * line's interrupt handler has been run, we may miss some nested
966 * interrupts.
967 */
10dd5ce2 968static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
5e1c5ff4 969{
92105bb7 970 void __iomem *isr_reg = NULL;
5e1c5ff4
TL		 971 u32 isr;
972 unsigned int gpio_irq;
973 struct gpio_bank *bank;
ea6dedd7
ID		 974 u32 retrigger = 0;
975 int unmasked = 0;
5e1c5ff4
TL		 976
977 desc->chip->ack(irq);
978
418ca1f0 979 bank = get_irq_data(irq);
e5c56ed3 980#ifdef CONFIG_ARCH_OMAP1
5e1c5ff4
TL		 981 if (bank->method == METHOD_MPUIO)
982 isr_reg = bank->base + OMAP_MPUIO_GPIO_INT;
e5c56ed3 983#endif
1a8bfa1e 984#ifdef CONFIG_ARCH_OMAP15XX
5e1c5ff4
TL		 985 if (bank->method == METHOD_GPIO_1510)
986 isr_reg = bank->base + OMAP1510_GPIO_INT_STATUS;
987#endif
988#if defined(CONFIG_ARCH_OMAP16XX)
989 if (bank->method == METHOD_GPIO_1610)
990 isr_reg = bank->base + OMAP1610_GPIO_IRQSTATUS1;
991#endif
992#ifdef CONFIG_ARCH_OMAP730
993 if (bank->method == METHOD_GPIO_730)
994 isr_reg = bank->base + OMAP730_GPIO_INT_STATUS;
995#endif
5492fb1a 996#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
92105bb7
TL		 997 if (bank->method == METHOD_GPIO_24XX)
998 isr_reg = bank->base + OMAP24XX_GPIO_IRQSTATUS1;
999#endif
92105bb7 1000 while(1) {
6e60e79a 1001 u32 isr_saved, level_mask = 0;
ea6dedd7 1002 u32 enabled;
6e60e79a 1003
ea6dedd7
ID		 1004 enabled = _get_gpio_irqbank_mask(bank);
1005 isr_saved = isr = __raw_readl(isr_reg) & enabled;
6e60e79a
TL		 1006
1007 if (cpu_is_omap15xx() && (bank->method == METHOD_MPUIO))
1008 isr &= 0x0000ffff;
1009
5492fb1a 1010 if (cpu_class_is_omap2()) {
b144ff6f 1011 level_mask = bank->level_mask & enabled;
ea6dedd7 1012 }
6e60e79a
TL		 1013
1014 /* clear edge sensitive interrupts before handler(s) are
1015 called so that we don't miss any interrupt occurred while
1016 executing them */
1017 _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 0);
1018 _clear_gpio_irqbank(bank, isr_saved & ~level_mask);
1019 _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 1);
1020
1021 /* if there is only edge sensitive GPIO pin interrupts
1022 configured, we could unmask GPIO bank interrupt immediately */
ea6dedd7
ID		 1023 if (!level_mask && !unmasked) {
1024 unmasked = 1;
6e60e79a 1025 desc->chip->unmask(irq);
ea6dedd7 1026 }
92105bb7 1027
ea6dedd7
ID		 1028 isr |= retrigger;
1029 retrigger = 0;
92105bb7
TL		 1030 if (!isr)
1031 break;
1032
1033 gpio_irq = bank->virtual_irq_start;
1034 for (; isr != 0; isr >>= 1, gpio_irq++) {
92105bb7
TL		 1035 if (!(isr & 1))
1036 continue;
29454dde 1037
d8aa0251 1038 generic_handle_irq(gpio_irq);
92105bb7 1039 }
1a8bfa1e 1040 }
ea6dedd7
ID		 1041 /* if bank has any level sensitive GPIO pin interrupt
1042 configured, we must unmask the bank interrupt only after
1043 handler(s) are executed in order to avoid spurious bank
1044 interrupt */
1045 if (!unmasked)
1046 desc->chip->unmask(irq);
1047
5e1c5ff4
TL		 1048}
1049
4196dd6b
TL		 1050static void gpio_irq_shutdown(unsigned int irq)
1051{
1052 unsigned int gpio = irq - IH_GPIO_BASE;
58781016 1053 struct gpio_bank *bank = get_irq_chip_data(irq);
4196dd6b
TL		 1054
1055 _reset_gpio(bank, gpio);
1056}
1057
5e1c5ff4
TL		 1058static void gpio_ack_irq(unsigned int irq)
1059{
1060 unsigned int gpio = irq - IH_GPIO_BASE;
58781016 1061 struct gpio_bank *bank = get_irq_chip_data(irq);
5e1c5ff4
TL		 1062
1063 _clear_gpio_irqstatus(bank, gpio);
1064}
1065
1066static void gpio_mask_irq(unsigned int irq)
1067{
1068 unsigned int gpio = irq - IH_GPIO_BASE;
58781016 1069 struct gpio_bank *bank = get_irq_chip_data(irq);
5e1c5ff4
TL		 1070
1071 _set_gpio_irqenable(bank, gpio, 0);
1072}
1073
1074static void gpio_unmask_irq(unsigned int irq)
1075{
1076 unsigned int gpio = irq - IH_GPIO_BASE;
58781016 1077 struct gpio_bank *bank = get_irq_chip_data(irq);
b144ff6f
KH		 1078 unsigned int irq_mask = 1 << get_gpio_index(gpio);
1079
1080 /* For level-triggered GPIOs, the clearing must be done after
1081 * the HW source is cleared, thus after the handler has run */
1082 if (bank->level_mask & irq_mask) {
1083 _set_gpio_irqenable(bank, gpio, 0);
1084 _clear_gpio_irqstatus(bank, gpio);
1085 }
5e1c5ff4 1086
4de8c75b 1087 _set_gpio_irqenable(bank, gpio, 1);
5e1c5ff4
TL		 1088}
1089
e5c56ed3
DB		 1090static struct irq_chip gpio_irq_chip = {
1091 .name = "GPIO",
1092 .shutdown = gpio_irq_shutdown,
1093 .ack = gpio_ack_irq,
1094 .mask = gpio_mask_irq,
1095 .unmask = gpio_unmask_irq,
1096 .set_type = gpio_irq_type,
1097 .set_wake = gpio_wake_enable,
1098};
1099
1100/*---------------------------------------------------------------------*/
1101
1102#ifdef CONFIG_ARCH_OMAP1
1103
1104/* MPUIO uses the always-on 32k clock */
1105
5e1c5ff4
TL		 1106static void mpuio_ack_irq(unsigned int irq)
1107{
1108 /* The ISR is reset automatically, so do nothing here. */
1109}
1110
1111static void mpuio_mask_irq(unsigned int irq)
1112{
1113 unsigned int gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
58781016 1114 struct gpio_bank *bank = get_irq_chip_data(irq);
5e1c5ff4
TL		 1115
1116 _set_gpio_irqenable(bank, gpio, 0);
1117}
1118
1119static void mpuio_unmask_irq(unsigned int irq)
1120{
1121 unsigned int gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
58781016 1122 struct gpio_bank *bank = get_irq_chip_data(irq);
5e1c5ff4
TL		 1123
1124 _set_gpio_irqenable(bank, gpio, 1);
1125}
1126
e5c56ed3
DB		 1127static struct irq_chip mpuio_irq_chip = {
1128 .name = "MPUIO",
1129 .ack = mpuio_ack_irq,
1130 .mask = mpuio_mask_irq,
1131 .unmask = mpuio_unmask_irq,
92105bb7 1132 .set_type = gpio_irq_type,
11a78b79
DB		 1133#ifdef CONFIG_ARCH_OMAP16XX
1134 /* REVISIT: assuming only 16xx supports MPUIO wake events */
1135 .set_wake = gpio_wake_enable,
1136#endif
5e1c5ff4
TL		 1137};
1138
e5c56ed3
DB		 1139
1140#define bank_is_mpuio(bank) ((bank)->method == METHOD_MPUIO)
1141
11a78b79
DB		 1142
1143#ifdef CONFIG_ARCH_OMAP16XX
1144
1145#include <linux/platform_device.h>
1146
1147static int omap_mpuio_suspend_late(struct platform_device *pdev, pm_message_t mesg)
1148{
1149 struct gpio_bank *bank = platform_get_drvdata(pdev);
1150 void __iomem *mask_reg = bank->base + OMAP_MPUIO_GPIO_MASKIT;
a6472533 1151 unsigned long flags;
11a78b79 1152
a6472533 1153 spin_lock_irqsave(&bank->lock, flags);
11a78b79
DB		 1154 bank->saved_wakeup = __raw_readl(mask_reg);
1155 __raw_writel(0xffff & ~bank->suspend_wakeup, mask_reg);
a6472533 1156 spin_unlock_irqrestore(&bank->lock, flags);
11a78b79
DB		 1157
1158 return 0;
1159}
1160
1161static int omap_mpuio_resume_early(struct platform_device *pdev)
1162{
1163 struct gpio_bank *bank = platform_get_drvdata(pdev);
1164 void __iomem *mask_reg = bank->base + OMAP_MPUIO_GPIO_MASKIT;
a6472533 1165 unsigned long flags;
11a78b79 1166
a6472533 1167 spin_lock_irqsave(&bank->lock, flags);
11a78b79 1168 __raw_writel(bank->saved_wakeup, mask_reg);
a6472533 1169 spin_unlock_irqrestore(&bank->lock, flags);
11a78b79
DB		 1170
1171 return 0;
1172}
1173
1174/* use platform_driver for this, now that there's no longer any
1175 * point to sys_device (other than not disturbing old code).
1176 */
1177static struct platform_driver omap_mpuio_driver = {
1178 .suspend_late = omap_mpuio_suspend_late,
1179 .resume_early = omap_mpuio_resume_early,
1180 .driver = {
1181 .name = "mpuio",
1182 },
1183};
1184
1185static struct platform_device omap_mpuio_device = {
1186 .name = "mpuio",
1187 .id = -1,
1188 .dev = {
1189 .driver = &omap_mpuio_driver.driver,
1190 }
1191 /* could list the /proc/iomem resources */
1192};
1193
1194static inline void mpuio_init(void)
1195{
fcf126d8
DB		 1196 platform_set_drvdata(&omap_mpuio_device, &gpio_bank_1610[0]);
1197
11a78b79
DB		 1198 if (platform_driver_register(&omap_mpuio_driver) == 0)
1199 (void) platform_device_register(&omap_mpuio_device);
1200}
1201
1202#else
1203static inline void mpuio_init(void) {}
1204#endif /* 16xx */
1205
e5c56ed3
DB		 1206#else
1207
1208extern struct irq_chip mpuio_irq_chip;
1209
1210#define bank_is_mpuio(bank) 0
11a78b79 1211static inline void mpuio_init(void) {}
e5c56ed3
DB		 1212
1213#endif
1214
1215/*---------------------------------------------------------------------*/
5e1c5ff4 1216
52e31344
DB		 1217/* REVISIT these are stupid implementations! replace by ones that
1218 * don't switch on METHOD_* and which mostly avoid spinlocks
1219 */
1220
1221static int gpio_input(struct gpio_chip *chip, unsigned offset)
1222{
1223 struct gpio_bank *bank;
1224 unsigned long flags;
1225
1226 bank = container_of(chip, struct gpio_bank, chip);
1227 spin_lock_irqsave(&bank->lock, flags);
1228 _set_gpio_direction(bank, offset, 1);
1229 spin_unlock_irqrestore(&bank->lock, flags);
1230 return 0;
1231}
1232
1233static int gpio_get(struct gpio_chip *chip, unsigned offset)
1234{
0b84b5ca 1235 return __omap_get_gpio_datain(chip->base + offset);
52e31344
DB		 1236}
1237
1238static int gpio_output(struct gpio_chip *chip, unsigned offset, int value)
1239{
1240 struct gpio_bank *bank;
1241 unsigned long flags;
1242
1243 bank = container_of(chip, struct gpio_bank, chip);
1244 spin_lock_irqsave(&bank->lock, flags);
1245 _set_gpio_dataout(bank, offset, value);
1246 _set_gpio_direction(bank, offset, 0);
1247 spin_unlock_irqrestore(&bank->lock, flags);
1248 return 0;
1249}
1250
1251static void gpio_set(struct gpio_chip *chip, unsigned offset, int value)
1252{
1253 struct gpio_bank *bank;
1254 unsigned long flags;
1255
1256 bank = container_of(chip, struct gpio_bank, chip);
1257 spin_lock_irqsave(&bank->lock, flags);
1258 _set_gpio_dataout(bank, offset, value);
1259 spin_unlock_irqrestore(&bank->lock, flags);
1260}
1261
a007b709
DB		 1262static int gpio_2irq(struct gpio_chip *chip, unsigned offset)
1263{
1264 struct gpio_bank *bank;
1265
1266 bank = container_of(chip, struct gpio_bank, chip);
1267 return bank->virtual_irq_start + offset;
1268}
1269
52e31344
DB		 1270/*---------------------------------------------------------------------*/
1271
1a8bfa1e 1272static int initialized;
5492fb1a 1273#if !defined(CONFIG_ARCH_OMAP3)
1a8bfa1e 1274static struct clk * gpio_ick;
5492fb1a
SMK		 1275#endif
1276
1277#if defined(CONFIG_ARCH_OMAP2)
1a8bfa1e 1278static struct clk * gpio_fck;
5492fb1a 1279#endif
5e1c5ff4 1280
5492fb1a 1281#if defined(CONFIG_ARCH_OMAP2430)
56a25641
SMK		 1282static struct clk * gpio5_ick;
1283static struct clk * gpio5_fck;
1284#endif
1285
5492fb1a 1286#if defined(CONFIG_ARCH_OMAP3)
5492fb1a
SMK		 1287static struct clk *gpio_iclks[OMAP34XX_NR_GPIOS];
1288#endif
1289
8ba55c5c
DB		 1290/* This lock class tells lockdep that GPIO irqs are in a different
1291 * category than their parents, so it won't report false recursion.
1292 */
1293static struct lock_class_key gpio_lock_class;
1294
5e1c5ff4
TL		 1295static int __init _omap_gpio_init(void)
1296{
1297 int i;
52e31344 1298 int gpio = 0;
5e1c5ff4 1299 struct gpio_bank *bank;
5492fb1a 1300 char clk_name[11];
5e1c5ff4
TL		 1301
1302 initialized = 1;
1303
5492fb1a 1304#if defined(CONFIG_ARCH_OMAP1)
6e60e79a 1305 if (cpu_is_omap15xx()) {
1a8bfa1e
TL		 1306 gpio_ick = clk_get(NULL, "arm_gpio_ck");
1307 if (IS_ERR(gpio_ick))
92105bb7
TL		 1308 printk("Could not get arm_gpio_ck\n");
1309 else
30ff720b 1310 clk_enable(gpio_ick);
1a8bfa1e 1311 }
5492fb1a
SMK		 1312#endif
1313#if defined(CONFIG_ARCH_OMAP2)
1314 if (cpu_class_is_omap2()) {
1a8bfa1e
TL		 1315 gpio_ick = clk_get(NULL, "gpios_ick");
1316 if (IS_ERR(gpio_ick))
1317 printk("Could not get gpios_ick\n");
1318 else
30ff720b 1319 clk_enable(gpio_ick);
1a8bfa1e 1320 gpio_fck = clk_get(NULL, "gpios_fck");
1630b52d 1321 if (IS_ERR(gpio_fck))
1a8bfa1e
TL		 1322 printk("Could not get gpios_fck\n");
1323 else
30ff720b 1324 clk_enable(gpio_fck);
56a25641
SMK		 1325
1326 /*
5492fb1a 1327 * On 2430 & 3430 GPIO 5 uses CORE L4 ICLK
56a25641 1328 */
5492fb1a 1329#if defined(CONFIG_ARCH_OMAP2430)
56a25641
SMK		 1330 if (cpu_is_omap2430()) {
1331 gpio5_ick = clk_get(NULL, "gpio5_ick");
1332 if (IS_ERR(gpio5_ick))
1333 printk("Could not get gpio5_ick\n");
1334 else
1335 clk_enable(gpio5_ick);
1336 gpio5_fck = clk_get(NULL, "gpio5_fck");
1337 if (IS_ERR(gpio5_fck))
1338 printk("Could not get gpio5_fck\n");
1339 else
1340 clk_enable(gpio5_fck);
1341 }
1342#endif
5492fb1a
SMK		 1343 }
1344#endif
1345
1346#if defined(CONFIG_ARCH_OMAP3)
1347 if (cpu_is_omap34xx()) {
1348 for (i = 0; i < OMAP34XX_NR_GPIOS; i++) {
1349 sprintf(clk_name, "gpio%d_ick", i + 1);
1350 gpio_iclks[i] = clk_get(NULL, clk_name);
1351 if (IS_ERR(gpio_iclks[i]))
1352 printk(KERN_ERR "Could not get %s\n", clk_name);
1353 else
1354 clk_enable(gpio_iclks[i]);
5492fb1a
SMK		 1355 }
1356 }
1357#endif
1358
92105bb7 1359
1a8bfa1e 1360#ifdef CONFIG_ARCH_OMAP15XX
6e60e79a 1361 if (cpu_is_omap15xx()) {
5e1c5ff4
TL		 1362 printk(KERN_INFO "OMAP1510 GPIO hardware\n");
1363 gpio_bank_count = 2;
1364 gpio_bank = gpio_bank_1510;
1365 }
1366#endif
1367#if defined(CONFIG_ARCH_OMAP16XX)
1368 if (cpu_is_omap16xx()) {
92105bb7 1369 u32 rev;
5e1c5ff4
TL		 1370
1371 gpio_bank_count = 5;
1372 gpio_bank = gpio_bank_1610;
7c7095aa 1373 rev = __raw_readw(gpio_bank[1].base + OMAP1610_GPIO_REVISION);
5e1c5ff4
TL		 1374 printk(KERN_INFO "OMAP GPIO hardware version %d.%d\n",
1375 (rev >> 4) & 0x0f, rev & 0x0f);
1376 }
1377#endif
1378#ifdef CONFIG_ARCH_OMAP730
1379 if (cpu_is_omap730()) {
1380 printk(KERN_INFO "OMAP730 GPIO hardware\n");
1381 gpio_bank_count = 7;
1382 gpio_bank = gpio_bank_730;
1383 }
92105bb7 1384#endif
56a25641 1385
92105bb7 1386#ifdef CONFIG_ARCH_OMAP24XX
56a25641 1387 if (cpu_is_omap242x()) {
92105bb7
TL		 1388 int rev;
1389
1390 gpio_bank_count = 4;
56a25641 1391 gpio_bank = gpio_bank_242x;
7c7095aa 1392 rev = __raw_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
56a25641
SMK		 1393 printk(KERN_INFO "OMAP242x GPIO hardware version %d.%d\n",
1394 (rev >> 4) & 0x0f, rev & 0x0f);
1395 }
1396 if (cpu_is_omap243x()) {
1397 int rev;
1398
1399 gpio_bank_count = 5;
1400 gpio_bank = gpio_bank_243x;
7c7095aa 1401 rev = __raw_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
56a25641 1402 printk(KERN_INFO "OMAP243x GPIO hardware version %d.%d\n",
92105bb7
TL		 1403 (rev >> 4) & 0x0f, rev & 0x0f);
1404 }
5492fb1a
SMK		 1405#endif
1406#ifdef CONFIG_ARCH_OMAP34XX
1407 if (cpu_is_omap34xx()) {
1408 int rev;
1409
1410 gpio_bank_count = OMAP34XX_NR_GPIOS;
1411 gpio_bank = gpio_bank_34xx;
7c7095aa 1412 rev = __raw_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
5492fb1a
SMK		 1413 printk(KERN_INFO "OMAP34xx GPIO hardware version %d.%d\n",
1414 (rev >> 4) & 0x0f, rev & 0x0f);
1415 }
5e1c5ff4
TL		 1416#endif
1417 for (i = 0; i < gpio_bank_count; i++) {
1418 int j, gpio_count = 16;
1419
1420 bank = &gpio_bank[i];
5e1c5ff4 1421 spin_lock_init(&bank->lock);
e5c56ed3 1422 if (bank_is_mpuio(bank))
7c7095aa 1423 __raw_writew(0xffff, bank->base + OMAP_MPUIO_GPIO_MASKIT);
d11ac979 1424 if (cpu_is_omap15xx() && bank->method == METHOD_GPIO_1510) {
5e1c5ff4
TL		 1425 __raw_writew(0xffff, bank->base + OMAP1510_GPIO_INT_MASK);
1426 __raw_writew(0x0000, bank->base + OMAP1510_GPIO_INT_STATUS);
1427 }
d11ac979 1428 if (cpu_is_omap16xx() && bank->method == METHOD_GPIO_1610) {
5e1c5ff4
TL		 1429 __raw_writew(0x0000, bank->base + OMAP1610_GPIO_IRQENABLE1);
1430 __raw_writew(0xffff, bank->base + OMAP1610_GPIO_IRQSTATUS1);
92105bb7 1431 __raw_writew(0x0014, bank->base + OMAP1610_GPIO_SYSCONFIG);
5e1c5ff4 1432 }
d11ac979 1433 if (cpu_is_omap730() && bank->method == METHOD_GPIO_730) {
5e1c5ff4
TL		 1434 __raw_writel(0xffffffff, bank->base + OMAP730_GPIO_INT_MASK);
1435 __raw_writel(0x00000000, bank->base + OMAP730_GPIO_INT_STATUS);
1436
1437 gpio_count = 32; /* 730 has 32-bit GPIOs */
1438 }
d11ac979 1439
5492fb1a 1440#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
92105bb7 1441 if (bank->method == METHOD_GPIO_24XX) {
3ac4fa99
JY		 1442 static const u32 non_wakeup_gpios[] = {
1443 0xe203ffc0, 0x08700040
1444 };
1445
92105bb7
TL		 1446 __raw_writel(0x00000000, bank->base + OMAP24XX_GPIO_IRQENABLE1);
1447 __raw_writel(0xffffffff, bank->base + OMAP24XX_GPIO_IRQSTATUS1);
14f1c3bf
JY		 1448 __raw_writew(0x0015, bank->base + OMAP24XX_GPIO_SYSCONFIG);
1449
1450 /* Initialize interface clock ungated, module enabled */
1451 __raw_writel(0, bank->base + OMAP24XX_GPIO_CTRL);
3ac4fa99
JY		 1452 if (i < ARRAY_SIZE(non_wakeup_gpios))
1453 bank->non_wakeup_gpios = non_wakeup_gpios[i];
92105bb7
TL		 1454 gpio_count = 32;
1455 }
5e1c5ff4 1456#endif
52e31344
DB		 1457
1458 /* REVISIT eventually switch from OMAP-specific gpio structs
1459 * over to the generic ones
1460 */
1461 bank->chip.direction_input = gpio_input;
1462 bank->chip.get = gpio_get;
1463 bank->chip.direction_output = gpio_output;
1464 bank->chip.set = gpio_set;
a007b709 1465 bank->chip.to_irq = gpio_2irq;
52e31344
DB		 1466 if (bank_is_mpuio(bank)) {
1467 bank->chip.label = "mpuio";
69114a47 1468#ifdef CONFIG_ARCH_OMAP16XX
d8f388d8
DB		 1469 bank->chip.dev = &omap_mpuio_device.dev;
1470#endif
52e31344
DB		 1471 bank->chip.base = OMAP_MPUIO(0);
1472 } else {
1473 bank->chip.label = "gpio";
1474 bank->chip.base = gpio;
1475 gpio += gpio_count;
1476 }
1477 bank->chip.ngpio = gpio_count;
1478
1479 gpiochip_add(&bank->chip);
1480
5e1c5ff4
TL		 1481 for (j = bank->virtual_irq_start;
1482 j < bank->virtual_irq_start + gpio_count; j++) {
8ba55c5c 1483 lockdep_set_class(&irq_desc[j].lock, &gpio_lock_class);
58781016 1484 set_irq_chip_data(j, bank);
e5c56ed3 1485 if (bank_is_mpuio(bank))
5e1c5ff4
TL		 1486 set_irq_chip(j, &mpuio_irq_chip);
1487 else
1488 set_irq_chip(j, &gpio_irq_chip);
10dd5ce2 1489 set_irq_handler(j, handle_simple_irq);
5e1c5ff4
TL		 1490 set_irq_flags(j, IRQF_VALID);
1491 }
1492 set_irq_chained_handler(bank->irq, gpio_irq_handler);
1493 set_irq_data(bank->irq, bank);
89db9482
JH		 1494
1495 if (cpu_is_omap34xx()) {
1496 sprintf(clk_name, "gpio%d_dbck", i + 1);
1497 bank->dbck = clk_get(NULL, clk_name);
1498 if (IS_ERR(bank->dbck))
1499 printk(KERN_ERR "Could not get %s\n", clk_name);
1500 }
5e1c5ff4
TL		 1501 }
1502
1503 /* Enable system clock for GPIO module.
1504 * The CAM_CLK_CTRL *is* really the right place. */
92105bb7 1505 if (cpu_is_omap16xx())
5e1c5ff4
TL		 1506 omap_writel(omap_readl(ULPD_CAM_CLK_CTRL) | 0x04, ULPD_CAM_CLK_CTRL);
1507
14f1c3bf
JY		 1508 /* Enable autoidle for the OCP interface */
1509 if (cpu_is_omap24xx())
1510 omap_writel(1 << 0, 0x48019010);
5492fb1a
SMK		 1511 if (cpu_is_omap34xx())
1512 omap_writel(1 << 0, 0x48306814);
d11ac979 1513
5e1c5ff4
TL		 1514 return 0;
1515}
1516
5492fb1a 1517#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
92105bb7
TL		 1518static int omap_gpio_suspend(struct sys_device *dev, pm_message_t mesg)
1519{
1520 int i;
1521
5492fb1a 1522 if (!cpu_class_is_omap2() && !cpu_is_omap16xx())
92105bb7
TL		 1523 return 0;
1524
1525 for (i = 0; i < gpio_bank_count; i++) {
1526 struct gpio_bank *bank = &gpio_bank[i];
1527 void __iomem *wake_status;
1528 void __iomem *wake_clear;
1529 void __iomem *wake_set;
a6472533 1530 unsigned long flags;
92105bb7
TL		 1531
1532 switch (bank->method) {
e5c56ed3 1533#ifdef CONFIG_ARCH_OMAP16XX
92105bb7
TL		 1534 case METHOD_GPIO_1610:
1535 wake_status = bank->base + OMAP1610_GPIO_WAKEUPENABLE;
1536 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1537 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1538 break;
e5c56ed3 1539#endif
5492fb1a 1540#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
92105bb7 1541 case METHOD_GPIO_24XX:
723fdb78 1542 wake_status = bank->base + OMAP24XX_GPIO_WAKE_EN;
92105bb7
TL		 1543 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1544 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
1545 break;
e5c56ed3 1546#endif
92105bb7
TL		 1547 default:
1548 continue;
1549 }
1550
a6472533 1551 spin_lock_irqsave(&bank->lock, flags);
92105bb7
TL		 1552 bank->saved_wakeup = __raw_readl(wake_status);
1553 __raw_writel(0xffffffff, wake_clear);
1554 __raw_writel(bank->suspend_wakeup, wake_set);
a6472533 1555 spin_unlock_irqrestore(&bank->lock, flags);
92105bb7
TL		 1556 }
1557
1558 return 0;
1559}
1560
1561static int omap_gpio_resume(struct sys_device *dev)
1562{
1563 int i;
1564
723fdb78 1565 if (!cpu_class_is_omap2() && !cpu_is_omap16xx())
92105bb7
TL		 1566 return 0;
1567
1568 for (i = 0; i < gpio_bank_count; i++) {
1569 struct gpio_bank *bank = &gpio_bank[i];
1570 void __iomem *wake_clear;
1571 void __iomem *wake_set;
a6472533 1572 unsigned long flags;
92105bb7
TL		 1573
1574 switch (bank->method) {
e5c56ed3 1575#ifdef CONFIG_ARCH_OMAP16XX
92105bb7
TL		 1576 case METHOD_GPIO_1610:
1577 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1578 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1579 break;
e5c56ed3 1580#endif
5492fb1a 1581#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
92105bb7 1582 case METHOD_GPIO_24XX:
0d9356cb
TL		 1583 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1584 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
92105bb7 1585 break;
e5c56ed3 1586#endif
92105bb7
TL		 1587 default:
1588 continue;
1589 }
1590
a6472533 1591 spin_lock_irqsave(&bank->lock, flags);
92105bb7
TL		 1592 __raw_writel(0xffffffff, wake_clear);
1593 __raw_writel(bank->saved_wakeup, wake_set);
a6472533 1594 spin_unlock_irqrestore(&bank->lock, flags);
92105bb7
TL		 1595 }
1596
1597 return 0;
1598}
1599
1600static struct sysdev_class omap_gpio_sysclass = {
af5ca3f4 1601 .name = "gpio",
92105bb7
TL		 1602 .suspend = omap_gpio_suspend,
1603 .resume = omap_gpio_resume,
1604};
1605
1606static struct sys_device omap_gpio_device = {
1607 .id = 0,
1608 .cls = &omap_gpio_sysclass,
1609};
3ac4fa99
JY		 1610
1611#endif
1612
5492fb1a 1613#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
3ac4fa99
JY		 1614
1615static int workaround_enabled;
1616
1617void omap2_gpio_prepare_for_retention(void)
1618{
1619 int i, c = 0;
1620
1621 /* Remove triggering for all non-wakeup GPIOs. Otherwise spurious
1622 * IRQs will be generated. See OMAP2420 Errata item 1.101. */
1623 for (i = 0; i < gpio_bank_count; i++) {
1624 struct gpio_bank *bank = &gpio_bank[i];
1625 u32 l1, l2;
1626
1627 if (!(bank->enabled_non_wakeup_gpios))
1628 continue;
5492fb1a 1629#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
3ac4fa99
JY		 1630 bank->saved_datain = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN);
1631 l1 = __raw_readl(bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1632 l2 = __raw_readl(bank->base + OMAP24XX_GPIO_RISINGDETECT);
5492fb1a 1633#endif
3ac4fa99
JY		 1634 bank->saved_fallingdetect = l1;
1635 bank->saved_risingdetect = l2;
1636 l1 &= ~bank->enabled_non_wakeup_gpios;
1637 l2 &= ~bank->enabled_non_wakeup_gpios;
5492fb1a 1638#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
3ac4fa99
JY		 1639 __raw_writel(l1, bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1640 __raw_writel(l2, bank->base + OMAP24XX_GPIO_RISINGDETECT);
5492fb1a 1641#endif
3ac4fa99
JY		 1642 c++;
1643 }
1644 if (!c) {
1645 workaround_enabled = 0;
1646 return;
1647 }
1648 workaround_enabled = 1;
1649}
1650
1651void omap2_gpio_resume_after_retention(void)
1652{
1653 int i;
1654
1655 if (!workaround_enabled)
1656 return;
1657 for (i = 0; i < gpio_bank_count; i++) {
1658 struct gpio_bank *bank = &gpio_bank[i];
1659 u32 l;
1660
1661 if (!(bank->enabled_non_wakeup_gpios))
1662 continue;
5492fb1a 1663#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
3ac4fa99
JY		 1664 __raw_writel(bank->saved_fallingdetect,
1665 bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1666 __raw_writel(bank->saved_risingdetect,
1667 bank->base + OMAP24XX_GPIO_RISINGDETECT);
5492fb1a 1668#endif
3ac4fa99
JY		 1669 /* Check if any of the non-wakeup interrupt GPIOs have changed
1670 * state. If so, generate an IRQ by software. This is
1671 * horribly racy, but it's the best we can do to work around
1672 * this silicon bug. */
5492fb1a 1673#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
3ac4fa99 1674 l = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN);
5492fb1a 1675#endif
3ac4fa99
JY		 1676 l ^= bank->saved_datain;
1677 l &= bank->non_wakeup_gpios;
1678 if (l) {
1679 u32 old0, old1;
5492fb1a 1680#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
3ac4fa99
JY		 1681 old0 = __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0);
1682 old1 = __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
1683 __raw_writel(old0 | l, bank->base + OMAP24XX_GPIO_LEVELDETECT0);
1684 __raw_writel(old1 | l, bank->base + OMAP24XX_GPIO_LEVELDETECT1);
1685 __raw_writel(old0, bank->base + OMAP24XX_GPIO_LEVELDETECT0);
1686 __raw_writel(old1, bank->base + OMAP24XX_GPIO_LEVELDETECT1);
5492fb1a 1687#endif
3ac4fa99
JY		 1688 }
1689 }
1690
1691}
1692
92105bb7
TL		 1693#endif
1694
5e1c5ff4
TL		 1695/*
1696 * This may get called early from board specific init
1a8bfa1e 1697 * for boards that have interrupts routed via FPGA.
5e1c5ff4 1698 */
277d58ef 1699int __init omap_gpio_init(void)
5e1c5ff4
TL		 1700{
1701 if (!initialized)
1702 return _omap_gpio_init();
1703 else
1704 return 0;
1705}
1706
92105bb7
TL		 1707static int __init omap_gpio_sysinit(void)
1708{
1709 int ret = 0;
1710
1711 if (!initialized)
1712 ret = _omap_gpio_init();
1713
11a78b79
DB		 1714 mpuio_init();
1715
5492fb1a
SMK		 1716#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1717 if (cpu_is_omap16xx() || cpu_class_is_omap2()) {
92105bb7
TL		 1718 if (ret == 0) {
1719 ret = sysdev_class_register(&omap_gpio_sysclass);
1720 if (ret == 0)
1721 ret = sysdev_register(&omap_gpio_device);
1722 }
1723 }
1724#endif
1725
1726 return ret;
1727}
1728
5e1c5ff4
TL		 1729EXPORT_SYMBOL(omap_request_gpio);
1730EXPORT_SYMBOL(omap_free_gpio);
5e1c5ff4 1731
92105bb7 1732arch_initcall(omap_gpio_sysinit);
b9772a22
DB		 1733
1734
1735#ifdef CONFIG_DEBUG_FS
1736
1737#include <linux/debugfs.h>
1738#include <linux/seq_file.h>
1739
1740static int gpio_is_input(struct gpio_bank *bank, int mask)
1741{
1742 void __iomem *reg = bank->base;
1743
1744 switch (bank->method) {
1745 case METHOD_MPUIO:
1746 reg += OMAP_MPUIO_IO_CNTL;
1747 break;
1748 case METHOD_GPIO_1510:
1749 reg += OMAP1510_GPIO_DIR_CONTROL;
1750 break;
1751 case METHOD_GPIO_1610:
1752 reg += OMAP1610_GPIO_DIRECTION;
1753 break;
1754 case METHOD_GPIO_730:
1755 reg += OMAP730_GPIO_DIR_CONTROL;
1756 break;
1757 case METHOD_GPIO_24XX:
1758 reg += OMAP24XX_GPIO_OE;
1759 break;
1760 }
1761 return __raw_readl(reg) & mask;
1762}
1763
1764
1765static int dbg_gpio_show(struct seq_file *s, void *unused)
1766{
1767 unsigned i, j, gpio;
1768
1769 for (i = 0, gpio = 0; i < gpio_bank_count; i++) {
1770 struct gpio_bank *bank = gpio_bank + i;
1771 unsigned bankwidth = 16;
1772 u32 mask = 1;
1773
e5c56ed3 1774 if (bank_is_mpuio(bank))
b9772a22 1775 gpio = OMAP_MPUIO(0);
5492fb1a 1776 else if (cpu_class_is_omap2() || cpu_is_omap730())
b9772a22
DB		 1777 bankwidth = 32;
1778
1779 for (j = 0; j < bankwidth; j++, gpio++, mask <<= 1) {
1780 unsigned irq, value, is_in, irqstat;
52e31344 1781 const char *label;
b9772a22 1782
52e31344
DB		 1783 label = gpiochip_is_requested(&bank->chip, j);
1784 if (!label)
b9772a22
DB		 1785 continue;
1786
1787 irq = bank->virtual_irq_start + j;
0b84b5ca 1788 value = gpio_get_value(gpio);
b9772a22
DB		 1789 is_in = gpio_is_input(bank, mask);
1790
e5c56ed3 1791 if (bank_is_mpuio(bank))
52e31344 1792 seq_printf(s, "MPUIO %2d ", j);
b9772a22 1793 else
52e31344 1794 seq_printf(s, "GPIO %3d ", gpio);
21c867f1 1795 seq_printf(s, "(%-20.20s): %s %s",
52e31344 1796 label,
b9772a22
DB		 1797 is_in ? "in " : "out",
1798 value ? "hi" : "lo");
1799
52e31344
DB		 1800/* FIXME for at least omap2, show pullup/pulldown state */
1801
b9772a22
DB		 1802 irqstat = irq_desc[irq].status;
1803 if (is_in && ((bank->suspend_wakeup & mask)
1804 || irqstat & IRQ_TYPE_SENSE_MASK)) {
1805 char *trigger = NULL;
1806
1807 switch (irqstat & IRQ_TYPE_SENSE_MASK) {
1808 case IRQ_TYPE_EDGE_FALLING:
1809 trigger = "falling";
1810 break;
1811 case IRQ_TYPE_EDGE_RISING:
1812 trigger = "rising";
1813 break;
1814 case IRQ_TYPE_EDGE_BOTH:
1815 trigger = "bothedge";
1816 break;
1817 case IRQ_TYPE_LEVEL_LOW:
1818 trigger = "low";
1819 break;
1820 case IRQ_TYPE_LEVEL_HIGH:
1821 trigger = "high";
1822 break;
1823 case IRQ_TYPE_NONE:
52e31344 1824 trigger = "(?)";
b9772a22
DB		 1825 break;
1826 }
52e31344 1827 seq_printf(s, ", irq-%d %-8s%s",
b9772a22
DB		 1828 irq, trigger,
1829 (bank->suspend_wakeup & mask)
1830 ? " wakeup" : "");
1831 }
1832 seq_printf(s, "\n");
1833 }
1834
e5c56ed3 1835 if (bank_is_mpuio(bank)) {
b9772a22
DB		 1836 seq_printf(s, "\n");
1837 gpio = 0;
1838 }
1839 }
1840 return 0;
1841}
1842
1843static int dbg_gpio_open(struct inode *inode, struct file *file)
1844{
e5c56ed3 1845 return single_open(file, dbg_gpio_show, &inode->i_private);
b9772a22
DB		 1846}
1847
1848static const struct file_operations debug_fops = {
1849 .open = dbg_gpio_open,
1850 .read = seq_read,
1851 .llseek = seq_lseek,
1852 .release = single_release,
1853};
1854
1855static int __init omap_gpio_debuginit(void)
1856{
e5c56ed3
DB		 1857 (void) debugfs_create_file("omap_gpio", S_IRUGO,
1858 NULL, NULL, &debug_fops);
b9772a22
DB		 1859 return 0;
1860}
1861late_initcall(omap_gpio_debuginit);
1862#endif
Linux kernel - Deliverables
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