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ARM / OMAP: Use struct syscore_ops for "core" power management
[deliverable/linux.git] / arch / arm / plat-omap / gpio.c
CommitLineData
5e1c5ff4
TL		 1/*
2 * linux/arch/arm/plat-omap/gpio.c
3 *
4 * Support functions for OMAP GPIO
5 *
92105bb7 6 * Copyright (C) 2003-2005 Nokia Corporation
96de0e25 7 * Written by Juha Yrjölä <juha.yrjola@nokia.com>
5e1c5ff4 8 *
44169075
SS		 9 * Copyright (C) 2009 Texas Instruments
10 * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
11 *
5e1c5ff4
TL		 12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License version 2 as
14 * published by the Free Software Foundation.
15 */
16
5e1c5ff4
TL		 17#include <linux/init.h>
18#include <linux/module.h>
5e1c5ff4 19#include <linux/interrupt.h>
3c437ffd 20#include <linux/syscore_ops.h>
92105bb7 21#include <linux/err.h>
f8ce2547 22#include <linux/clk.h>
fced80c7 23#include <linux/io.h>
77640aab
VC		 24#include <linux/slab.h>
25#include <linux/pm_runtime.h>
5e1c5ff4 26
a09e64fb 27#include <mach/hardware.h>
5e1c5ff4 28#include <asm/irq.h>
a09e64fb
RK		 29#include <mach/irqs.h>
30#include <mach/gpio.h>
5e1c5ff4
TL		 31#include <asm/mach/irq.h>
32
5e1c5ff4
TL		 33/*
34 * OMAP1510 GPIO registers
35 */
5e1c5ff4
TL		 36#define OMAP1510_GPIO_DATA_INPUT 0x00
37#define OMAP1510_GPIO_DATA_OUTPUT 0x04
38#define OMAP1510_GPIO_DIR_CONTROL 0x08
39#define OMAP1510_GPIO_INT_CONTROL 0x0c
40#define OMAP1510_GPIO_INT_MASK 0x10
41#define OMAP1510_GPIO_INT_STATUS 0x14
42#define OMAP1510_GPIO_PIN_CONTROL 0x18
43
44#define OMAP1510_IH_GPIO_BASE 64
45
46/*
47 * OMAP1610 specific GPIO registers
48 */
5e1c5ff4
TL		 49#define OMAP1610_GPIO_REVISION 0x0000
50#define OMAP1610_GPIO_SYSCONFIG 0x0010
51#define OMAP1610_GPIO_SYSSTATUS 0x0014
52#define OMAP1610_GPIO_IRQSTATUS1 0x0018
53#define OMAP1610_GPIO_IRQENABLE1 0x001c
92105bb7 54#define OMAP1610_GPIO_WAKEUPENABLE 0x0028
5e1c5ff4
TL		 55#define OMAP1610_GPIO_DATAIN 0x002c
56#define OMAP1610_GPIO_DATAOUT 0x0030
57#define OMAP1610_GPIO_DIRECTION 0x0034
58#define OMAP1610_GPIO_EDGE_CTRL1 0x0038
59#define OMAP1610_GPIO_EDGE_CTRL2 0x003c
60#define OMAP1610_GPIO_CLEAR_IRQENABLE1 0x009c
92105bb7 61#define OMAP1610_GPIO_CLEAR_WAKEUPENA 0x00a8
5e1c5ff4
TL		 62#define OMAP1610_GPIO_CLEAR_DATAOUT 0x00b0
63#define OMAP1610_GPIO_SET_IRQENABLE1 0x00dc
92105bb7 64#define OMAP1610_GPIO_SET_WAKEUPENA 0x00e8
5e1c5ff4
TL		 65#define OMAP1610_GPIO_SET_DATAOUT 0x00f0
66
67/*
7c006926 68 * OMAP7XX specific GPIO registers
5e1c5ff4 69 */
7c006926
AB		 70#define OMAP7XX_GPIO_DATA_INPUT 0x00
71#define OMAP7XX_GPIO_DATA_OUTPUT 0x04
72#define OMAP7XX_GPIO_DIR_CONTROL 0x08
73#define OMAP7XX_GPIO_INT_CONTROL 0x0c
74#define OMAP7XX_GPIO_INT_MASK 0x10
75#define OMAP7XX_GPIO_INT_STATUS 0x14
5e1c5ff4 76
92105bb7 77/*
77640aab 78 * omap2+ specific GPIO registers
92105bb7 79 */
92105bb7 80#define OMAP24XX_GPIO_REVISION 0x0000
92105bb7 81#define OMAP24XX_GPIO_IRQSTATUS1 0x0018
bee7930f
HD		 82#define OMAP24XX_GPIO_IRQSTATUS2 0x0028
83#define OMAP24XX_GPIO_IRQENABLE2 0x002c
92105bb7 84#define OMAP24XX_GPIO_IRQENABLE1 0x001c
723fdb78 85#define OMAP24XX_GPIO_WAKE_EN 0x0020
92105bb7
TL		 86#define OMAP24XX_GPIO_CTRL 0x0030
87#define OMAP24XX_GPIO_OE 0x0034
88#define OMAP24XX_GPIO_DATAIN 0x0038
89#define OMAP24XX_GPIO_DATAOUT 0x003c
90#define OMAP24XX_GPIO_LEVELDETECT0 0x0040
91#define OMAP24XX_GPIO_LEVELDETECT1 0x0044
92#define OMAP24XX_GPIO_RISINGDETECT 0x0048
93#define OMAP24XX_GPIO_FALLINGDETECT 0x004c
5eb3bb9c
KH		 94#define OMAP24XX_GPIO_DEBOUNCE_EN 0x0050
95#define OMAP24XX_GPIO_DEBOUNCE_VAL 0x0054
92105bb7
TL		 96#define OMAP24XX_GPIO_CLEARIRQENABLE1 0x0060
97#define OMAP24XX_GPIO_SETIRQENABLE1 0x0064
98#define OMAP24XX_GPIO_CLEARWKUENA 0x0080
99#define OMAP24XX_GPIO_SETWKUENA 0x0084
100#define OMAP24XX_GPIO_CLEARDATAOUT 0x0090
101#define OMAP24XX_GPIO_SETDATAOUT 0x0094
102
78a1a6d3 103#define OMAP4_GPIO_REVISION 0x0000
78a1a6d3
SR		 104#define OMAP4_GPIO_EOI 0x0020
105#define OMAP4_GPIO_IRQSTATUSRAW0 0x0024
106#define OMAP4_GPIO_IRQSTATUSRAW1 0x0028
107#define OMAP4_GPIO_IRQSTATUS0 0x002c
108#define OMAP4_GPIO_IRQSTATUS1 0x0030
109#define OMAP4_GPIO_IRQSTATUSSET0 0x0034
110#define OMAP4_GPIO_IRQSTATUSSET1 0x0038
111#define OMAP4_GPIO_IRQSTATUSCLR0 0x003c
112#define OMAP4_GPIO_IRQSTATUSCLR1 0x0040
113#define OMAP4_GPIO_IRQWAKEN0 0x0044
114#define OMAP4_GPIO_IRQWAKEN1 0x0048
9f096868
C		 115#define OMAP4_GPIO_IRQENABLE1 0x011c
116#define OMAP4_GPIO_WAKE_EN 0x0120
117#define OMAP4_GPIO_IRQSTATUS2 0x0128
118#define OMAP4_GPIO_IRQENABLE2 0x012c
78a1a6d3
SR		 119#define OMAP4_GPIO_CTRL 0x0130
120#define OMAP4_GPIO_OE 0x0134
121#define OMAP4_GPIO_DATAIN 0x0138
122#define OMAP4_GPIO_DATAOUT 0x013c
123#define OMAP4_GPIO_LEVELDETECT0 0x0140
124#define OMAP4_GPIO_LEVELDETECT1 0x0144
125#define OMAP4_GPIO_RISINGDETECT 0x0148
126#define OMAP4_GPIO_FALLINGDETECT 0x014c
127#define OMAP4_GPIO_DEBOUNCENABLE 0x0150
128#define OMAP4_GPIO_DEBOUNCINGTIME 0x0154
9f096868
C		 129#define OMAP4_GPIO_CLEARIRQENABLE1 0x0160
130#define OMAP4_GPIO_SETIRQENABLE1 0x0164
131#define OMAP4_GPIO_CLEARWKUENA 0x0180
132#define OMAP4_GPIO_SETWKUENA 0x0184
78a1a6d3
SR		 133#define OMAP4_GPIO_CLEARDATAOUT 0x0190
134#define OMAP4_GPIO_SETDATAOUT 0x0194
5492fb1a 135
5e1c5ff4 136struct gpio_bank {
9f7065da 137 unsigned long pbase;
92105bb7 138 void __iomem *base;
5e1c5ff4
TL		 139 u16 irq;
140 u16 virtual_irq_start;
92105bb7 141 int method;
140455fa 142#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS)
92105bb7
TL		 143 u32 suspend_wakeup;
144 u32 saved_wakeup;
3ac4fa99 145#endif
3ac4fa99
JY		 146 u32 non_wakeup_gpios;
147 u32 enabled_non_wakeup_gpios;
148
149 u32 saved_datain;
150 u32 saved_fallingdetect;
151 u32 saved_risingdetect;
b144ff6f 152 u32 level_mask;
4318f36b 153 u32 toggle_mask;
5e1c5ff4 154 spinlock_t lock;
52e31344 155 struct gpio_chip chip;
89db9482 156 struct clk *dbck;
058af1ea 157 u32 mod_usage;
8865b9b6 158 u32 dbck_enable_mask;
77640aab
VC		 159 struct device *dev;
160 bool dbck_flag;
5de62b86 161 int stride;
5e1c5ff4
TL		 162};
163
a8eb7ca0 164#ifdef CONFIG_ARCH_OMAP3
40c670f0 165struct omap3_gpio_regs {
40c670f0
RN		 166 u32 irqenable1;
167 u32 irqenable2;
168 u32 wake_en;
169 u32 ctrl;
170 u32 oe;
171 u32 leveldetect0;
172 u32 leveldetect1;
173 u32 risingdetect;
174 u32 fallingdetect;
175 u32 dataout;
5492fb1a
SMK		 176};
177
40c670f0 178static struct omap3_gpio_regs gpio_context[OMAP34XX_NR_GPIOS];
5492fb1a
SMK		 179#endif
180
77640aab
VC		 181/*
182 * TODO: Cleanup gpio_bank usage as it is having information
183 * related to all instances of the device
184 */
185static struct gpio_bank *gpio_bank;
44169075 186
77640aab 187static int bank_width;
44169075 188
c95d10bc
VC		 189/* TODO: Analyze removing gpio_bank_count usage from driver code */
190int gpio_bank_count;
5e1c5ff4
TL		 191
192static inline struct gpio_bank *get_gpio_bank(int gpio)
193{
6e60e79a 194 if (cpu_is_omap15xx()) {
5e1c5ff4
TL		 195 if (OMAP_GPIO_IS_MPUIO(gpio))
196 return &gpio_bank[0];
197 return &gpio_bank[1];
198 }
5e1c5ff4
TL		 199 if (cpu_is_omap16xx()) {
200 if (OMAP_GPIO_IS_MPUIO(gpio))
201 return &gpio_bank[0];
202 return &gpio_bank[1 + (gpio >> 4)];
203 }
56739a69 204 if (cpu_is_omap7xx()) {
5e1c5ff4
TL		 205 if (OMAP_GPIO_IS_MPUIO(gpio))
206 return &gpio_bank[0];
207 return &gpio_bank[1 + (gpio >> 5)];
208 }
92105bb7
TL		 209 if (cpu_is_omap24xx())
210 return &gpio_bank[gpio >> 5];
44169075 211 if (cpu_is_omap34xx() || cpu_is_omap44xx())
5492fb1a 212 return &gpio_bank[gpio >> 5];
e031ab23
DB		 213 BUG();
214 return NULL;
5e1c5ff4
TL		 215}
216
217static inline int get_gpio_index(int gpio)
218{
56739a69 219 if (cpu_is_omap7xx())
5e1c5ff4 220 return gpio & 0x1f;
92105bb7
TL		 221 if (cpu_is_omap24xx())
222 return gpio & 0x1f;
44169075 223 if (cpu_is_omap34xx() || cpu_is_omap44xx())
5492fb1a 224 return gpio & 0x1f;
92105bb7 225 return gpio & 0x0f;
5e1c5ff4
TL		 226}
227
228static inline int gpio_valid(int gpio)
229{
230 if (gpio < 0)
231 return -1;
d11ac979 232 if (cpu_class_is_omap1() && OMAP_GPIO_IS_MPUIO(gpio)) {
193e68be 233 if (gpio >= OMAP_MAX_GPIO_LINES + 16)
5e1c5ff4
TL		 234 return -1;
235 return 0;
236 }
6e60e79a 237 if (cpu_is_omap15xx() && gpio < 16)
5e1c5ff4 238 return 0;
5e1c5ff4
TL		 239 if ((cpu_is_omap16xx()) && gpio < 64)
240 return 0;
56739a69 241 if (cpu_is_omap7xx() && gpio < 192)
5e1c5ff4 242 return 0;
25d6f630
TL		 243 if (cpu_is_omap2420() && gpio < 128)
244 return 0;
245 if (cpu_is_omap2430() && gpio < 160)
92105bb7 246 return 0;
44169075 247 if ((cpu_is_omap34xx() || cpu_is_omap44xx()) && gpio < 192)
5492fb1a 248 return 0;
5e1c5ff4
TL		 249 return -1;
250}
251
252static int check_gpio(int gpio)
253{
d32b20fc 254 if (unlikely(gpio_valid(gpio) < 0)) {
5e1c5ff4
TL		 255 printk(KERN_ERR "omap-gpio: invalid GPIO %d\n", gpio);
256 dump_stack();
257 return -1;
258 }
259 return 0;
260}
261
262static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input)
263{
92105bb7 264 void __iomem *reg = bank->base;
5e1c5ff4
TL		 265 u32 l;
266
267 switch (bank->method) {
e5c56ed3 268#ifdef CONFIG_ARCH_OMAP1
5e1c5ff4 269 case METHOD_MPUIO:
5de62b86 270 reg += OMAP_MPUIO_IO_CNTL / bank->stride;
5e1c5ff4 271 break;
e5c56ed3
DB		 272#endif
273#ifdef CONFIG_ARCH_OMAP15XX
5e1c5ff4
TL		 274 case METHOD_GPIO_1510:
275 reg += OMAP1510_GPIO_DIR_CONTROL;
276 break;
e5c56ed3
DB		 277#endif
278#ifdef CONFIG_ARCH_OMAP16XX
5e1c5ff4
TL		 279 case METHOD_GPIO_1610:
280 reg += OMAP1610_GPIO_DIRECTION;
281 break;
e5c56ed3 282#endif
b718aa81 283#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
7c006926
AB		 284 case METHOD_GPIO_7XX:
285 reg += OMAP7XX_GPIO_DIR_CONTROL;
56739a69
ZM		 286 break;
287#endif
a8eb7ca0 288#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
92105bb7
TL		 289 case METHOD_GPIO_24XX:
290 reg += OMAP24XX_GPIO_OE;
291 break;
78a1a6d3
SR		 292#endif
293#if defined(CONFIG_ARCH_OMAP4)
3f1686a9 294 case METHOD_GPIO_44XX:
78a1a6d3
SR		 295 reg += OMAP4_GPIO_OE;
296 break;
e5c56ed3
DB		 297#endif
298 default:
299 WARN_ON(1);
300 return;
5e1c5ff4
TL		 301 }
302 l = __raw_readl(reg);
303 if (is_input)
304 l |= 1 << gpio;
305 else
306 l &= ~(1 << gpio);
307 __raw_writel(l, reg);
308}
309
5e1c5ff4
TL		 310static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable)
311{
92105bb7 312 void __iomem *reg = bank->base;
5e1c5ff4
TL		 313 u32 l = 0;
314
315 switch (bank->method) {
e5c56ed3 316#ifdef CONFIG_ARCH_OMAP1
5e1c5ff4 317 case METHOD_MPUIO:
5de62b86 318 reg += OMAP_MPUIO_OUTPUT / bank->stride;
5e1c5ff4
TL		 319 l = __raw_readl(reg);
320 if (enable)
321 l |= 1 << gpio;
322 else
323 l &= ~(1 << gpio);
324 break;
e5c56ed3
DB		 325#endif
326#ifdef CONFIG_ARCH_OMAP15XX
5e1c5ff4
TL		 327 case METHOD_GPIO_1510:
328 reg += OMAP1510_GPIO_DATA_OUTPUT;
329 l = __raw_readl(reg);
330 if (enable)
331 l |= 1 << gpio;
332 else
333 l &= ~(1 << gpio);
334 break;
e5c56ed3
DB		 335#endif
336#ifdef CONFIG_ARCH_OMAP16XX
5e1c5ff4
TL		 337 case METHOD_GPIO_1610:
338 if (enable)
339 reg += OMAP1610_GPIO_SET_DATAOUT;
340 else
341 reg += OMAP1610_GPIO_CLEAR_DATAOUT;
342 l = 1 << gpio;
343 break;
e5c56ed3 344#endif
b718aa81 345#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
7c006926
AB		 346 case METHOD_GPIO_7XX:
347 reg += OMAP7XX_GPIO_DATA_OUTPUT;
56739a69
ZM		 348 l = __raw_readl(reg);
349 if (enable)
350 l |= 1 << gpio;
351 else
352 l &= ~(1 << gpio);
353 break;
354#endif
a8eb7ca0 355#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
92105bb7
TL		 356 case METHOD_GPIO_24XX:
357 if (enable)
358 reg += OMAP24XX_GPIO_SETDATAOUT;
359 else
360 reg += OMAP24XX_GPIO_CLEARDATAOUT;
361 l = 1 << gpio;
362 break;
78a1a6d3
SR		 363#endif
364#ifdef CONFIG_ARCH_OMAP4
3f1686a9 365 case METHOD_GPIO_44XX:
78a1a6d3
SR		 366 if (enable)
367 reg += OMAP4_GPIO_SETDATAOUT;
368 else
369 reg += OMAP4_GPIO_CLEARDATAOUT;
370 l = 1 << gpio;
371 break;
e5c56ed3 372#endif
5e1c5ff4 373 default:
e5c56ed3 374 WARN_ON(1);
5e1c5ff4
TL		 375 return;
376 }
377 __raw_writel(l, reg);
378}
379
b37c45b8 380static int _get_gpio_datain(struct gpio_bank *bank, int gpio)
5e1c5ff4 381{
92105bb7 382 void __iomem *reg;
5e1c5ff4
TL		 383
384 if (check_gpio(gpio) < 0)
e5c56ed3 385 return -EINVAL;
5e1c5ff4
TL		 386 reg = bank->base;
387 switch (bank->method) {
e5c56ed3 388#ifdef CONFIG_ARCH_OMAP1
5e1c5ff4 389 case METHOD_MPUIO:
5de62b86 390 reg += OMAP_MPUIO_INPUT_LATCH / bank->stride;
5e1c5ff4 391 break;
e5c56ed3
DB		 392#endif
393#ifdef CONFIG_ARCH_OMAP15XX
5e1c5ff4
TL		 394 case METHOD_GPIO_1510:
395 reg += OMAP1510_GPIO_DATA_INPUT;
396 break;
e5c56ed3
DB		 397#endif
398#ifdef CONFIG_ARCH_OMAP16XX
5e1c5ff4
TL		 399 case METHOD_GPIO_1610:
400 reg += OMAP1610_GPIO_DATAIN;
401 break;
e5c56ed3 402#endif
b718aa81 403#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
7c006926
AB		 404 case METHOD_GPIO_7XX:
405 reg += OMAP7XX_GPIO_DATA_INPUT;
56739a69
ZM		 406 break;
407#endif
a8eb7ca0 408#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
92105bb7
TL		 409 case METHOD_GPIO_24XX:
410 reg += OMAP24XX_GPIO_DATAIN;
411 break;
78a1a6d3
SR		 412#endif
413#ifdef CONFIG_ARCH_OMAP4
3f1686a9 414 case METHOD_GPIO_44XX:
78a1a6d3
SR		 415 reg += OMAP4_GPIO_DATAIN;
416 break;
e5c56ed3 417#endif
5e1c5ff4 418 default:
e5c56ed3 419 return -EINVAL;
5e1c5ff4 420 }
92105bb7
TL		 421 return (__raw_readl(reg)
422 & (1 << get_gpio_index(gpio))) != 0;
5e1c5ff4
TL		 423}
424
b37c45b8
RQ		 425static int _get_gpio_dataout(struct gpio_bank *bank, int gpio)
426{
427 void __iomem *reg;
428
429 if (check_gpio(gpio) < 0)
430 return -EINVAL;
431 reg = bank->base;
432
433 switch (bank->method) {
434#ifdef CONFIG_ARCH_OMAP1
435 case METHOD_MPUIO:
5de62b86 436 reg += OMAP_MPUIO_OUTPUT / bank->stride;
b37c45b8
RQ		 437 break;
438#endif
439#ifdef CONFIG_ARCH_OMAP15XX
440 case METHOD_GPIO_1510:
441 reg += OMAP1510_GPIO_DATA_OUTPUT;
442 break;
443#endif
444#ifdef CONFIG_ARCH_OMAP16XX
445 case METHOD_GPIO_1610:
446 reg += OMAP1610_GPIO_DATAOUT;
447 break;
448#endif
b718aa81 449#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
7c006926
AB		 450 case METHOD_GPIO_7XX:
451 reg += OMAP7XX_GPIO_DATA_OUTPUT;
b37c45b8
RQ		 452 break;
453#endif
9f096868 454#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
b37c45b8
RQ		 455 case METHOD_GPIO_24XX:
456 reg += OMAP24XX_GPIO_DATAOUT;
457 break;
9f096868
C		 458#endif
459#ifdef CONFIG_ARCH_OMAP4
460 case METHOD_GPIO_44XX:
461 reg += OMAP4_GPIO_DATAOUT;
462 break;
b37c45b8
RQ		 463#endif
464 default:
465 return -EINVAL;
466 }
467
468 return (__raw_readl(reg) & (1 << get_gpio_index(gpio))) != 0;
469}
470
92105bb7
TL		 471#define MOD_REG_BIT(reg, bit_mask, set) \
472do { \
473 int l = __raw_readl(base + reg); \
474 if (set) l |= bit_mask; \
475 else l &= ~bit_mask; \
476 __raw_writel(l, base + reg); \
477} while(0)
478
168ef3d9
FB		 479/**
480 * _set_gpio_debounce - low level gpio debounce time
481 * @bank: the gpio bank we're acting upon
482 * @gpio: the gpio number on this @gpio
483 * @debounce: debounce time to use
484 *
485 * OMAP's debounce time is in 31us steps so we need
486 * to convert and round up to the closest unit.
487 */
488static void _set_gpio_debounce(struct gpio_bank *bank, unsigned gpio,
489 unsigned debounce)
490{
491 void __iomem *reg = bank->base;
492 u32 val;
493 u32 l;
494
77640aab
VC		 495 if (!bank->dbck_flag)
496 return;
497
168ef3d9
FB		 498 if (debounce < 32)
499 debounce = 0x01;
500 else if (debounce > 7936)
501 debounce = 0xff;
502 else
503 debounce = (debounce / 0x1f) - 1;
504
505 l = 1 << get_gpio_index(gpio);
506
77640aab 507 if (bank->method == METHOD_GPIO_44XX)
168ef3d9
FB		 508 reg += OMAP4_GPIO_DEBOUNCINGTIME;
509 else
510 reg += OMAP24XX_GPIO_DEBOUNCE_VAL;
511
512 __raw_writel(debounce, reg);
513
514 reg = bank->base;
77640aab 515 if (bank->method == METHOD_GPIO_44XX)
168ef3d9
FB		 516 reg += OMAP4_GPIO_DEBOUNCENABLE;
517 else
518 reg += OMAP24XX_GPIO_DEBOUNCE_EN;
519
520 val = __raw_readl(reg);
521
522 if (debounce) {
523 val |= l;
77640aab 524 clk_enable(bank->dbck);
168ef3d9
FB		 525 } else {
526 val &= ~l;
77640aab 527 clk_disable(bank->dbck);
168ef3d9 528 }
f7ec0b0b 529 bank->dbck_enable_mask = val;
168ef3d9
FB		 530
531 __raw_writel(val, reg);
532}
533
140455fa 534#ifdef CONFIG_ARCH_OMAP2PLUS
5eb3bb9c
KH		 535static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio,
536 int trigger)
5e1c5ff4 537{
3ac4fa99 538 void __iomem *base = bank->base;
92105bb7 539 u32 gpio_bit = 1 << gpio;
78a1a6d3 540 u32 val;
92105bb7 541
78a1a6d3
SR		 542 if (cpu_is_omap44xx()) {
543 MOD_REG_BIT(OMAP4_GPIO_LEVELDETECT0, gpio_bit,
544 trigger & IRQ_TYPE_LEVEL_LOW);
545 MOD_REG_BIT(OMAP4_GPIO_LEVELDETECT1, gpio_bit,
546 trigger & IRQ_TYPE_LEVEL_HIGH);
547 MOD_REG_BIT(OMAP4_GPIO_RISINGDETECT, gpio_bit,
548 trigger & IRQ_TYPE_EDGE_RISING);
549 MOD_REG_BIT(OMAP4_GPIO_FALLINGDETECT, gpio_bit,
550 trigger & IRQ_TYPE_EDGE_FALLING);
551 } else {
552 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT0, gpio_bit,
553 trigger & IRQ_TYPE_LEVEL_LOW);
554 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT1, gpio_bit,
555 trigger & IRQ_TYPE_LEVEL_HIGH);
556 MOD_REG_BIT(OMAP24XX_GPIO_RISINGDETECT, gpio_bit,
557 trigger & IRQ_TYPE_EDGE_RISING);
558 MOD_REG_BIT(OMAP24XX_GPIO_FALLINGDETECT, gpio_bit,
559 trigger & IRQ_TYPE_EDGE_FALLING);
560 }
3ac4fa99 561 if (likely(!(bank->non_wakeup_gpios & gpio_bit))) {
78a1a6d3
SR		 562 if (cpu_is_omap44xx()) {
563 if (trigger != 0)
564 __raw_writel(1 << gpio, bank->base+
565 OMAP4_GPIO_IRQWAKEN0);
566 else {
567 val = __raw_readl(bank->base +
568 OMAP4_GPIO_IRQWAKEN0);
569 __raw_writel(val & (~(1 << gpio)), bank->base +
570 OMAP4_GPIO_IRQWAKEN0);
571 }
572 } else {
699117a6
CW		 573 /*
574 * GPIO wakeup request can only be generated on edge
575 * transitions
576 */
577 if (trigger & IRQ_TYPE_EDGE_BOTH)
78a1a6d3 578 __raw_writel(1 << gpio, bank->base
5eb3bb9c 579 + OMAP24XX_GPIO_SETWKUENA);
78a1a6d3
SR		 580 else
581 __raw_writel(1 << gpio, bank->base
5eb3bb9c 582 + OMAP24XX_GPIO_CLEARWKUENA);
78a1a6d3 583 }
a118b5f3
TK		 584 }
585 /* This part needs to be executed always for OMAP34xx */
586 if (cpu_is_omap34xx() || (bank->non_wakeup_gpios & gpio_bit)) {
699117a6
CW		 587 /*
588 * Log the edge gpio and manually trigger the IRQ
589 * after resume if the input level changes
590 * to avoid irq lost during PER RET/OFF mode
591 * Applies for omap2 non-wakeup gpio and all omap3 gpios
592 */
593 if (trigger & IRQ_TYPE_EDGE_BOTH)
3ac4fa99
JY		 594 bank->enabled_non_wakeup_gpios |= gpio_bit;
595 else
596 bank->enabled_non_wakeup_gpios &= ~gpio_bit;
597 }
5eb3bb9c 598
78a1a6d3
SR		 599 if (cpu_is_omap44xx()) {
600 bank->level_mask =
601 __raw_readl(bank->base + OMAP4_GPIO_LEVELDETECT0) |
602 __raw_readl(bank->base + OMAP4_GPIO_LEVELDETECT1);
603 } else {
604 bank->level_mask =
605 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0) |
606 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
607 }
92105bb7 608}
3ac4fa99 609#endif
92105bb7 610
9198bcd3 611#ifdef CONFIG_ARCH_OMAP1
4318f36b
CM		 612/*
613 * This only applies to chips that can't do both rising and falling edge
614 * detection at once. For all other chips, this function is a noop.
615 */
616static void _toggle_gpio_edge_triggering(struct gpio_bank *bank, int gpio)
617{
618 void __iomem *reg = bank->base;
619 u32 l = 0;
620
621 switch (bank->method) {
4318f36b 622 case METHOD_MPUIO:
5de62b86 623 reg += OMAP_MPUIO_GPIO_INT_EDGE / bank->stride;
4318f36b 624 break;
4318f36b
CM		 625#ifdef CONFIG_ARCH_OMAP15XX
626 case METHOD_GPIO_1510:
627 reg += OMAP1510_GPIO_INT_CONTROL;
628 break;
629#endif
630#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
631 case METHOD_GPIO_7XX:
632 reg += OMAP7XX_GPIO_INT_CONTROL;
633 break;
634#endif
635 default:
636 return;
637 }
638
639 l = __raw_readl(reg);
640 if ((l >> gpio) & 1)
641 l &= ~(1 << gpio);
642 else
643 l |= 1 << gpio;
644
645 __raw_writel(l, reg);
646}
9198bcd3 647#endif
4318f36b 648
92105bb7
TL		 649static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
650{
651 void __iomem *reg = bank->base;
652 u32 l = 0;
5e1c5ff4
TL		 653
654 switch (bank->method) {
e5c56ed3 655#ifdef CONFIG_ARCH_OMAP1
5e1c5ff4 656 case METHOD_MPUIO:
5de62b86 657 reg += OMAP_MPUIO_GPIO_INT_EDGE / bank->stride;
5e1c5ff4 658 l = __raw_readl(reg);
29501577 659 if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
4318f36b 660 bank->toggle_mask |= 1 << gpio;
6cab4860 661 if (trigger & IRQ_TYPE_EDGE_RISING)
5e1c5ff4 662 l |= 1 << gpio;
6cab4860 663 else if (trigger & IRQ_TYPE_EDGE_FALLING)
5e1c5ff4 664 l &= ~(1 << gpio);
92105bb7
TL		 665 else
666 goto bad;
5e1c5ff4 667 break;
e5c56ed3
DB		 668#endif
669#ifdef CONFIG_ARCH_OMAP15XX
5e1c5ff4
TL		 670 case METHOD_GPIO_1510:
671 reg += OMAP1510_GPIO_INT_CONTROL;
672 l = __raw_readl(reg);
29501577 673 if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
4318f36b 674 bank->toggle_mask |= 1 << gpio;
6cab4860 675 if (trigger & IRQ_TYPE_EDGE_RISING)
5e1c5ff4 676 l |= 1 << gpio;
6cab4860 677 else if (trigger & IRQ_TYPE_EDGE_FALLING)
5e1c5ff4 678 l &= ~(1 << gpio);
92105bb7
TL		 679 else
680 goto bad;
5e1c5ff4 681 break;
e5c56ed3 682#endif
3ac4fa99 683#ifdef CONFIG_ARCH_OMAP16XX
5e1c5ff4 684 case METHOD_GPIO_1610:
5e1c5ff4
TL		 685 if (gpio & 0x08)
686 reg += OMAP1610_GPIO_EDGE_CTRL2;
687 else
688 reg += OMAP1610_GPIO_EDGE_CTRL1;
689 gpio &= 0x07;
690 l = __raw_readl(reg);
691 l &= ~(3 << (gpio << 1));
6cab4860 692 if (trigger & IRQ_TYPE_EDGE_RISING)
6e60e79a 693 l |= 2 << (gpio << 1);
6cab4860 694 if (trigger & IRQ_TYPE_EDGE_FALLING)
6e60e79a 695 l |= 1 << (gpio << 1);
3ac4fa99
JY		 696 if (trigger)
697 /* Enable wake-up during idle for dynamic tick */
698 __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_SET_WAKEUPENA);
699 else
700 __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA);
5e1c5ff4 701 break;
3ac4fa99 702#endif
b718aa81 703#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
7c006926
AB		 704 case METHOD_GPIO_7XX:
705 reg += OMAP7XX_GPIO_INT_CONTROL;
56739a69 706 l = __raw_readl(reg);
29501577 707 if ((trigger & IRQ_TYPE_SENSE_MASK) == IRQ_TYPE_EDGE_BOTH)
4318f36b 708 bank->toggle_mask |= 1 << gpio;
56739a69
ZM		 709 if (trigger & IRQ_TYPE_EDGE_RISING)
710 l |= 1 << gpio;
711 else if (trigger & IRQ_TYPE_EDGE_FALLING)
712 l &= ~(1 << gpio);
713 else
714 goto bad;
715 break;
716#endif
140455fa 717#ifdef CONFIG_ARCH_OMAP2PLUS
92105bb7 718 case METHOD_GPIO_24XX:
3f1686a9 719 case METHOD_GPIO_44XX:
3ac4fa99 720 set_24xx_gpio_triggering(bank, gpio, trigger);
f7c5cc45 721 return 0;
3ac4fa99 722#endif
5e1c5ff4 723 default:
92105bb7 724 goto bad;
5e1c5ff4 725 }
92105bb7
TL		 726 __raw_writel(l, reg);
727 return 0;
728bad:
729 return -EINVAL;
5e1c5ff4
TL		 730}
731
e9191028 732static int gpio_irq_type(struct irq_data *d, unsigned type)
5e1c5ff4
TL		 733{
734 struct gpio_bank *bank;
92105bb7
TL		 735 unsigned gpio;
736 int retval;
a6472533 737 unsigned long flags;
92105bb7 738
e9191028
LB		 739 if (!cpu_class_is_omap2() && d->irq > IH_MPUIO_BASE)
740 gpio = OMAP_MPUIO(d->irq - IH_MPUIO_BASE);
92105bb7 741 else
e9191028 742 gpio = d->irq - IH_GPIO_BASE;
5e1c5ff4
TL		 743
744 if (check_gpio(gpio) < 0)
92105bb7
TL		 745 return -EINVAL;
746
e5c56ed3 747 if (type & ~IRQ_TYPE_SENSE_MASK)
6e60e79a 748 return -EINVAL;
e5c56ed3
DB		 749
750 /* OMAP1 allows only only edge triggering */
5492fb1a 751 if (!cpu_class_is_omap2()
e5c56ed3 752 && (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH)))
92105bb7
TL		 753 return -EINVAL;
754
e9191028 755 bank = irq_data_get_irq_chip_data(d);
a6472533 756 spin_lock_irqsave(&bank->lock, flags);
92105bb7 757 retval = _set_gpio_triggering(bank, get_gpio_index(gpio), type);
a6472533 758 spin_unlock_irqrestore(&bank->lock, flags);
672e302e
KH		 759
760 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
6845664a 761 __irq_set_handler_locked(d->irq, handle_level_irq);
672e302e 762 else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
6845664a 763 __irq_set_handler_locked(d->irq, handle_edge_irq);
672e302e 764
92105bb7 765 return retval;
5e1c5ff4
TL		 766}
767
768static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
769{
92105bb7 770 void __iomem *reg = bank->base;
5e1c5ff4
TL		 771
772 switch (bank->method) {
e5c56ed3 773#ifdef CONFIG_ARCH_OMAP1
5e1c5ff4
TL		 774 case METHOD_MPUIO:
775 /* MPUIO irqstatus is reset by reading the status register,
776 * so do nothing here */
777 return;
e5c56ed3
DB		 778#endif
779#ifdef CONFIG_ARCH_OMAP15XX
5e1c5ff4
TL		 780 case METHOD_GPIO_1510:
781 reg += OMAP1510_GPIO_INT_STATUS;
782 break;
e5c56ed3
DB		 783#endif
784#ifdef CONFIG_ARCH_OMAP16XX
5e1c5ff4
TL		 785 case METHOD_GPIO_1610:
786 reg += OMAP1610_GPIO_IRQSTATUS1;
787 break;
e5c56ed3 788#endif
b718aa81 789#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
7c006926
AB		 790 case METHOD_GPIO_7XX:
791 reg += OMAP7XX_GPIO_INT_STATUS;
56739a69
ZM		 792 break;
793#endif
a8eb7ca0 794#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
92105bb7
TL		 795 case METHOD_GPIO_24XX:
796 reg += OMAP24XX_GPIO_IRQSTATUS1;
797 break;
78a1a6d3
SR		 798#endif
799#if defined(CONFIG_ARCH_OMAP4)
3f1686a9 800 case METHOD_GPIO_44XX:
78a1a6d3
SR		 801 reg += OMAP4_GPIO_IRQSTATUS0;
802 break;
e5c56ed3 803#endif
5e1c5ff4 804 default:
e5c56ed3 805 WARN_ON(1);
5e1c5ff4
TL		 806 return;
807 }
808 __raw_writel(gpio_mask, reg);
bee7930f
HD		 809
810 /* Workaround for clearing DSP GPIO interrupts to allow retention */
3f1686a9
TL		 811 if (cpu_is_omap24xx() || cpu_is_omap34xx())
812 reg = bank->base + OMAP24XX_GPIO_IRQSTATUS2;
813 else if (cpu_is_omap44xx())
814 reg = bank->base + OMAP4_GPIO_IRQSTATUS1;
815
78a1a6d3 816 if (cpu_is_omap24xx() || cpu_is_omap34xx() || cpu_is_omap44xx()) {
bedfd154
RQ		 817 __raw_writel(gpio_mask, reg);
818
819 /* Flush posted write for the irq status to avoid spurious interrupts */
820 __raw_readl(reg);
78a1a6d3 821 }
5e1c5ff4
TL		 822}
823
824static inline void _clear_gpio_irqstatus(struct gpio_bank *bank, int gpio)
825{
826 _clear_gpio_irqbank(bank, 1 << get_gpio_index(gpio));
827}
828
ea6dedd7
ID		 829static u32 _get_gpio_irqbank_mask(struct gpio_bank *bank)
830{
831 void __iomem *reg = bank->base;
99c47707
ID		 832 int inv = 0;
833 u32 l;
834 u32 mask;
ea6dedd7
ID		 835
836 switch (bank->method) {
e5c56ed3 837#ifdef CONFIG_ARCH_OMAP1
ea6dedd7 838 case METHOD_MPUIO:
5de62b86 839 reg += OMAP_MPUIO_GPIO_MASKIT / bank->stride;
99c47707
ID		 840 mask = 0xffff;
841 inv = 1;
ea6dedd7 842 break;
e5c56ed3
DB		 843#endif
844#ifdef CONFIG_ARCH_OMAP15XX
ea6dedd7
ID		 845 case METHOD_GPIO_1510:
846 reg += OMAP1510_GPIO_INT_MASK;
99c47707
ID		 847 mask = 0xffff;
848 inv = 1;
ea6dedd7 849 break;
e5c56ed3
DB		 850#endif
851#ifdef CONFIG_ARCH_OMAP16XX
ea6dedd7
ID		 852 case METHOD_GPIO_1610:
853 reg += OMAP1610_GPIO_IRQENABLE1;
99c47707 854 mask = 0xffff;
ea6dedd7 855 break;
e5c56ed3 856#endif
b718aa81 857#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
7c006926
AB		 858 case METHOD_GPIO_7XX:
859 reg += OMAP7XX_GPIO_INT_MASK;
56739a69
ZM		 860 mask = 0xffffffff;
861 inv = 1;
862 break;
863#endif
a8eb7ca0 864#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
ea6dedd7
ID		 865 case METHOD_GPIO_24XX:
866 reg += OMAP24XX_GPIO_IRQENABLE1;
99c47707 867 mask = 0xffffffff;
ea6dedd7 868 break;
78a1a6d3
SR		 869#endif
870#if defined(CONFIG_ARCH_OMAP4)
3f1686a9 871 case METHOD_GPIO_44XX:
78a1a6d3
SR		 872 reg += OMAP4_GPIO_IRQSTATUSSET0;
873 mask = 0xffffffff;
874 break;
e5c56ed3 875#endif
ea6dedd7 876 default:
e5c56ed3 877 WARN_ON(1);
ea6dedd7
ID		 878 return 0;
879 }
880
99c47707
ID		 881 l = __raw_readl(reg);
882 if (inv)
883 l = ~l;
884 l &= mask;
885 return l;
ea6dedd7
ID		 886}
887
5e1c5ff4
TL		 888static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask, int enable)
889{
92105bb7 890 void __iomem *reg = bank->base;
5e1c5ff4
TL		 891 u32 l;
892
893 switch (bank->method) {
e5c56ed3 894#ifdef CONFIG_ARCH_OMAP1
5e1c5ff4 895 case METHOD_MPUIO:
5de62b86 896 reg += OMAP_MPUIO_GPIO_MASKIT / bank->stride;
5e1c5ff4
TL		 897 l = __raw_readl(reg);
898 if (enable)
899 l &= ~(gpio_mask);
900 else
901 l |= gpio_mask;
902 break;
e5c56ed3
DB		 903#endif
904#ifdef CONFIG_ARCH_OMAP15XX
5e1c5ff4
TL		 905 case METHOD_GPIO_1510:
906 reg += OMAP1510_GPIO_INT_MASK;
907 l = __raw_readl(reg);
908 if (enable)
909 l &= ~(gpio_mask);
910 else
911 l |= gpio_mask;
912 break;
e5c56ed3
DB		 913#endif
914#ifdef CONFIG_ARCH_OMAP16XX
5e1c5ff4
TL		 915 case METHOD_GPIO_1610:
916 if (enable)
917 reg += OMAP1610_GPIO_SET_IRQENABLE1;
918 else
919 reg += OMAP1610_GPIO_CLEAR_IRQENABLE1;
920 l = gpio_mask;
921 break;
e5c56ed3 922#endif
b718aa81 923#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
7c006926
AB		 924 case METHOD_GPIO_7XX:
925 reg += OMAP7XX_GPIO_INT_MASK;
56739a69
ZM		 926 l = __raw_readl(reg);
927 if (enable)
928 l &= ~(gpio_mask);
929 else
930 l |= gpio_mask;
931 break;
932#endif
a8eb7ca0 933#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
92105bb7
TL		 934 case METHOD_GPIO_24XX:
935 if (enable)
936 reg += OMAP24XX_GPIO_SETIRQENABLE1;
937 else
938 reg += OMAP24XX_GPIO_CLEARIRQENABLE1;
939 l = gpio_mask;
940 break;
78a1a6d3
SR		 941#endif
942#ifdef CONFIG_ARCH_OMAP4
3f1686a9 943 case METHOD_GPIO_44XX:
78a1a6d3
SR		 944 if (enable)
945 reg += OMAP4_GPIO_IRQSTATUSSET0;
946 else
947 reg += OMAP4_GPIO_IRQSTATUSCLR0;
948 l = gpio_mask;
949 break;
e5c56ed3 950#endif
5e1c5ff4 951 default:
e5c56ed3 952 WARN_ON(1);
5e1c5ff4
TL		 953 return;
954 }
955 __raw_writel(l, reg);
956}
957
958static inline void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int enable)
959{
960 _enable_gpio_irqbank(bank, 1 << get_gpio_index(gpio), enable);
961}
962
92105bb7
TL		 963/*
964 * Note that ENAWAKEUP needs to be enabled in GPIO_SYSCONFIG register.
965 * 1510 does not seem to have a wake-up register. If JTAG is connected
966 * to the target, system will wake up always on GPIO events. While
967 * system is running all registered GPIO interrupts need to have wake-up
968 * enabled. When system is suspended, only selected GPIO interrupts need
969 * to have wake-up enabled.
970 */
971static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable)
972{
4cc6420c 973 unsigned long uninitialized_var(flags);
a6472533 974
92105bb7 975 switch (bank->method) {
3ac4fa99 976#ifdef CONFIG_ARCH_OMAP16XX
11a78b79 977 case METHOD_MPUIO:
92105bb7 978 case METHOD_GPIO_1610:
a6472533 979 spin_lock_irqsave(&bank->lock, flags);
b3bb4f68 980 if (enable)
92105bb7 981 bank->suspend_wakeup |= (1 << gpio);
b3bb4f68 982 else
92105bb7 983 bank->suspend_wakeup &= ~(1 << gpio);
a6472533 984 spin_unlock_irqrestore(&bank->lock, flags);
92105bb7 985 return 0;
3ac4fa99 986#endif
140455fa 987#ifdef CONFIG_ARCH_OMAP2PLUS
3ac4fa99 988 case METHOD_GPIO_24XX:
3f1686a9 989 case METHOD_GPIO_44XX:
11a78b79
DB		 990 if (bank->non_wakeup_gpios & (1 << gpio)) {
991 printk(KERN_ERR "Unable to modify wakeup on "
992 "non-wakeup GPIO%d\n",
993 (bank - gpio_bank) * 32 + gpio);
994 return -EINVAL;
995 }
a6472533 996 spin_lock_irqsave(&bank->lock, flags);
b3bb4f68 997 if (enable)
3ac4fa99 998 bank->suspend_wakeup |= (1 << gpio);
b3bb4f68 999 else
3ac4fa99 1000 bank->suspend_wakeup &= ~(1 << gpio);
a6472533 1001 spin_unlock_irqrestore(&bank->lock, flags);
3ac4fa99
JY		 1002 return 0;
1003#endif
92105bb7
TL		 1004 default:
1005 printk(KERN_ERR "Can't enable GPIO wakeup for method %i\n",
1006 bank->method);
1007 return -EINVAL;
1008 }
1009}
1010
4196dd6b
TL		 1011static void _reset_gpio(struct gpio_bank *bank, int gpio)
1012{
1013 _set_gpio_direction(bank, get_gpio_index(gpio), 1);
1014 _set_gpio_irqenable(bank, gpio, 0);
1015 _clear_gpio_irqstatus(bank, gpio);
6cab4860 1016 _set_gpio_triggering(bank, get_gpio_index(gpio), IRQ_TYPE_NONE);
4196dd6b
TL		 1017}
1018
92105bb7 1019/* Use disable_irq_wake() and enable_irq_wake() functions from drivers */
e9191028 1020static int gpio_wake_enable(struct irq_data *d, unsigned int enable)
92105bb7 1021{
e9191028 1022 unsigned int gpio = d->irq - IH_GPIO_BASE;
92105bb7
TL		 1023 struct gpio_bank *bank;
1024 int retval;
1025
1026 if (check_gpio(gpio) < 0)
1027 return -ENODEV;
e9191028 1028 bank = irq_data_get_irq_chip_data(d);
92105bb7 1029 retval = _set_gpio_wakeup(bank, get_gpio_index(gpio), enable);
92105bb7
TL		 1030
1031 return retval;
1032}
1033
3ff164e1 1034static int omap_gpio_request(struct gpio_chip *chip, unsigned offset)
5e1c5ff4 1035{
3ff164e1 1036 struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
a6472533 1037 unsigned long flags;
52e31344 1038
a6472533 1039 spin_lock_irqsave(&bank->lock, flags);
92105bb7 1040
4196dd6b
TL		 1041 /* Set trigger to none. You need to enable the desired trigger with
1042 * request_irq() or set_irq_type().
1043 */
3ff164e1 1044 _set_gpio_triggering(bank, offset, IRQ_TYPE_NONE);
92105bb7 1045
1a8bfa1e 1046#ifdef CONFIG_ARCH_OMAP15XX
5e1c5ff4 1047 if (bank->method == METHOD_GPIO_1510) {
92105bb7 1048 void __iomem *reg;
5e1c5ff4 1049
92105bb7 1050 /* Claim the pin for MPU */
5e1c5ff4 1051 reg = bank->base + OMAP1510_GPIO_PIN_CONTROL;
3ff164e1 1052 __raw_writel(__raw_readl(reg) | (1 << offset), reg);
5e1c5ff4
TL		 1053 }
1054#endif
058af1ea
C		 1055 if (!cpu_class_is_omap1()) {
1056 if (!bank->mod_usage) {
9f096868 1057 void __iomem *reg = bank->base;
058af1ea 1058 u32 ctrl;
9f096868
C		 1059
1060 if (cpu_is_omap24xx() || cpu_is_omap34xx())
1061 reg += OMAP24XX_GPIO_CTRL;
1062 else if (cpu_is_omap44xx())
1063 reg += OMAP4_GPIO_CTRL;
1064 ctrl = __raw_readl(reg);
058af1ea 1065 /* Module is enabled, clocks are not gated */
9f096868
C		 1066 ctrl &= 0xFFFFFFFE;
1067 __raw_writel(ctrl, reg);
058af1ea
C		 1068 }
1069 bank->mod_usage |= 1 << offset;
1070 }
a6472533 1071 spin_unlock_irqrestore(&bank->lock, flags);
5e1c5ff4
TL		 1072
1073 return 0;
1074}
1075
3ff164e1 1076static void omap_gpio_free(struct gpio_chip *chip, unsigned offset)
5e1c5ff4 1077{
3ff164e1 1078 struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
a6472533 1079 unsigned long flags;
5e1c5ff4 1080
a6472533 1081 spin_lock_irqsave(&bank->lock, flags);
92105bb7
TL		 1082#ifdef CONFIG_ARCH_OMAP16XX
1083 if (bank->method == METHOD_GPIO_1610) {
1084 /* Disable wake-up during idle for dynamic tick */
1085 void __iomem *reg = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
3ff164e1 1086 __raw_writel(1 << offset, reg);
92105bb7
TL		 1087 }
1088#endif
9f096868
C		 1089#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
1090 if (bank->method == METHOD_GPIO_24XX) {
92105bb7
TL		 1091 /* Disable wake-up during idle for dynamic tick */
1092 void __iomem *reg = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
3ff164e1 1093 __raw_writel(1 << offset, reg);
92105bb7 1094 }
9f096868
C		 1095#endif
1096#ifdef CONFIG_ARCH_OMAP4
1097 if (bank->method == METHOD_GPIO_44XX) {
1098 /* Disable wake-up during idle for dynamic tick */
1099 void __iomem *reg = bank->base + OMAP4_GPIO_IRQWAKEN0;
1100 __raw_writel(1 << offset, reg);
1101 }
92105bb7 1102#endif
058af1ea
C		 1103 if (!cpu_class_is_omap1()) {
1104 bank->mod_usage &= ~(1 << offset);
1105 if (!bank->mod_usage) {
9f096868 1106 void __iomem *reg = bank->base;
058af1ea 1107 u32 ctrl;
9f096868
C		 1108
1109 if (cpu_is_omap24xx() || cpu_is_omap34xx())
1110 reg += OMAP24XX_GPIO_CTRL;
1111 else if (cpu_is_omap44xx())
1112 reg += OMAP4_GPIO_CTRL;
1113 ctrl = __raw_readl(reg);
058af1ea
C		 1114 /* Module is disabled, clocks are gated */
1115 ctrl |= 1;
9f096868 1116 __raw_writel(ctrl, reg);
058af1ea
C		 1117 }
1118 }
3ff164e1 1119 _reset_gpio(bank, bank->chip.base + offset);
a6472533 1120 spin_unlock_irqrestore(&bank->lock, flags);
5e1c5ff4
TL		 1121}
1122
1123/*
1124 * We need to unmask the GPIO bank interrupt as soon as possible to
1125 * avoid missing GPIO interrupts for other lines in the bank.
1126 * Then we need to mask-read-clear-unmask the triggered GPIO lines
1127 * in the bank to avoid missing nested interrupts for a GPIO line.
1128 * If we wait to unmask individual GPIO lines in the bank after the
1129 * line's interrupt handler has been run, we may miss some nested
1130 * interrupts.
1131 */
10dd5ce2 1132static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
5e1c5ff4 1133{
92105bb7 1134 void __iomem *isr_reg = NULL;
5e1c5ff4 1135 u32 isr;
4318f36b 1136 unsigned int gpio_irq, gpio_index;
5e1c5ff4 1137 struct gpio_bank *bank;
ea6dedd7
ID		 1138 u32 retrigger = 0;
1139 int unmasked = 0;
5e1c5ff4 1140
e9191028 1141 desc->irq_data.chip->irq_ack(&desc->irq_data);
5e1c5ff4 1142
6845664a 1143 bank = irq_get_handler_data(irq);
e5c56ed3 1144#ifdef CONFIG_ARCH_OMAP1
5e1c5ff4 1145 if (bank->method == METHOD_MPUIO)
5de62b86
TL		 1146 isr_reg = bank->base +
1147 OMAP_MPUIO_GPIO_INT / bank->stride;
e5c56ed3 1148#endif
1a8bfa1e 1149#ifdef CONFIG_ARCH_OMAP15XX
5e1c5ff4
TL		 1150 if (bank->method == METHOD_GPIO_1510)
1151 isr_reg = bank->base + OMAP1510_GPIO_INT_STATUS;
1152#endif
1153#if defined(CONFIG_ARCH_OMAP16XX)
1154 if (bank->method == METHOD_GPIO_1610)
1155 isr_reg = bank->base + OMAP1610_GPIO_IRQSTATUS1;
1156#endif
b718aa81 1157#if defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850)
7c006926
AB		 1158 if (bank->method == METHOD_GPIO_7XX)
1159 isr_reg = bank->base + OMAP7XX_GPIO_INT_STATUS;
56739a69 1160#endif
a8eb7ca0 1161#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
92105bb7
TL		 1162 if (bank->method == METHOD_GPIO_24XX)
1163 isr_reg = bank->base + OMAP24XX_GPIO_IRQSTATUS1;
78a1a6d3
SR		 1164#endif
1165#if defined(CONFIG_ARCH_OMAP4)
3f1686a9 1166 if (bank->method == METHOD_GPIO_44XX)
78a1a6d3 1167 isr_reg = bank->base + OMAP4_GPIO_IRQSTATUS0;
92105bb7 1168#endif
b1cc4c55
EK		 1169
1170 if (WARN_ON(!isr_reg))
1171 goto exit;
1172
92105bb7 1173 while(1) {
6e60e79a 1174 u32 isr_saved, level_mask = 0;
ea6dedd7 1175 u32 enabled;
6e60e79a 1176
ea6dedd7
ID		 1177 enabled = _get_gpio_irqbank_mask(bank);
1178 isr_saved = isr = __raw_readl(isr_reg) & enabled;
6e60e79a
TL		 1179
1180 if (cpu_is_omap15xx() && (bank->method == METHOD_MPUIO))
1181 isr &= 0x0000ffff;
1182
5492fb1a 1183 if (cpu_class_is_omap2()) {
b144ff6f 1184 level_mask = bank->level_mask & enabled;
ea6dedd7 1185 }
6e60e79a
TL		 1186
1187 /* clear edge sensitive interrupts before handler(s) are
1188 called so that we don't miss any interrupt occurred while
1189 executing them */
1190 _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 0);
1191 _clear_gpio_irqbank(bank, isr_saved & ~level_mask);
1192 _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 1);
1193
1194 /* if there is only edge sensitive GPIO pin interrupts
1195 configured, we could unmask GPIO bank interrupt immediately */
ea6dedd7
ID		 1196 if (!level_mask && !unmasked) {
1197 unmasked = 1;
e9191028 1198 desc->irq_data.chip->irq_unmask(&desc->irq_data);
ea6dedd7 1199 }
92105bb7 1200
ea6dedd7
ID		 1201 isr |= retrigger;
1202 retrigger = 0;
92105bb7
TL		 1203 if (!isr)
1204 break;
1205
1206 gpio_irq = bank->virtual_irq_start;
1207 for (; isr != 0; isr >>= 1, gpio_irq++) {
4318f36b
CM		 1208 gpio_index = get_gpio_index(irq_to_gpio(gpio_irq));
1209
92105bb7
TL		 1210 if (!(isr & 1))
1211 continue;
29454dde 1212
4318f36b
CM		 1213#ifdef CONFIG_ARCH_OMAP1
1214 /*
1215 * Some chips can't respond to both rising and falling
1216 * at the same time. If this irq was requested with
1217 * both flags, we need to flip the ICR data for the IRQ
1218 * to respond to the IRQ for the opposite direction.
1219 * This will be indicated in the bank toggle_mask.
1220 */
1221 if (bank->toggle_mask & (1 << gpio_index))
1222 _toggle_gpio_edge_triggering(bank, gpio_index);
1223#endif
1224
d8aa0251 1225 generic_handle_irq(gpio_irq);
92105bb7 1226 }
1a8bfa1e 1227 }
ea6dedd7
ID		 1228 /* if bank has any level sensitive GPIO pin interrupt
1229 configured, we must unmask the bank interrupt only after
1230 handler(s) are executed in order to avoid spurious bank
1231 interrupt */
b1cc4c55 1232exit:
ea6dedd7 1233 if (!unmasked)
e9191028 1234 desc->irq_data.chip->irq_unmask(&desc->irq_data);
5e1c5ff4
TL		 1235}
1236
e9191028 1237static void gpio_irq_shutdown(struct irq_data *d)
4196dd6b 1238{
e9191028
LB		 1239 unsigned int gpio = d->irq - IH_GPIO_BASE;
1240 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
4196dd6b
TL		 1241
1242 _reset_gpio(bank, gpio);
1243}
1244
e9191028 1245static void gpio_ack_irq(struct irq_data *d)
5e1c5ff4 1246{
e9191028
LB		 1247 unsigned int gpio = d->irq - IH_GPIO_BASE;
1248 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
5e1c5ff4
TL		 1249
1250 _clear_gpio_irqstatus(bank, gpio);
1251}
1252
e9191028 1253static void gpio_mask_irq(struct irq_data *d)
5e1c5ff4 1254{
e9191028
LB		 1255 unsigned int gpio = d->irq - IH_GPIO_BASE;
1256 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
5e1c5ff4
TL		 1257
1258 _set_gpio_irqenable(bank, gpio, 0);
55b6019a 1259 _set_gpio_triggering(bank, get_gpio_index(gpio), IRQ_TYPE_NONE);
5e1c5ff4
TL		 1260}
1261
e9191028 1262static void gpio_unmask_irq(struct irq_data *d)
5e1c5ff4 1263{
e9191028
LB		 1264 unsigned int gpio = d->irq - IH_GPIO_BASE;
1265 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
b144ff6f 1266 unsigned int irq_mask = 1 << get_gpio_index(gpio);
8c04a176 1267 u32 trigger = irqd_get_trigger_type(d);
55b6019a
KH		 1268
1269 if (trigger)
1270 _set_gpio_triggering(bank, get_gpio_index(gpio), trigger);
b144ff6f
KH		 1271
1272 /* For level-triggered GPIOs, the clearing must be done after
1273 * the HW source is cleared, thus after the handler has run */
1274 if (bank->level_mask & irq_mask) {
1275 _set_gpio_irqenable(bank, gpio, 0);
1276 _clear_gpio_irqstatus(bank, gpio);
1277 }
5e1c5ff4 1278
4de8c75b 1279 _set_gpio_irqenable(bank, gpio, 1);
5e1c5ff4
TL		 1280}
1281
e5c56ed3
DB		 1282static struct irq_chip gpio_irq_chip = {
1283 .name = "GPIO",
e9191028
LB		 1284 .irq_shutdown = gpio_irq_shutdown,
1285 .irq_ack = gpio_ack_irq,
1286 .irq_mask = gpio_mask_irq,
1287 .irq_unmask = gpio_unmask_irq,
1288 .irq_set_type = gpio_irq_type,
1289 .irq_set_wake = gpio_wake_enable,
e5c56ed3
DB		 1290};
1291
1292/*---------------------------------------------------------------------*/
1293
1294#ifdef CONFIG_ARCH_OMAP1
1295
1296/* MPUIO uses the always-on 32k clock */
1297
e9191028 1298static void mpuio_ack_irq(struct irq_data *d)
5e1c5ff4
TL		 1299{
1300 /* The ISR is reset automatically, so do nothing here. */
1301}
1302
e9191028 1303static void mpuio_mask_irq(struct irq_data *d)
5e1c5ff4 1304{
e9191028
LB		 1305 unsigned int gpio = OMAP_MPUIO(d->irq - IH_MPUIO_BASE);
1306 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
5e1c5ff4
TL		 1307
1308 _set_gpio_irqenable(bank, gpio, 0);
1309}
1310
e9191028 1311static void mpuio_unmask_irq(struct irq_data *d)
5e1c5ff4 1312{
e9191028
LB		 1313 unsigned int gpio = OMAP_MPUIO(d->irq - IH_MPUIO_BASE);
1314 struct gpio_bank *bank = irq_data_get_irq_chip_data(d);
5e1c5ff4
TL		 1315
1316 _set_gpio_irqenable(bank, gpio, 1);
1317}
1318
e5c56ed3
DB		 1319static struct irq_chip mpuio_irq_chip = {
1320 .name = "MPUIO",
e9191028
LB		 1321 .irq_ack = mpuio_ack_irq,
1322 .irq_mask = mpuio_mask_irq,
1323 .irq_unmask = mpuio_unmask_irq,
1324 .irq_set_type = gpio_irq_type,
11a78b79
DB		 1325#ifdef CONFIG_ARCH_OMAP16XX
1326 /* REVISIT: assuming only 16xx supports MPUIO wake events */
e9191028 1327 .irq_set_wake = gpio_wake_enable,
11a78b79 1328#endif
5e1c5ff4
TL		 1329};
1330
e5c56ed3
DB		 1331
1332#define bank_is_mpuio(bank) ((bank)->method == METHOD_MPUIO)
1333
11a78b79
DB		 1334
1335#ifdef CONFIG_ARCH_OMAP16XX
1336
1337#include <linux/platform_device.h>
1338
79ee031f 1339static int omap_mpuio_suspend_noirq(struct device *dev)
11a78b79 1340{
79ee031f 1341 struct platform_device *pdev = to_platform_device(dev);
11a78b79 1342 struct gpio_bank *bank = platform_get_drvdata(pdev);
5de62b86
TL		 1343 void __iomem *mask_reg = bank->base +
1344 OMAP_MPUIO_GPIO_MASKIT / bank->stride;
a6472533 1345 unsigned long flags;
11a78b79 1346
a6472533 1347 spin_lock_irqsave(&bank->lock, flags);
11a78b79
DB		 1348 bank->saved_wakeup = __raw_readl(mask_reg);
1349 __raw_writel(0xffff & ~bank->suspend_wakeup, mask_reg);
a6472533 1350 spin_unlock_irqrestore(&bank->lock, flags);
11a78b79
DB		 1351
1352 return 0;
1353}
1354
79ee031f 1355static int omap_mpuio_resume_noirq(struct device *dev)
11a78b79 1356{
79ee031f 1357 struct platform_device *pdev = to_platform_device(dev);
11a78b79 1358 struct gpio_bank *bank = platform_get_drvdata(pdev);
5de62b86
TL		 1359 void __iomem *mask_reg = bank->base +
1360 OMAP_MPUIO_GPIO_MASKIT / bank->stride;
a6472533 1361 unsigned long flags;
11a78b79 1362
a6472533 1363 spin_lock_irqsave(&bank->lock, flags);
11a78b79 1364 __raw_writel(bank->saved_wakeup, mask_reg);
a6472533 1365 spin_unlock_irqrestore(&bank->lock, flags);
11a78b79
DB		 1366
1367 return 0;
1368}
1369
47145210 1370static const struct dev_pm_ops omap_mpuio_dev_pm_ops = {
79ee031f
MD		 1371 .suspend_noirq = omap_mpuio_suspend_noirq,
1372 .resume_noirq = omap_mpuio_resume_noirq,
1373};
1374
3c437ffd 1375/* use platform_driver for this. */
11a78b79 1376static struct platform_driver omap_mpuio_driver = {
11a78b79
DB		 1377 .driver = {
1378 .name = "mpuio",
79ee031f 1379 .pm = &omap_mpuio_dev_pm_ops,
11a78b79
DB		 1380 },
1381};
1382
1383static struct platform_device omap_mpuio_device = {
1384 .name = "mpuio",
1385 .id = -1,
1386 .dev = {
1387 .driver = &omap_mpuio_driver.driver,
1388 }
1389 /* could list the /proc/iomem resources */
1390};
1391
1392static inline void mpuio_init(void)
1393{
77640aab
VC		 1394 struct gpio_bank *bank = get_gpio_bank(OMAP_MPUIO(0));
1395 platform_set_drvdata(&omap_mpuio_device, bank);
fcf126d8 1396
11a78b79
DB		 1397 if (platform_driver_register(&omap_mpuio_driver) == 0)
1398 (void) platform_device_register(&omap_mpuio_device);
1399}
1400
1401#else
1402static inline void mpuio_init(void) {}
1403#endif /* 16xx */
1404
e5c56ed3
DB		 1405#else
1406
1407extern struct irq_chip mpuio_irq_chip;
1408
1409#define bank_is_mpuio(bank) 0
11a78b79 1410static inline void mpuio_init(void) {}
e5c56ed3
DB		 1411
1412#endif
1413
1414/*---------------------------------------------------------------------*/
5e1c5ff4 1415
52e31344
DB		 1416/* REVISIT these are stupid implementations! replace by ones that
1417 * don't switch on METHOD_* and which mostly avoid spinlocks
1418 */
1419
1420static int gpio_input(struct gpio_chip *chip, unsigned offset)
1421{
1422 struct gpio_bank *bank;
1423 unsigned long flags;
1424
1425 bank = container_of(chip, struct gpio_bank, chip);
1426 spin_lock_irqsave(&bank->lock, flags);
1427 _set_gpio_direction(bank, offset, 1);
1428 spin_unlock_irqrestore(&bank->lock, flags);
1429 return 0;
1430}
1431
b37c45b8
RQ		 1432static int gpio_is_input(struct gpio_bank *bank, int mask)
1433{
1434 void __iomem *reg = bank->base;
1435
1436 switch (bank->method) {
1437 case METHOD_MPUIO:
5de62b86 1438 reg += OMAP_MPUIO_IO_CNTL / bank->stride;
b37c45b8
RQ		 1439 break;
1440 case METHOD_GPIO_1510:
1441 reg += OMAP1510_GPIO_DIR_CONTROL;
1442 break;
1443 case METHOD_GPIO_1610:
1444 reg += OMAP1610_GPIO_DIRECTION;
1445 break;
7c006926
AB		 1446 case METHOD_GPIO_7XX:
1447 reg += OMAP7XX_GPIO_DIR_CONTROL;
b37c45b8
RQ		 1448 break;
1449 case METHOD_GPIO_24XX:
1450 reg += OMAP24XX_GPIO_OE;
1451 break;
9f096868
C		 1452 case METHOD_GPIO_44XX:
1453 reg += OMAP4_GPIO_OE;
1454 break;
1455 default:
1456 WARN_ONCE(1, "gpio_is_input: incorrect OMAP GPIO method");
1457 return -EINVAL;
b37c45b8
RQ		 1458 }
1459 return __raw_readl(reg) & mask;
1460}
1461
52e31344
DB		 1462static int gpio_get(struct gpio_chip *chip, unsigned offset)
1463{
b37c45b8
RQ		 1464 struct gpio_bank *bank;
1465 void __iomem *reg;
1466 int gpio;
1467 u32 mask;
1468
1469 gpio = chip->base + offset;
1470 bank = get_gpio_bank(gpio);
1471 reg = bank->base;
1472 mask = 1 << get_gpio_index(gpio);
1473
1474 if (gpio_is_input(bank, mask))
1475 return _get_gpio_datain(bank, gpio);
1476 else
1477 return _get_gpio_dataout(bank, gpio);
52e31344
DB		 1478}
1479
1480static int gpio_output(struct gpio_chip *chip, unsigned offset, int value)
1481{
1482 struct gpio_bank *bank;
1483 unsigned long flags;
1484
1485 bank = container_of(chip, struct gpio_bank, chip);
1486 spin_lock_irqsave(&bank->lock, flags);
1487 _set_gpio_dataout(bank, offset, value);
1488 _set_gpio_direction(bank, offset, 0);
1489 spin_unlock_irqrestore(&bank->lock, flags);
1490 return 0;
1491}
1492
168ef3d9
FB		 1493static int gpio_debounce(struct gpio_chip *chip, unsigned offset,
1494 unsigned debounce)
1495{
1496 struct gpio_bank *bank;
1497 unsigned long flags;
1498
1499 bank = container_of(chip, struct gpio_bank, chip);
77640aab
VC		 1500
1501 if (!bank->dbck) {
1502 bank->dbck = clk_get(bank->dev, "dbclk");
1503 if (IS_ERR(bank->dbck))
1504 dev_err(bank->dev, "Could not get gpio dbck\n");
1505 }
1506
168ef3d9
FB		 1507 spin_lock_irqsave(&bank->lock, flags);
1508 _set_gpio_debounce(bank, offset, debounce);
1509 spin_unlock_irqrestore(&bank->lock, flags);
1510
1511 return 0;
1512}
1513
52e31344
DB		 1514static void gpio_set(struct gpio_chip *chip, unsigned offset, int value)
1515{
1516 struct gpio_bank *bank;
1517 unsigned long flags;
1518
1519 bank = container_of(chip, struct gpio_bank, chip);
1520 spin_lock_irqsave(&bank->lock, flags);
1521 _set_gpio_dataout(bank, offset, value);
1522 spin_unlock_irqrestore(&bank->lock, flags);
1523}
1524
a007b709
DB		 1525static int gpio_2irq(struct gpio_chip *chip, unsigned offset)
1526{
1527 struct gpio_bank *bank;
1528
1529 bank = container_of(chip, struct gpio_bank, chip);
1530 return bank->virtual_irq_start + offset;
1531}
1532
52e31344
DB		 1533/*---------------------------------------------------------------------*/
1534
9a748053 1535static void __init omap_gpio_show_rev(struct gpio_bank *bank)
9f7065da
TL		 1536{
1537 u32 rev;
1538
9a748053
TL		 1539 if (cpu_is_omap16xx() && !(bank->method != METHOD_MPUIO))
1540 rev = __raw_readw(bank->base + OMAP1610_GPIO_REVISION);
9f7065da 1541 else if (cpu_is_omap24xx() || cpu_is_omap34xx())
9a748053 1542 rev = __raw_readl(bank->base + OMAP24XX_GPIO_REVISION);
9f7065da 1543 else if (cpu_is_omap44xx())
9a748053 1544 rev = __raw_readl(bank->base + OMAP4_GPIO_REVISION);
9f7065da
TL		 1545 else
1546 return;
1547
1548 printk(KERN_INFO "OMAP GPIO hardware version %d.%d\n",
1549 (rev >> 4) & 0x0f, rev & 0x0f);
1550}
1551
8ba55c5c
DB		 1552/* This lock class tells lockdep that GPIO irqs are in a different
1553 * category than their parents, so it won't report false recursion.
1554 */
1555static struct lock_class_key gpio_lock_class;
1556
77640aab
VC		 1557static inline int init_gpio_info(struct platform_device *pdev)
1558{
1559 /* TODO: Analyze removing gpio_bank_count usage from driver code */
1560 gpio_bank = kzalloc(gpio_bank_count * sizeof(struct gpio_bank),
1561 GFP_KERNEL);
1562 if (!gpio_bank) {
1563 dev_err(&pdev->dev, "Memory alloc failed for gpio_bank\n");
1564 return -ENOMEM;
1565 }
1566 return 0;
1567}
1568
1569/* TODO: Cleanup cpu_is_* checks */
2fae7fbe
VC		 1570static void omap_gpio_mod_init(struct gpio_bank *bank, int id)
1571{
1572 if (cpu_class_is_omap2()) {
1573 if (cpu_is_omap44xx()) {
1574 __raw_writel(0xffffffff, bank->base +
1575 OMAP4_GPIO_IRQSTATUSCLR0);
1576 __raw_writel(0x00000000, bank->base +
1577 OMAP4_GPIO_DEBOUNCENABLE);
1578 /* Initialize interface clk ungated, module enabled */
1579 __raw_writel(0, bank->base + OMAP4_GPIO_CTRL);
1580 } else if (cpu_is_omap34xx()) {
1581 __raw_writel(0x00000000, bank->base +
1582 OMAP24XX_GPIO_IRQENABLE1);
1583 __raw_writel(0xffffffff, bank->base +
1584 OMAP24XX_GPIO_IRQSTATUS1);
1585 __raw_writel(0x00000000, bank->base +
1586 OMAP24XX_GPIO_DEBOUNCE_EN);
1587
1588 /* Initialize interface clk ungated, module enabled */
1589 __raw_writel(0, bank->base + OMAP24XX_GPIO_CTRL);
1590 } else if (cpu_is_omap24xx()) {
1591 static const u32 non_wakeup_gpios[] = {
1592 0xe203ffc0, 0x08700040
1593 };
1594 if (id < ARRAY_SIZE(non_wakeup_gpios))
1595 bank->non_wakeup_gpios = non_wakeup_gpios[id];
1596 }
1597 } else if (cpu_class_is_omap1()) {
1598 if (bank_is_mpuio(bank))
5de62b86
TL		 1599 __raw_writew(0xffff, bank->base +
1600 OMAP_MPUIO_GPIO_MASKIT / bank->stride);
2fae7fbe
VC		 1601 if (cpu_is_omap15xx() && bank->method == METHOD_GPIO_1510) {
1602 __raw_writew(0xffff, bank->base
1603 + OMAP1510_GPIO_INT_MASK);
1604 __raw_writew(0x0000, bank->base
1605 + OMAP1510_GPIO_INT_STATUS);
1606 }
1607 if (cpu_is_omap16xx() && bank->method == METHOD_GPIO_1610) {
1608 __raw_writew(0x0000, bank->base
1609 + OMAP1610_GPIO_IRQENABLE1);
1610 __raw_writew(0xffff, bank->base
1611 + OMAP1610_GPIO_IRQSTATUS1);
1612 __raw_writew(0x0014, bank->base
1613 + OMAP1610_GPIO_SYSCONFIG);
1614
1615 /*
1616 * Enable system clock for GPIO module.
1617 * The CAM_CLK_CTRL *is* really the right place.
1618 */
1619 omap_writel(omap_readl(ULPD_CAM_CLK_CTRL) | 0x04,
1620 ULPD_CAM_CLK_CTRL);
1621 }
1622 if (cpu_is_omap7xx() && bank->method == METHOD_GPIO_7XX) {
1623 __raw_writel(0xffffffff, bank->base
1624 + OMAP7XX_GPIO_INT_MASK);
1625 __raw_writel(0x00000000, bank->base
1626 + OMAP7XX_GPIO_INT_STATUS);
1627 }
1628 }
1629}
1630
1631static void __init omap_gpio_chip_init(struct gpio_bank *bank)
1632{
77640aab 1633 int j;
2fae7fbe
VC		 1634 static int gpio;
1635
2fae7fbe
VC		 1636 bank->mod_usage = 0;
1637 /*
1638 * REVISIT eventually switch from OMAP-specific gpio structs
1639 * over to the generic ones
1640 */
1641 bank->chip.request = omap_gpio_request;
1642 bank->chip.free = omap_gpio_free;
1643 bank->chip.direction_input = gpio_input;
1644 bank->chip.get = gpio_get;
1645 bank->chip.direction_output = gpio_output;
1646 bank->chip.set_debounce = gpio_debounce;
1647 bank->chip.set = gpio_set;
1648 bank->chip.to_irq = gpio_2irq;
1649 if (bank_is_mpuio(bank)) {
1650 bank->chip.label = "mpuio";
1651#ifdef CONFIG_ARCH_OMAP16XX
1652 bank->chip.dev = &omap_mpuio_device.dev;
1653#endif
1654 bank->chip.base = OMAP_MPUIO(0);
1655 } else {
1656 bank->chip.label = "gpio";
1657 bank->chip.base = gpio;
1658 gpio += bank_width;
1659 }
1660 bank->chip.ngpio = bank_width;
1661
1662 gpiochip_add(&bank->chip);
1663
1664 for (j = bank->virtual_irq_start;
1665 j < bank->virtual_irq_start + bank_width; j++) {
1475b85d 1666 irq_set_lockdep_class(j, &gpio_lock_class);
6845664a 1667 irq_set_chip_data(j, bank);
2fae7fbe 1668 if (bank_is_mpuio(bank))
6845664a 1669 irq_set_chip(j, &mpuio_irq_chip);
2fae7fbe 1670 else
6845664a
TG		 1671 irq_set_chip(j, &gpio_irq_chip);
1672 irq_set_handler(j, handle_simple_irq);
2fae7fbe
VC		 1673 set_irq_flags(j, IRQF_VALID);
1674 }
6845664a
TG		 1675 irq_set_chained_handler(bank->irq, gpio_irq_handler);
1676 irq_set_handler_data(bank->irq, bank);
2fae7fbe
VC		 1677}
1678
77640aab 1679static int __devinit omap_gpio_probe(struct platform_device *pdev)
5e1c5ff4 1680{
77640aab
VC		 1681 static int gpio_init_done;
1682 struct omap_gpio_platform_data *pdata;
1683 struct resource *res;
1684 int id;
5e1c5ff4
TL		 1685 struct gpio_bank *bank;
1686
77640aab
VC		 1687 if (!pdev->dev.platform_data)
1688 return -EINVAL;
5e1c5ff4 1689
77640aab 1690 pdata = pdev->dev.platform_data;
56a25641 1691
77640aab
VC		 1692 if (!gpio_init_done) {
1693 int ret;
5492fb1a 1694
77640aab
VC		 1695 ret = init_gpio_info(pdev);
1696 if (ret)
1697 return ret;
5492fb1a 1698 }
5492fb1a 1699
77640aab
VC		 1700 id = pdev->id;
1701 bank = &gpio_bank[id];
92105bb7 1702
77640aab
VC		 1703 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1704 if (unlikely(!res)) {
1705 dev_err(&pdev->dev, "GPIO Bank %i Invalid IRQ resource\n", id);
1706 return -ENODEV;
44169075 1707 }
5e1c5ff4 1708
77640aab
VC		 1709 bank->irq = res->start;
1710 bank->virtual_irq_start = pdata->virtual_irq_start;
1711 bank->method = pdata->bank_type;
1712 bank->dev = &pdev->dev;
1713 bank->dbck_flag = pdata->dbck_flag;
5de62b86 1714 bank->stride = pdata->bank_stride;
77640aab 1715 bank_width = pdata->bank_width;
9f7065da 1716
77640aab 1717 spin_lock_init(&bank->lock);
9f7065da 1718
77640aab
VC		 1719 /* Static mapping, never released */
1720 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1721 if (unlikely(!res)) {
1722 dev_err(&pdev->dev, "GPIO Bank %i Invalid mem resource\n", id);
1723 return -ENODEV;
1724 }
89db9482 1725
77640aab
VC		 1726 bank->base = ioremap(res->start, resource_size(res));
1727 if (!bank->base) {
1728 dev_err(&pdev->dev, "Could not ioremap gpio bank%i\n", id);
1729 return -ENOMEM;
5e1c5ff4
TL		 1730 }
1731
77640aab
VC		 1732 pm_runtime_enable(bank->dev);
1733 pm_runtime_get_sync(bank->dev);
1734
1735 omap_gpio_mod_init(bank, id);
1736 omap_gpio_chip_init(bank);
9a748053 1737 omap_gpio_show_rev(bank);
9f7065da 1738
77640aab
VC		 1739 if (!gpio_init_done)
1740 gpio_init_done = 1;
1741
5e1c5ff4
TL		 1742 return 0;
1743}
1744
140455fa 1745#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS)
3c437ffd 1746static int omap_gpio_suspend(void)
92105bb7
TL		 1747{
1748 int i;
1749
5492fb1a 1750 if (!cpu_class_is_omap2() && !cpu_is_omap16xx())
92105bb7
TL		 1751 return 0;
1752
1753 for (i = 0; i < gpio_bank_count; i++) {
1754 struct gpio_bank *bank = &gpio_bank[i];
1755 void __iomem *wake_status;
1756 void __iomem *wake_clear;
1757 void __iomem *wake_set;
a6472533 1758 unsigned long flags;
92105bb7
TL		 1759
1760 switch (bank->method) {
e5c56ed3 1761#ifdef CONFIG_ARCH_OMAP16XX
92105bb7
TL		 1762 case METHOD_GPIO_1610:
1763 wake_status = bank->base + OMAP1610_GPIO_WAKEUPENABLE;
1764 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1765 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1766 break;
e5c56ed3 1767#endif
a8eb7ca0 1768#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
92105bb7 1769 case METHOD_GPIO_24XX:
723fdb78 1770 wake_status = bank->base + OMAP24XX_GPIO_WAKE_EN;
92105bb7
TL		 1771 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1772 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
1773 break;
78a1a6d3
SR		 1774#endif
1775#ifdef CONFIG_ARCH_OMAP4
3f1686a9 1776 case METHOD_GPIO_44XX:
78a1a6d3
SR		 1777 wake_status = bank->base + OMAP4_GPIO_IRQWAKEN0;
1778 wake_clear = bank->base + OMAP4_GPIO_IRQWAKEN0;
1779 wake_set = bank->base + OMAP4_GPIO_IRQWAKEN0;
1780 break;
e5c56ed3 1781#endif
92105bb7
TL		 1782 default:
1783 continue;
1784 }
1785
a6472533 1786 spin_lock_irqsave(&bank->lock, flags);
92105bb7
TL		 1787 bank->saved_wakeup = __raw_readl(wake_status);
1788 __raw_writel(0xffffffff, wake_clear);
1789 __raw_writel(bank->suspend_wakeup, wake_set);
a6472533 1790 spin_unlock_irqrestore(&bank->lock, flags);
92105bb7
TL		 1791 }
1792
1793 return 0;
1794}
1795
3c437ffd 1796static void omap_gpio_resume(void)
92105bb7
TL		 1797{
1798 int i;
1799
723fdb78 1800 if (!cpu_class_is_omap2() && !cpu_is_omap16xx())
3c437ffd 1801 return;
92105bb7
TL		 1802
1803 for (i = 0; i < gpio_bank_count; i++) {
1804 struct gpio_bank *bank = &gpio_bank[i];
1805 void __iomem *wake_clear;
1806 void __iomem *wake_set;
a6472533 1807 unsigned long flags;
92105bb7
TL		 1808
1809 switch (bank->method) {
e5c56ed3 1810#ifdef CONFIG_ARCH_OMAP16XX
92105bb7
TL		 1811 case METHOD_GPIO_1610:
1812 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1813 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1814 break;
e5c56ed3 1815#endif
a8eb7ca0 1816#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
92105bb7 1817 case METHOD_GPIO_24XX:
0d9356cb
TL		 1818 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1819 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
92105bb7 1820 break;
78a1a6d3
SR		 1821#endif
1822#ifdef CONFIG_ARCH_OMAP4
3f1686a9 1823 case METHOD_GPIO_44XX:
78a1a6d3
SR		 1824 wake_clear = bank->base + OMAP4_GPIO_IRQWAKEN0;
1825 wake_set = bank->base + OMAP4_GPIO_IRQWAKEN0;
1826 break;
e5c56ed3 1827#endif
92105bb7
TL		 1828 default:
1829 continue;
1830 }
1831
a6472533 1832 spin_lock_irqsave(&bank->lock, flags);
92105bb7
TL		 1833 __raw_writel(0xffffffff, wake_clear);
1834 __raw_writel(bank->saved_wakeup, wake_set);
a6472533 1835 spin_unlock_irqrestore(&bank->lock, flags);
92105bb7 1836 }
92105bb7
TL		 1837}
1838
3c437ffd 1839static struct syscore_ops omap_gpio_syscore_ops = {
92105bb7
TL		 1840 .suspend = omap_gpio_suspend,
1841 .resume = omap_gpio_resume,
1842};
1843
3ac4fa99
JY		 1844#endif
1845
140455fa 1846#ifdef CONFIG_ARCH_OMAP2PLUS
3ac4fa99
JY		 1847
1848static int workaround_enabled;
1849
72e06d08 1850void omap2_gpio_prepare_for_idle(int off_mode)
3ac4fa99
JY		 1851{
1852 int i, c = 0;
a118b5f3 1853 int min = 0;
3ac4fa99 1854
a118b5f3
TK		 1855 if (cpu_is_omap34xx())
1856 min = 1;
43ffcd9a 1857
a118b5f3 1858 for (i = min; i < gpio_bank_count; i++) {
3ac4fa99 1859 struct gpio_bank *bank = &gpio_bank[i];
ca828760 1860 u32 l1 = 0, l2 = 0;
0aed0435 1861 int j;
3ac4fa99 1862
0aed0435 1863 for (j = 0; j < hweight_long(bank->dbck_enable_mask); j++)
8865b9b6
KH		 1864 clk_disable(bank->dbck);
1865
72e06d08 1866 if (!off_mode)
43ffcd9a
KH		 1867 continue;
1868
1869 /* If going to OFF, remove triggering for all
1870 * non-wakeup GPIOs. Otherwise spurious IRQs will be
1871 * generated. See OMAP2420 Errata item 1.101. */
3ac4fa99
JY		 1872 if (!(bank->enabled_non_wakeup_gpios))
1873 continue;
3f1686a9
TL		 1874
1875 if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
1876 bank->saved_datain = __raw_readl(bank->base +
1877 OMAP24XX_GPIO_DATAIN);
1878 l1 = __raw_readl(bank->base +
1879 OMAP24XX_GPIO_FALLINGDETECT);
1880 l2 = __raw_readl(bank->base +
1881 OMAP24XX_GPIO_RISINGDETECT);
1882 }
1883
1884 if (cpu_is_omap44xx()) {
1885 bank->saved_datain = __raw_readl(bank->base +
1886 OMAP4_GPIO_DATAIN);
1887 l1 = __raw_readl(bank->base +
1888 OMAP4_GPIO_FALLINGDETECT);
1889 l2 = __raw_readl(bank->base +
1890 OMAP4_GPIO_RISINGDETECT);
1891 }
1892
3ac4fa99
JY		 1893 bank->saved_fallingdetect = l1;
1894 bank->saved_risingdetect = l2;
1895 l1 &= ~bank->enabled_non_wakeup_gpios;
1896 l2 &= ~bank->enabled_non_wakeup_gpios;
3f1686a9
TL		 1897
1898 if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
1899 __raw_writel(l1, bank->base +
1900 OMAP24XX_GPIO_FALLINGDETECT);
1901 __raw_writel(l2, bank->base +
1902 OMAP24XX_GPIO_RISINGDETECT);
1903 }
1904
1905 if (cpu_is_omap44xx()) {
1906 __raw_writel(l1, bank->base + OMAP4_GPIO_FALLINGDETECT);
1907 __raw_writel(l2, bank->base + OMAP4_GPIO_RISINGDETECT);
1908 }
1909
3ac4fa99
JY		 1910 c++;
1911 }
1912 if (!c) {
1913 workaround_enabled = 0;
1914 return;
1915 }
1916 workaround_enabled = 1;
1917}
1918
43ffcd9a 1919void omap2_gpio_resume_after_idle(void)
3ac4fa99
JY		 1920{
1921 int i;
a118b5f3 1922 int min = 0;
3ac4fa99 1923
a118b5f3
TK		 1924 if (cpu_is_omap34xx())
1925 min = 1;
1926 for (i = min; i < gpio_bank_count; i++) {
3ac4fa99 1927 struct gpio_bank *bank = &gpio_bank[i];
ca828760 1928 u32 l = 0, gen, gen0, gen1;
0aed0435 1929 int j;
3ac4fa99 1930
0aed0435 1931 for (j = 0; j < hweight_long(bank->dbck_enable_mask); j++)
8865b9b6
KH		 1932 clk_enable(bank->dbck);
1933
43ffcd9a
KH		 1934 if (!workaround_enabled)
1935 continue;
1936
3ac4fa99
JY		 1937 if (!(bank->enabled_non_wakeup_gpios))
1938 continue;
3f1686a9
TL		 1939
1940 if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
1941 __raw_writel(bank->saved_fallingdetect,
3ac4fa99 1942 bank->base + OMAP24XX_GPIO_FALLINGDETECT);
3f1686a9 1943 __raw_writel(bank->saved_risingdetect,
3ac4fa99 1944 bank->base + OMAP24XX_GPIO_RISINGDETECT);
3f1686a9
TL		 1945 l = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN);
1946 }
1947
1948 if (cpu_is_omap44xx()) {
1949 __raw_writel(bank->saved_fallingdetect,
78a1a6d3 1950 bank->base + OMAP4_GPIO_FALLINGDETECT);
3f1686a9 1951 __raw_writel(bank->saved_risingdetect,
78a1a6d3 1952 bank->base + OMAP4_GPIO_RISINGDETECT);
3f1686a9
TL		 1953 l = __raw_readl(bank->base + OMAP4_GPIO_DATAIN);
1954 }
1955
3ac4fa99
JY		 1956 /* Check if any of the non-wakeup interrupt GPIOs have changed
1957 * state. If so, generate an IRQ by software. This is
1958 * horribly racy, but it's the best we can do to work around
1959 * this silicon bug. */
3ac4fa99 1960 l ^= bank->saved_datain;
a118b5f3 1961 l &= bank->enabled_non_wakeup_gpios;
82dbb9d3
EN		 1962
1963 /*
1964 * No need to generate IRQs for the rising edge for gpio IRQs
1965 * configured with falling edge only; and vice versa.
1966 */
1967 gen0 = l & bank->saved_fallingdetect;
1968 gen0 &= bank->saved_datain;
1969
1970 gen1 = l & bank->saved_risingdetect;
1971 gen1 &= ~(bank->saved_datain);
1972
1973 /* FIXME: Consider GPIO IRQs with level detections properly! */
1974 gen = l & (~(bank->saved_fallingdetect) &
1975 ~(bank->saved_risingdetect));
1976 /* Consider all GPIO IRQs needed to be updated */
1977 gen |= gen0 | gen1;
1978
1979 if (gen) {
3ac4fa99 1980 u32 old0, old1;
3f1686a9 1981
f00d6497 1982 if (cpu_is_omap24xx() || cpu_is_omap34xx()) {
3f1686a9
TL		 1983 old0 = __raw_readl(bank->base +
1984 OMAP24XX_GPIO_LEVELDETECT0);
1985 old1 = __raw_readl(bank->base +
1986 OMAP24XX_GPIO_LEVELDETECT1);
f00d6497 1987 __raw_writel(old0 | gen, bank->base +
82dbb9d3 1988 OMAP24XX_GPIO_LEVELDETECT0);
f00d6497 1989 __raw_writel(old1 | gen, bank->base +
82dbb9d3 1990 OMAP24XX_GPIO_LEVELDETECT1);
f00d6497 1991 __raw_writel(old0, bank->base +
3f1686a9 1992 OMAP24XX_GPIO_LEVELDETECT0);
f00d6497 1993 __raw_writel(old1, bank->base +
3f1686a9
TL		 1994 OMAP24XX_GPIO_LEVELDETECT1);
1995 }
1996
1997 if (cpu_is_omap44xx()) {
1998 old0 = __raw_readl(bank->base +
78a1a6d3 1999 OMAP4_GPIO_LEVELDETECT0);
3f1686a9 2000 old1 = __raw_readl(bank->base +
78a1a6d3 2001 OMAP4_GPIO_LEVELDETECT1);
3f1686a9 2002 __raw_writel(old0 | l, bank->base +
78a1a6d3 2003 OMAP4_GPIO_LEVELDETECT0);
3f1686a9 2004 __raw_writel(old1 | l, bank->base +
78a1a6d3 2005 OMAP4_GPIO_LEVELDETECT1);
3f1686a9 2006 __raw_writel(old0, bank->base +
78a1a6d3 2007 OMAP4_GPIO_LEVELDETECT0);
3f1686a9 2008 __raw_writel(old1, bank->base +
78a1a6d3 2009 OMAP4_GPIO_LEVELDETECT1);
3f1686a9 2010 }
3ac4fa99
JY		 2011 }
2012 }
2013
2014}
2015
92105bb7
TL		 2016#endif
2017
a8eb7ca0 2018#ifdef CONFIG_ARCH_OMAP3
40c670f0
RN		 2019/* save the registers of bank 2-6 */
2020void omap_gpio_save_context(void)
2021{
2022 int i;
2023
2024 /* saving banks from 2-6 only since GPIO1 is in WKUP */
2025 for (i = 1; i < gpio_bank_count; i++) {
2026 struct gpio_bank *bank = &gpio_bank[i];
40c670f0
RN		 2027 gpio_context[i].irqenable1 =
2028 __raw_readl(bank->base + OMAP24XX_GPIO_IRQENABLE1);
2029 gpio_context[i].irqenable2 =
2030 __raw_readl(bank->base + OMAP24XX_GPIO_IRQENABLE2);
2031 gpio_context[i].wake_en =
2032 __raw_readl(bank->base + OMAP24XX_GPIO_WAKE_EN);
2033 gpio_context[i].ctrl =
2034 __raw_readl(bank->base + OMAP24XX_GPIO_CTRL);
2035 gpio_context[i].oe =
2036 __raw_readl(bank->base + OMAP24XX_GPIO_OE);
2037 gpio_context[i].leveldetect0 =
2038 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0);
2039 gpio_context[i].leveldetect1 =
2040 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
2041 gpio_context[i].risingdetect =
2042 __raw_readl(bank->base + OMAP24XX_GPIO_RISINGDETECT);
2043 gpio_context[i].fallingdetect =
2044 __raw_readl(bank->base + OMAP24XX_GPIO_FALLINGDETECT);
2045 gpio_context[i].dataout =
2046 __raw_readl(bank->base + OMAP24XX_GPIO_DATAOUT);
40c670f0
RN		 2047 }
2048}
2049
2050/* restore the required registers of bank 2-6 */
2051void omap_gpio_restore_context(void)
2052{
2053 int i;
2054
2055 for (i = 1; i < gpio_bank_count; i++) {
2056 struct gpio_bank *bank = &gpio_bank[i];
40c670f0
RN		 2057 __raw_writel(gpio_context[i].irqenable1,
2058 bank->base + OMAP24XX_GPIO_IRQENABLE1);
2059 __raw_writel(gpio_context[i].irqenable2,
2060 bank->base + OMAP24XX_GPIO_IRQENABLE2);
2061 __raw_writel(gpio_context[i].wake_en,
2062 bank->base + OMAP24XX_GPIO_WAKE_EN);
2063 __raw_writel(gpio_context[i].ctrl,
2064 bank->base + OMAP24XX_GPIO_CTRL);
2065 __raw_writel(gpio_context[i].oe,
2066 bank->base + OMAP24XX_GPIO_OE);
2067 __raw_writel(gpio_context[i].leveldetect0,
2068 bank->base + OMAP24XX_GPIO_LEVELDETECT0);
2069 __raw_writel(gpio_context[i].leveldetect1,
2070 bank->base + OMAP24XX_GPIO_LEVELDETECT1);
2071 __raw_writel(gpio_context[i].risingdetect,
2072 bank->base + OMAP24XX_GPIO_RISINGDETECT);
2073 __raw_writel(gpio_context[i].fallingdetect,
2074 bank->base + OMAP24XX_GPIO_FALLINGDETECT);
2075 __raw_writel(gpio_context[i].dataout,
2076 bank->base + OMAP24XX_GPIO_DATAOUT);
40c670f0
RN		 2077 }
2078}
2079#endif
2080
77640aab
VC		 2081static struct platform_driver omap_gpio_driver = {
2082 .probe = omap_gpio_probe,
2083 .driver = {
2084 .name = "omap_gpio",
2085 },
2086};
2087
5e1c5ff4 2088/*
77640aab
VC		 2089 * gpio driver register needs to be done before
2090 * machine_init functions access gpio APIs.
2091 * Hence omap_gpio_drv_reg() is a postcore_initcall.
5e1c5ff4 2092 */
77640aab 2093static int __init omap_gpio_drv_reg(void)
5e1c5ff4 2094{
77640aab 2095 return platform_driver_register(&omap_gpio_driver);
5e1c5ff4 2096}
77640aab 2097postcore_initcall(omap_gpio_drv_reg);
5e1c5ff4 2098
92105bb7
TL		 2099static int __init omap_gpio_sysinit(void)
2100{
11a78b79
DB		 2101 mpuio_init();
2102
140455fa 2103#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP2PLUS)
3c437ffd
RW		 2104 if (cpu_is_omap16xx() || cpu_class_is_omap2())
2105 register_syscore_ops(&omap_gpio_syscore_ops);
92105bb7
TL		 2106#endif
2107
3c437ffd 2108 return 0;
92105bb7
TL		 2109}
2110
92105bb7 2111arch_initcall(omap_gpio_sysinit);
Linux kernel - Deliverables
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