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ARM: OMAP3: pandora: add support for mode devices
[deliverable/linux.git] / arch / arm / plat-omap / gpio.c
CommitLineData
5e1c5ff4
TL		 1/*
2 * linux/arch/arm/plat-omap/gpio.c
3 *
4 * Support functions for OMAP GPIO
5 *
92105bb7 6 * Copyright (C) 2003-2005 Nokia Corporation
96de0e25 7 * Written by Juha Yrjölä <juha.yrjola@nokia.com>
5e1c5ff4
TL		 8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
5e1c5ff4
TL		 14#include <linux/init.h>
15#include <linux/module.h>
5e1c5ff4 16#include <linux/interrupt.h>
92105bb7
TL		 17#include <linux/sysdev.h>
18#include <linux/err.h>
f8ce2547 19#include <linux/clk.h>
fced80c7 20#include <linux/io.h>
5e1c5ff4 21
a09e64fb 22#include <mach/hardware.h>
5e1c5ff4 23#include <asm/irq.h>
a09e64fb
RK		 24#include <mach/irqs.h>
25#include <mach/gpio.h>
5e1c5ff4
TL		 26#include <asm/mach/irq.h>
27
5e1c5ff4
TL		 28/*
29 * OMAP1510 GPIO registers
30 */
7c7095aa 31#define OMAP1510_GPIO_BASE IO_ADDRESS(0xfffce000)
5e1c5ff4
TL		 32#define OMAP1510_GPIO_DATA_INPUT 0x00
33#define OMAP1510_GPIO_DATA_OUTPUT 0x04
34#define OMAP1510_GPIO_DIR_CONTROL 0x08
35#define OMAP1510_GPIO_INT_CONTROL 0x0c
36#define OMAP1510_GPIO_INT_MASK 0x10
37#define OMAP1510_GPIO_INT_STATUS 0x14
38#define OMAP1510_GPIO_PIN_CONTROL 0x18
39
40#define OMAP1510_IH_GPIO_BASE 64
41
42/*
43 * OMAP1610 specific GPIO registers
44 */
7c7095aa
RK		 45#define OMAP1610_GPIO1_BASE IO_ADDRESS(0xfffbe400)
46#define OMAP1610_GPIO2_BASE IO_ADDRESS(0xfffbec00)
47#define OMAP1610_GPIO3_BASE IO_ADDRESS(0xfffbb400)
48#define OMAP1610_GPIO4_BASE IO_ADDRESS(0xfffbbc00)
5e1c5ff4
TL		 49#define OMAP1610_GPIO_REVISION 0x0000
50#define OMAP1610_GPIO_SYSCONFIG 0x0010
51#define OMAP1610_GPIO_SYSSTATUS 0x0014
52#define OMAP1610_GPIO_IRQSTATUS1 0x0018
53#define OMAP1610_GPIO_IRQENABLE1 0x001c
92105bb7 54#define OMAP1610_GPIO_WAKEUPENABLE 0x0028
5e1c5ff4
TL		 55#define OMAP1610_GPIO_DATAIN 0x002c
56#define OMAP1610_GPIO_DATAOUT 0x0030
57#define OMAP1610_GPIO_DIRECTION 0x0034
58#define OMAP1610_GPIO_EDGE_CTRL1 0x0038
59#define OMAP1610_GPIO_EDGE_CTRL2 0x003c
60#define OMAP1610_GPIO_CLEAR_IRQENABLE1 0x009c
92105bb7 61#define OMAP1610_GPIO_CLEAR_WAKEUPENA 0x00a8
5e1c5ff4
TL		 62#define OMAP1610_GPIO_CLEAR_DATAOUT 0x00b0
63#define OMAP1610_GPIO_SET_IRQENABLE1 0x00dc
92105bb7 64#define OMAP1610_GPIO_SET_WAKEUPENA 0x00e8
5e1c5ff4
TL		 65#define OMAP1610_GPIO_SET_DATAOUT 0x00f0
66
67/*
68 * OMAP730 specific GPIO registers
69 */
7c7095aa
RK		 70#define OMAP730_GPIO1_BASE IO_ADDRESS(0xfffbc000)
71#define OMAP730_GPIO2_BASE IO_ADDRESS(0xfffbc800)
72#define OMAP730_GPIO3_BASE IO_ADDRESS(0xfffbd000)
73#define OMAP730_GPIO4_BASE IO_ADDRESS(0xfffbd800)
74#define OMAP730_GPIO5_BASE IO_ADDRESS(0xfffbe000)
75#define OMAP730_GPIO6_BASE IO_ADDRESS(0xfffbe800)
5e1c5ff4
TL		 76#define OMAP730_GPIO_DATA_INPUT 0x00
77#define OMAP730_GPIO_DATA_OUTPUT 0x04
78#define OMAP730_GPIO_DIR_CONTROL 0x08
79#define OMAP730_GPIO_INT_CONTROL 0x0c
80#define OMAP730_GPIO_INT_MASK 0x10
81#define OMAP730_GPIO_INT_STATUS 0x14
82
56739a69
ZM		 83/*
84 * OMAP850 specific GPIO registers
85 */
86#define OMAP850_GPIO1_BASE IO_ADDRESS(0xfffbc000)
87#define OMAP850_GPIO2_BASE IO_ADDRESS(0xfffbc800)
88#define OMAP850_GPIO3_BASE IO_ADDRESS(0xfffbd000)
89#define OMAP850_GPIO4_BASE IO_ADDRESS(0xfffbd800)
90#define OMAP850_GPIO5_BASE IO_ADDRESS(0xfffbe000)
91#define OMAP850_GPIO6_BASE IO_ADDRESS(0xfffbe800)
92#define OMAP850_GPIO_DATA_INPUT 0x00
93#define OMAP850_GPIO_DATA_OUTPUT 0x04
94#define OMAP850_GPIO_DIR_CONTROL 0x08
95#define OMAP850_GPIO_INT_CONTROL 0x0c
96#define OMAP850_GPIO_INT_MASK 0x10
97#define OMAP850_GPIO_INT_STATUS 0x14
98
92105bb7
TL		 99/*
100 * omap24xx specific GPIO registers
101 */
7c7095aa
RK		 102#define OMAP242X_GPIO1_BASE IO_ADDRESS(0x48018000)
103#define OMAP242X_GPIO2_BASE IO_ADDRESS(0x4801a000)
104#define OMAP242X_GPIO3_BASE IO_ADDRESS(0x4801c000)
105#define OMAP242X_GPIO4_BASE IO_ADDRESS(0x4801e000)
56a25641 106
7c7095aa
RK		 107#define OMAP243X_GPIO1_BASE IO_ADDRESS(0x4900C000)
108#define OMAP243X_GPIO2_BASE IO_ADDRESS(0x4900E000)
109#define OMAP243X_GPIO3_BASE IO_ADDRESS(0x49010000)
110#define OMAP243X_GPIO4_BASE IO_ADDRESS(0x49012000)
111#define OMAP243X_GPIO5_BASE IO_ADDRESS(0x480B6000)
56a25641 112
92105bb7
TL		 113#define OMAP24XX_GPIO_REVISION 0x0000
114#define OMAP24XX_GPIO_SYSCONFIG 0x0010
115#define OMAP24XX_GPIO_SYSSTATUS 0x0014
116#define OMAP24XX_GPIO_IRQSTATUS1 0x0018
bee7930f
HD		 117#define OMAP24XX_GPIO_IRQSTATUS2 0x0028
118#define OMAP24XX_GPIO_IRQENABLE2 0x002c
92105bb7 119#define OMAP24XX_GPIO_IRQENABLE1 0x001c
723fdb78 120#define OMAP24XX_GPIO_WAKE_EN 0x0020
92105bb7
TL		 121#define OMAP24XX_GPIO_CTRL 0x0030
122#define OMAP24XX_GPIO_OE 0x0034
123#define OMAP24XX_GPIO_DATAIN 0x0038
124#define OMAP24XX_GPIO_DATAOUT 0x003c
125#define OMAP24XX_GPIO_LEVELDETECT0 0x0040
126#define OMAP24XX_GPIO_LEVELDETECT1 0x0044
127#define OMAP24XX_GPIO_RISINGDETECT 0x0048
128#define OMAP24XX_GPIO_FALLINGDETECT 0x004c
5eb3bb9c
KH		 129#define OMAP24XX_GPIO_DEBOUNCE_EN 0x0050
130#define OMAP24XX_GPIO_DEBOUNCE_VAL 0x0054
92105bb7
TL		 131#define OMAP24XX_GPIO_CLEARIRQENABLE1 0x0060
132#define OMAP24XX_GPIO_SETIRQENABLE1 0x0064
133#define OMAP24XX_GPIO_CLEARWKUENA 0x0080
134#define OMAP24XX_GPIO_SETWKUENA 0x0084
135#define OMAP24XX_GPIO_CLEARDATAOUT 0x0090
136#define OMAP24XX_GPIO_SETDATAOUT 0x0094
137
5492fb1a
SMK		 138/*
139 * omap34xx specific GPIO registers
140 */
141
7c7095aa
RK		 142#define OMAP34XX_GPIO1_BASE IO_ADDRESS(0x48310000)
143#define OMAP34XX_GPIO2_BASE IO_ADDRESS(0x49050000)
144#define OMAP34XX_GPIO3_BASE IO_ADDRESS(0x49052000)
145#define OMAP34XX_GPIO4_BASE IO_ADDRESS(0x49054000)
146#define OMAP34XX_GPIO5_BASE IO_ADDRESS(0x49056000)
147#define OMAP34XX_GPIO6_BASE IO_ADDRESS(0x49058000)
5492fb1a 148
7c7095aa 149#define OMAP_MPUIO_VBASE IO_ADDRESS(OMAP_MPUIO_BASE)
5492fb1a 150
5e1c5ff4 151struct gpio_bank {
92105bb7 152 void __iomem *base;
5e1c5ff4
TL		 153 u16 irq;
154 u16 virtual_irq_start;
92105bb7 155 int method;
5492fb1a 156#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
92105bb7
TL		 157 u32 suspend_wakeup;
158 u32 saved_wakeup;
3ac4fa99 159#endif
5492fb1a 160#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
3ac4fa99
JY		 161 u32 non_wakeup_gpios;
162 u32 enabled_non_wakeup_gpios;
163
164 u32 saved_datain;
165 u32 saved_fallingdetect;
166 u32 saved_risingdetect;
167#endif
b144ff6f 168 u32 level_mask;
5e1c5ff4 169 spinlock_t lock;
52e31344 170 struct gpio_chip chip;
89db9482 171 struct clk *dbck;
5e1c5ff4
TL		 172};
173
174#define METHOD_MPUIO 0
175#define METHOD_GPIO_1510 1
176#define METHOD_GPIO_1610 2
177#define METHOD_GPIO_730 3
56739a69
ZM		 178#define METHOD_GPIO_850 4
179#define METHOD_GPIO_24XX 5
5e1c5ff4 180
92105bb7 181#ifdef CONFIG_ARCH_OMAP16XX
5e1c5ff4 182static struct gpio_bank gpio_bank_1610[5] = {
7c7095aa 183 { OMAP_MPUIO_VBASE, INT_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO},
5e1c5ff4
TL		 184 { OMAP1610_GPIO1_BASE, INT_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_1610 },
185 { OMAP1610_GPIO2_BASE, INT_1610_GPIO_BANK2, IH_GPIO_BASE + 16, METHOD_GPIO_1610 },
186 { OMAP1610_GPIO3_BASE, INT_1610_GPIO_BANK3, IH_GPIO_BASE + 32, METHOD_GPIO_1610 },
187 { OMAP1610_GPIO4_BASE, INT_1610_GPIO_BANK4, IH_GPIO_BASE + 48, METHOD_GPIO_1610 },
188};
189#endif
190
1a8bfa1e 191#ifdef CONFIG_ARCH_OMAP15XX
5e1c5ff4 192static struct gpio_bank gpio_bank_1510[2] = {
7c7095aa 193 { OMAP_MPUIO_VBASE, INT_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO },
5e1c5ff4
TL		 194 { OMAP1510_GPIO_BASE, INT_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_1510 }
195};
196#endif
197
198#ifdef CONFIG_ARCH_OMAP730
199static struct gpio_bank gpio_bank_730[7] = {
7c7095aa 200 { OMAP_MPUIO_VBASE, INT_730_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO },
5e1c5ff4
TL		 201 { OMAP730_GPIO1_BASE, INT_730_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_730 },
202 { OMAP730_GPIO2_BASE, INT_730_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_730 },
203 { OMAP730_GPIO3_BASE, INT_730_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_730 },
204 { OMAP730_GPIO4_BASE, INT_730_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_730 },
205 { OMAP730_GPIO5_BASE, INT_730_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_730 },
206 { OMAP730_GPIO6_BASE, INT_730_GPIO_BANK6, IH_GPIO_BASE + 160, METHOD_GPIO_730 },
207};
208#endif
209
56739a69
ZM		 210#ifdef CONFIG_ARCH_OMAP850
211static struct gpio_bank gpio_bank_850[7] = {
212 { OMAP_MPUIO_BASE, INT_850_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO },
213 { OMAP850_GPIO1_BASE, INT_850_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_850 },
214 { OMAP850_GPIO2_BASE, INT_850_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_850 },
215 { OMAP850_GPIO3_BASE, INT_850_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_850 },
216 { OMAP850_GPIO4_BASE, INT_850_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_850 },
217 { OMAP850_GPIO5_BASE, INT_850_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_850 },
218 { OMAP850_GPIO6_BASE, INT_850_GPIO_BANK6, IH_GPIO_BASE + 160, METHOD_GPIO_850 },
219};
220#endif
221
222
92105bb7 223#ifdef CONFIG_ARCH_OMAP24XX
56a25641
SMK		 224
225static struct gpio_bank gpio_bank_242x[4] = {
226 { OMAP242X_GPIO1_BASE, INT_24XX_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_24XX },
227 { OMAP242X_GPIO2_BASE, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_24XX },
228 { OMAP242X_GPIO3_BASE, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_24XX },
229 { OMAP242X_GPIO4_BASE, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_24XX },
92105bb7 230};
56a25641
SMK		 231
232static struct gpio_bank gpio_bank_243x[5] = {
233 { OMAP243X_GPIO1_BASE, INT_24XX_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_24XX },
234 { OMAP243X_GPIO2_BASE, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_24XX },
235 { OMAP243X_GPIO3_BASE, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_24XX },
236 { OMAP243X_GPIO4_BASE, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_24XX },
237 { OMAP243X_GPIO5_BASE, INT_24XX_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_24XX },
238};
239
92105bb7
TL		 240#endif
241
5492fb1a
SMK		 242#ifdef CONFIG_ARCH_OMAP34XX
243static struct gpio_bank gpio_bank_34xx[6] = {
244 { OMAP34XX_GPIO1_BASE, INT_34XX_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_24XX },
245 { OMAP34XX_GPIO2_BASE, INT_34XX_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_24XX },
246 { OMAP34XX_GPIO3_BASE, INT_34XX_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_24XX },
247 { OMAP34XX_GPIO4_BASE, INT_34XX_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_24XX },
248 { OMAP34XX_GPIO5_BASE, INT_34XX_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_24XX },
249 { OMAP34XX_GPIO6_BASE, INT_34XX_GPIO_BANK6, IH_GPIO_BASE + 160, METHOD_GPIO_24XX },
250};
251
252#endif
253
5e1c5ff4
TL		 254static struct gpio_bank *gpio_bank;
255static int gpio_bank_count;
256
257static inline struct gpio_bank *get_gpio_bank(int gpio)
258{
6e60e79a 259 if (cpu_is_omap15xx()) {
5e1c5ff4
TL		 260 if (OMAP_GPIO_IS_MPUIO(gpio))
261 return &gpio_bank[0];
262 return &gpio_bank[1];
263 }
5e1c5ff4
TL		 264 if (cpu_is_omap16xx()) {
265 if (OMAP_GPIO_IS_MPUIO(gpio))
266 return &gpio_bank[0];
267 return &gpio_bank[1 + (gpio >> 4)];
268 }
56739a69 269 if (cpu_is_omap7xx()) {
5e1c5ff4
TL		 270 if (OMAP_GPIO_IS_MPUIO(gpio))
271 return &gpio_bank[0];
272 return &gpio_bank[1 + (gpio >> 5)];
273 }
92105bb7
TL		 274 if (cpu_is_omap24xx())
275 return &gpio_bank[gpio >> 5];
5492fb1a
SMK		 276 if (cpu_is_omap34xx())
277 return &gpio_bank[gpio >> 5];
e031ab23
DB		 278 BUG();
279 return NULL;
5e1c5ff4
TL		 280}
281
282static inline int get_gpio_index(int gpio)
283{
56739a69 284 if (cpu_is_omap7xx())
5e1c5ff4 285 return gpio & 0x1f;
92105bb7
TL		 286 if (cpu_is_omap24xx())
287 return gpio & 0x1f;
5492fb1a
SMK		 288 if (cpu_is_omap34xx())
289 return gpio & 0x1f;
92105bb7 290 return gpio & 0x0f;
5e1c5ff4
TL		 291}
292
293static inline int gpio_valid(int gpio)
294{
295 if (gpio < 0)
296 return -1;
d11ac979 297 if (cpu_class_is_omap1() && OMAP_GPIO_IS_MPUIO(gpio)) {
193e68be 298 if (gpio >= OMAP_MAX_GPIO_LINES + 16)
5e1c5ff4
TL		 299 return -1;
300 return 0;
301 }
6e60e79a 302 if (cpu_is_omap15xx() && gpio < 16)
5e1c5ff4 303 return 0;
5e1c5ff4
TL		 304 if ((cpu_is_omap16xx()) && gpio < 64)
305 return 0;
56739a69 306 if (cpu_is_omap7xx() && gpio < 192)
5e1c5ff4 307 return 0;
92105bb7
TL		 308 if (cpu_is_omap24xx() && gpio < 128)
309 return 0;
e102657e 310 if (cpu_is_omap34xx() && gpio < 192)
5492fb1a 311 return 0;
5e1c5ff4
TL		 312 return -1;
313}
314
315static int check_gpio(int gpio)
316{
317 if (unlikely(gpio_valid(gpio)) < 0) {
318 printk(KERN_ERR "omap-gpio: invalid GPIO %d\n", gpio);
319 dump_stack();
320 return -1;
321 }
322 return 0;
323}
324
325static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input)
326{
92105bb7 327 void __iomem *reg = bank->base;
5e1c5ff4
TL		 328 u32 l;
329
330 switch (bank->method) {
e5c56ed3 331#ifdef CONFIG_ARCH_OMAP1
5e1c5ff4
TL		 332 case METHOD_MPUIO:
333 reg += OMAP_MPUIO_IO_CNTL;
334 break;
e5c56ed3
DB		 335#endif
336#ifdef CONFIG_ARCH_OMAP15XX
5e1c5ff4
TL		 337 case METHOD_GPIO_1510:
338 reg += OMAP1510_GPIO_DIR_CONTROL;
339 break;
e5c56ed3
DB		 340#endif
341#ifdef CONFIG_ARCH_OMAP16XX
5e1c5ff4
TL		 342 case METHOD_GPIO_1610:
343 reg += OMAP1610_GPIO_DIRECTION;
344 break;
e5c56ed3
DB		 345#endif
346#ifdef CONFIG_ARCH_OMAP730
5e1c5ff4
TL		 347 case METHOD_GPIO_730:
348 reg += OMAP730_GPIO_DIR_CONTROL;
349 break;
e5c56ed3 350#endif
56739a69
ZM		 351#ifdef CONFIG_ARCH_OMAP850
352 case METHOD_GPIO_850:
353 reg += OMAP850_GPIO_DIR_CONTROL;
354 break;
355#endif
5492fb1a 356#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
92105bb7
TL		 357 case METHOD_GPIO_24XX:
358 reg += OMAP24XX_GPIO_OE;
359 break;
e5c56ed3
DB		 360#endif
361 default:
362 WARN_ON(1);
363 return;
5e1c5ff4
TL		 364 }
365 l = __raw_readl(reg);
366 if (is_input)
367 l |= 1 << gpio;
368 else
369 l &= ~(1 << gpio);
370 __raw_writel(l, reg);
371}
372
5e1c5ff4
TL		 373static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable)
374{
92105bb7 375 void __iomem *reg = bank->base;
5e1c5ff4
TL		 376 u32 l = 0;
377
378 switch (bank->method) {
e5c56ed3 379#ifdef CONFIG_ARCH_OMAP1
5e1c5ff4
TL		 380 case METHOD_MPUIO:
381 reg += OMAP_MPUIO_OUTPUT;
382 l = __raw_readl(reg);
383 if (enable)
384 l |= 1 << gpio;
385 else
386 l &= ~(1 << gpio);
387 break;
e5c56ed3
DB		 388#endif
389#ifdef CONFIG_ARCH_OMAP15XX
5e1c5ff4
TL		 390 case METHOD_GPIO_1510:
391 reg += OMAP1510_GPIO_DATA_OUTPUT;
392 l = __raw_readl(reg);
393 if (enable)
394 l |= 1 << gpio;
395 else
396 l &= ~(1 << gpio);
397 break;
e5c56ed3
DB		 398#endif
399#ifdef CONFIG_ARCH_OMAP16XX
5e1c5ff4
TL		 400 case METHOD_GPIO_1610:
401 if (enable)
402 reg += OMAP1610_GPIO_SET_DATAOUT;
403 else
404 reg += OMAP1610_GPIO_CLEAR_DATAOUT;
405 l = 1 << gpio;
406 break;
e5c56ed3
DB		 407#endif
408#ifdef CONFIG_ARCH_OMAP730
5e1c5ff4
TL		 409 case METHOD_GPIO_730:
410 reg += OMAP730_GPIO_DATA_OUTPUT;
411 l = __raw_readl(reg);
412 if (enable)
413 l |= 1 << gpio;
414 else
415 l &= ~(1 << gpio);
416 break;
e5c56ed3 417#endif
56739a69
ZM		 418#ifdef CONFIG_ARCH_OMAP850
419 case METHOD_GPIO_850:
420 reg += OMAP850_GPIO_DATA_OUTPUT;
421 l = __raw_readl(reg);
422 if (enable)
423 l |= 1 << gpio;
424 else
425 l &= ~(1 << gpio);
426 break;
427#endif
5492fb1a 428#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
92105bb7
TL		 429 case METHOD_GPIO_24XX:
430 if (enable)
431 reg += OMAP24XX_GPIO_SETDATAOUT;
432 else
433 reg += OMAP24XX_GPIO_CLEARDATAOUT;
434 l = 1 << gpio;
435 break;
e5c56ed3 436#endif
5e1c5ff4 437 default:
e5c56ed3 438 WARN_ON(1);
5e1c5ff4
TL		 439 return;
440 }
441 __raw_writel(l, reg);
442}
443
0b84b5ca 444static int __omap_get_gpio_datain(int gpio)
5e1c5ff4
TL		 445{
446 struct gpio_bank *bank;
92105bb7 447 void __iomem *reg;
5e1c5ff4
TL		 448
449 if (check_gpio(gpio) < 0)
e5c56ed3 450 return -EINVAL;
5e1c5ff4
TL		 451 bank = get_gpio_bank(gpio);
452 reg = bank->base;
453 switch (bank->method) {
e5c56ed3 454#ifdef CONFIG_ARCH_OMAP1
5e1c5ff4
TL		 455 case METHOD_MPUIO:
456 reg += OMAP_MPUIO_INPUT_LATCH;
457 break;
e5c56ed3
DB		 458#endif
459#ifdef CONFIG_ARCH_OMAP15XX
5e1c5ff4
TL		 460 case METHOD_GPIO_1510:
461 reg += OMAP1510_GPIO_DATA_INPUT;
462 break;
e5c56ed3
DB		 463#endif
464#ifdef CONFIG_ARCH_OMAP16XX
5e1c5ff4
TL		 465 case METHOD_GPIO_1610:
466 reg += OMAP1610_GPIO_DATAIN;
467 break;
e5c56ed3
DB		 468#endif
469#ifdef CONFIG_ARCH_OMAP730
5e1c5ff4
TL		 470 case METHOD_GPIO_730:
471 reg += OMAP730_GPIO_DATA_INPUT;
472 break;
e5c56ed3 473#endif
56739a69
ZM		 474#ifdef CONFIG_ARCH_OMAP850
475 case METHOD_GPIO_850:
476 reg += OMAP850_GPIO_DATA_INPUT;
477 break;
478#endif
5492fb1a 479#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
92105bb7
TL		 480 case METHOD_GPIO_24XX:
481 reg += OMAP24XX_GPIO_DATAIN;
482 break;
e5c56ed3 483#endif
5e1c5ff4 484 default:
e5c56ed3 485 return -EINVAL;
5e1c5ff4 486 }
92105bb7
TL		 487 return (__raw_readl(reg)
488 & (1 << get_gpio_index(gpio))) != 0;
5e1c5ff4
TL		 489}
490
92105bb7
TL		 491#define MOD_REG_BIT(reg, bit_mask, set) \
492do { \
493 int l = __raw_readl(base + reg); \
494 if (set) l |= bit_mask; \
495 else l &= ~bit_mask; \
496 __raw_writel(l, base + reg); \
497} while(0)
498
5eb3bb9c
KH		 499void omap_set_gpio_debounce(int gpio, int enable)
500{
501 struct gpio_bank *bank;
502 void __iomem *reg;
e031ab23 503 unsigned long flags;
5eb3bb9c
KH		 504 u32 val, l = 1 << get_gpio_index(gpio);
505
506 if (cpu_class_is_omap1())
507 return;
508
509 bank = get_gpio_bank(gpio);
510 reg = bank->base;
5eb3bb9c 511 reg += OMAP24XX_GPIO_DEBOUNCE_EN;
e031ab23
DB		 512
513 spin_lock_irqsave(&bank->lock, flags);
5eb3bb9c
KH		 514 val = __raw_readl(reg);
515
89db9482 516 if (enable && !(val & l))
5eb3bb9c 517 val |= l;
e031ab23 518 else if (!enable && (val & l))
5eb3bb9c 519 val &= ~l;
89db9482 520 else
e031ab23 521 goto done;
89db9482 522
e031ab23
DB		 523 if (cpu_is_omap34xx()) {
524 if (enable)
525 clk_enable(bank->dbck);
526 else
527 clk_disable(bank->dbck);
528 }
5eb3bb9c
KH		 529
530 __raw_writel(val, reg);
e031ab23
DB		 531done:
532 spin_unlock_irqrestore(&bank->lock, flags);
5eb3bb9c
KH		 533}
534EXPORT_SYMBOL(omap_set_gpio_debounce);
535
536void omap_set_gpio_debounce_time(int gpio, int enc_time)
537{
538 struct gpio_bank *bank;
539 void __iomem *reg;
540
541 if (cpu_class_is_omap1())
542 return;
543
544 bank = get_gpio_bank(gpio);
545 reg = bank->base;
546
547 enc_time &= 0xff;
548 reg += OMAP24XX_GPIO_DEBOUNCE_VAL;
549 __raw_writel(enc_time, reg);
550}
551EXPORT_SYMBOL(omap_set_gpio_debounce_time);
552
5492fb1a 553#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
5eb3bb9c
KH		 554static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio,
555 int trigger)
5e1c5ff4 556{
3ac4fa99 557 void __iomem *base = bank->base;
92105bb7
TL		 558 u32 gpio_bit = 1 << gpio;
559
560 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT0, gpio_bit,
6cab4860 561 trigger & IRQ_TYPE_LEVEL_LOW);
92105bb7 562 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT1, gpio_bit,
6cab4860 563 trigger & IRQ_TYPE_LEVEL_HIGH);
92105bb7 564 MOD_REG_BIT(OMAP24XX_GPIO_RISINGDETECT, gpio_bit,
6cab4860 565 trigger & IRQ_TYPE_EDGE_RISING);
92105bb7 566 MOD_REG_BIT(OMAP24XX_GPIO_FALLINGDETECT, gpio_bit,
6cab4860 567 trigger & IRQ_TYPE_EDGE_FALLING);
5eb3bb9c 568
3ac4fa99
JY		 569 if (likely(!(bank->non_wakeup_gpios & gpio_bit))) {
570 if (trigger != 0)
5eb3bb9c
KH		 571 __raw_writel(1 << gpio, bank->base
572 + OMAP24XX_GPIO_SETWKUENA);
3ac4fa99 573 else
5eb3bb9c
KH		 574 __raw_writel(1 << gpio, bank->base
575 + OMAP24XX_GPIO_CLEARWKUENA);
3ac4fa99
JY		 576 } else {
577 if (trigger != 0)
578 bank->enabled_non_wakeup_gpios |= gpio_bit;
579 else
580 bank->enabled_non_wakeup_gpios &= ~gpio_bit;
581 }
5eb3bb9c 582
b144ff6f
KH		 583 bank->level_mask =
584 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0) |
585 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
92105bb7 586}
3ac4fa99 587#endif
92105bb7
TL		 588
589static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
590{
591 void __iomem *reg = bank->base;
592 u32 l = 0;
5e1c5ff4
TL		 593
594 switch (bank->method) {
e5c56ed3 595#ifdef CONFIG_ARCH_OMAP1
5e1c5ff4
TL		 596 case METHOD_MPUIO:
597 reg += OMAP_MPUIO_GPIO_INT_EDGE;
598 l = __raw_readl(reg);
6cab4860 599 if (trigger & IRQ_TYPE_EDGE_RISING)
5e1c5ff4 600 l |= 1 << gpio;
6cab4860 601 else if (trigger & IRQ_TYPE_EDGE_FALLING)
5e1c5ff4 602 l &= ~(1 << gpio);
92105bb7
TL		 603 else
604 goto bad;
5e1c5ff4 605 break;
e5c56ed3
DB		 606#endif
607#ifdef CONFIG_ARCH_OMAP15XX
5e1c5ff4
TL		 608 case METHOD_GPIO_1510:
609 reg += OMAP1510_GPIO_INT_CONTROL;
610 l = __raw_readl(reg);
6cab4860 611 if (trigger & IRQ_TYPE_EDGE_RISING)
5e1c5ff4 612 l |= 1 << gpio;
6cab4860 613 else if (trigger & IRQ_TYPE_EDGE_FALLING)
5e1c5ff4 614 l &= ~(1 << gpio);
92105bb7
TL		 615 else
616 goto bad;
5e1c5ff4 617 break;
e5c56ed3 618#endif
3ac4fa99 619#ifdef CONFIG_ARCH_OMAP16XX
5e1c5ff4 620 case METHOD_GPIO_1610:
5e1c5ff4
TL		 621 if (gpio & 0x08)
622 reg += OMAP1610_GPIO_EDGE_CTRL2;
623 else
624 reg += OMAP1610_GPIO_EDGE_CTRL1;
625 gpio &= 0x07;
626 l = __raw_readl(reg);
627 l &= ~(3 << (gpio << 1));
6cab4860 628 if (trigger & IRQ_TYPE_EDGE_RISING)
6e60e79a 629 l |= 2 << (gpio << 1);
6cab4860 630 if (trigger & IRQ_TYPE_EDGE_FALLING)
6e60e79a 631 l |= 1 << (gpio << 1);
3ac4fa99
JY		 632 if (trigger)
633 /* Enable wake-up during idle for dynamic tick */
634 __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_SET_WAKEUPENA);
635 else
636 __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA);
5e1c5ff4 637 break;
3ac4fa99
JY		 638#endif
639#ifdef CONFIG_ARCH_OMAP730
5e1c5ff4
TL		 640 case METHOD_GPIO_730:
641 reg += OMAP730_GPIO_INT_CONTROL;
642 l = __raw_readl(reg);
6cab4860 643 if (trigger & IRQ_TYPE_EDGE_RISING)
5e1c5ff4 644 l |= 1 << gpio;
6cab4860 645 else if (trigger & IRQ_TYPE_EDGE_FALLING)
5e1c5ff4 646 l &= ~(1 << gpio);
92105bb7
TL		 647 else
648 goto bad;
649 break;
3ac4fa99 650#endif
56739a69
ZM		 651#ifdef CONFIG_ARCH_OMAP850
652 case METHOD_GPIO_850:
653 reg += OMAP850_GPIO_INT_CONTROL;
654 l = __raw_readl(reg);
655 if (trigger & IRQ_TYPE_EDGE_RISING)
656 l |= 1 << gpio;
657 else if (trigger & IRQ_TYPE_EDGE_FALLING)
658 l &= ~(1 << gpio);
659 else
660 goto bad;
661 break;
662#endif
5492fb1a 663#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
92105bb7 664 case METHOD_GPIO_24XX:
3ac4fa99 665 set_24xx_gpio_triggering(bank, gpio, trigger);
5e1c5ff4 666 break;
3ac4fa99 667#endif
5e1c5ff4 668 default:
92105bb7 669 goto bad;
5e1c5ff4 670 }
92105bb7
TL		 671 __raw_writel(l, reg);
672 return 0;
673bad:
674 return -EINVAL;
5e1c5ff4
TL		 675}
676
92105bb7 677static int gpio_irq_type(unsigned irq, unsigned type)
5e1c5ff4
TL		 678{
679 struct gpio_bank *bank;
92105bb7
TL		 680 unsigned gpio;
681 int retval;
a6472533 682 unsigned long flags;
92105bb7 683
5492fb1a 684 if (!cpu_class_is_omap2() && irq > IH_MPUIO_BASE)
92105bb7
TL		 685 gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
686 else
687 gpio = irq - IH_GPIO_BASE;
5e1c5ff4
TL		 688
689 if (check_gpio(gpio) < 0)
92105bb7
TL		 690 return -EINVAL;
691
e5c56ed3 692 if (type & ~IRQ_TYPE_SENSE_MASK)
6e60e79a 693 return -EINVAL;
e5c56ed3
DB		 694
695 /* OMAP1 allows only only edge triggering */
5492fb1a 696 if (!cpu_class_is_omap2()
e5c56ed3 697 && (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH)))
92105bb7
TL		 698 return -EINVAL;
699
58781016 700 bank = get_irq_chip_data(irq);
a6472533 701 spin_lock_irqsave(&bank->lock, flags);
92105bb7 702 retval = _set_gpio_triggering(bank, get_gpio_index(gpio), type);
b9772a22
DB		 703 if (retval == 0) {
704 irq_desc[irq].status &= ~IRQ_TYPE_SENSE_MASK;
705 irq_desc[irq].status |= type;
706 }
a6472533 707 spin_unlock_irqrestore(&bank->lock, flags);
672e302e
KH		 708
709 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
710 __set_irq_handler_unlocked(irq, handle_level_irq);
711 else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
712 __set_irq_handler_unlocked(irq, handle_edge_irq);
713
92105bb7 714 return retval;
5e1c5ff4
TL		 715}
716
717static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
718{
92105bb7 719 void __iomem *reg = bank->base;
5e1c5ff4
TL		 720
721 switch (bank->method) {
e5c56ed3 722#ifdef CONFIG_ARCH_OMAP1
5e1c5ff4
TL		 723 case METHOD_MPUIO:
724 /* MPUIO irqstatus is reset by reading the status register,
725 * so do nothing here */
726 return;
e5c56ed3
DB		 727#endif
728#ifdef CONFIG_ARCH_OMAP15XX
5e1c5ff4
TL		 729 case METHOD_GPIO_1510:
730 reg += OMAP1510_GPIO_INT_STATUS;
731 break;
e5c56ed3
DB		 732#endif
733#ifdef CONFIG_ARCH_OMAP16XX
5e1c5ff4
TL		 734 case METHOD_GPIO_1610:
735 reg += OMAP1610_GPIO_IRQSTATUS1;
736 break;
e5c56ed3
DB		 737#endif
738#ifdef CONFIG_ARCH_OMAP730
5e1c5ff4
TL		 739 case METHOD_GPIO_730:
740 reg += OMAP730_GPIO_INT_STATUS;
741 break;
e5c56ed3 742#endif
56739a69
ZM		 743#ifdef CONFIG_ARCH_OMAP850
744 case METHOD_GPIO_850:
745 reg += OMAP850_GPIO_INT_STATUS;
746 break;
747#endif
5492fb1a 748#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
92105bb7
TL		 749 case METHOD_GPIO_24XX:
750 reg += OMAP24XX_GPIO_IRQSTATUS1;
751 break;
e5c56ed3 752#endif
5e1c5ff4 753 default:
e5c56ed3 754 WARN_ON(1);
5e1c5ff4
TL		 755 return;
756 }
757 __raw_writel(gpio_mask, reg);
bee7930f
HD		 758
759 /* Workaround for clearing DSP GPIO interrupts to allow retention */
5492fb1a 760#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
bedfd154 761 reg = bank->base + OMAP24XX_GPIO_IRQSTATUS2;
5492fb1a 762 if (cpu_is_omap24xx() || cpu_is_omap34xx())
bedfd154
RQ		 763 __raw_writel(gpio_mask, reg);
764
765 /* Flush posted write for the irq status to avoid spurious interrupts */
766 __raw_readl(reg);
5492fb1a 767#endif
5e1c5ff4
TL		 768}
769
770static inline void _clear_gpio_irqstatus(struct gpio_bank *bank, int gpio)
771{
772 _clear_gpio_irqbank(bank, 1 << get_gpio_index(gpio));
773}
774
ea6dedd7
ID		 775static u32 _get_gpio_irqbank_mask(struct gpio_bank *bank)
776{
777 void __iomem *reg = bank->base;
99c47707
ID		 778 int inv = 0;
779 u32 l;
780 u32 mask;
ea6dedd7
ID		 781
782 switch (bank->method) {
e5c56ed3 783#ifdef CONFIG_ARCH_OMAP1
ea6dedd7
ID		 784 case METHOD_MPUIO:
785 reg += OMAP_MPUIO_GPIO_MASKIT;
99c47707
ID		 786 mask = 0xffff;
787 inv = 1;
ea6dedd7 788 break;
e5c56ed3
DB		 789#endif
790#ifdef CONFIG_ARCH_OMAP15XX
ea6dedd7
ID		 791 case METHOD_GPIO_1510:
792 reg += OMAP1510_GPIO_INT_MASK;
99c47707
ID		 793 mask = 0xffff;
794 inv = 1;
ea6dedd7 795 break;
e5c56ed3
DB		 796#endif
797#ifdef CONFIG_ARCH_OMAP16XX
ea6dedd7
ID		 798 case METHOD_GPIO_1610:
799 reg += OMAP1610_GPIO_IRQENABLE1;
99c47707 800 mask = 0xffff;
ea6dedd7 801 break;
e5c56ed3
DB		 802#endif
803#ifdef CONFIG_ARCH_OMAP730
ea6dedd7
ID		 804 case METHOD_GPIO_730:
805 reg += OMAP730_GPIO_INT_MASK;
99c47707
ID		 806 mask = 0xffffffff;
807 inv = 1;
ea6dedd7 808 break;
e5c56ed3 809#endif
56739a69
ZM		 810#ifdef CONFIG_ARCH_OMAP850
811 case METHOD_GPIO_850:
812 reg += OMAP850_GPIO_INT_MASK;
813 mask = 0xffffffff;
814 inv = 1;
815 break;
816#endif
5492fb1a 817#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
ea6dedd7
ID		 818 case METHOD_GPIO_24XX:
819 reg += OMAP24XX_GPIO_IRQENABLE1;
99c47707 820 mask = 0xffffffff;
ea6dedd7 821 break;
e5c56ed3 822#endif
ea6dedd7 823 default:
e5c56ed3 824 WARN_ON(1);
ea6dedd7
ID		 825 return 0;
826 }
827
99c47707
ID		 828 l = __raw_readl(reg);
829 if (inv)
830 l = ~l;
831 l &= mask;
832 return l;
ea6dedd7
ID		 833}
834
5e1c5ff4
TL		 835static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask, int enable)
836{
92105bb7 837 void __iomem *reg = bank->base;
5e1c5ff4
TL		 838 u32 l;
839
840 switch (bank->method) {
e5c56ed3 841#ifdef CONFIG_ARCH_OMAP1
5e1c5ff4
TL		 842 case METHOD_MPUIO:
843 reg += OMAP_MPUIO_GPIO_MASKIT;
844 l = __raw_readl(reg);
845 if (enable)
846 l &= ~(gpio_mask);
847 else
848 l |= gpio_mask;
849 break;
e5c56ed3
DB		 850#endif
851#ifdef CONFIG_ARCH_OMAP15XX
5e1c5ff4
TL		 852 case METHOD_GPIO_1510:
853 reg += OMAP1510_GPIO_INT_MASK;
854 l = __raw_readl(reg);
855 if (enable)
856 l &= ~(gpio_mask);
857 else
858 l |= gpio_mask;
859 break;
e5c56ed3
DB		 860#endif
861#ifdef CONFIG_ARCH_OMAP16XX
5e1c5ff4
TL		 862 case METHOD_GPIO_1610:
863 if (enable)
864 reg += OMAP1610_GPIO_SET_IRQENABLE1;
865 else
866 reg += OMAP1610_GPIO_CLEAR_IRQENABLE1;
867 l = gpio_mask;
868 break;
e5c56ed3
DB		 869#endif
870#ifdef CONFIG_ARCH_OMAP730
5e1c5ff4
TL		 871 case METHOD_GPIO_730:
872 reg += OMAP730_GPIO_INT_MASK;
873 l = __raw_readl(reg);
874 if (enable)
875 l &= ~(gpio_mask);
876 else
877 l |= gpio_mask;
878 break;
e5c56ed3 879#endif
56739a69
ZM		 880#ifdef CONFIG_ARCH_OMAP850
881 case METHOD_GPIO_850:
882 reg += OMAP850_GPIO_INT_MASK;
883 l = __raw_readl(reg);
884 if (enable)
885 l &= ~(gpio_mask);
886 else
887 l |= gpio_mask;
888 break;
889#endif
5492fb1a 890#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
92105bb7
TL		 891 case METHOD_GPIO_24XX:
892 if (enable)
893 reg += OMAP24XX_GPIO_SETIRQENABLE1;
894 else
895 reg += OMAP24XX_GPIO_CLEARIRQENABLE1;
896 l = gpio_mask;
897 break;
e5c56ed3 898#endif
5e1c5ff4 899 default:
e5c56ed3 900 WARN_ON(1);
5e1c5ff4
TL		 901 return;
902 }
903 __raw_writel(l, reg);
904}
905
906static inline void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int enable)
907{
908 _enable_gpio_irqbank(bank, 1 << get_gpio_index(gpio), enable);
909}
910
92105bb7
TL		 911/*
912 * Note that ENAWAKEUP needs to be enabled in GPIO_SYSCONFIG register.
913 * 1510 does not seem to have a wake-up register. If JTAG is connected
914 * to the target, system will wake up always on GPIO events. While
915 * system is running all registered GPIO interrupts need to have wake-up
916 * enabled. When system is suspended, only selected GPIO interrupts need
917 * to have wake-up enabled.
918 */
919static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable)
920{
a6472533
DB		 921 unsigned long flags;
922
92105bb7 923 switch (bank->method) {
3ac4fa99 924#ifdef CONFIG_ARCH_OMAP16XX
11a78b79 925 case METHOD_MPUIO:
92105bb7 926 case METHOD_GPIO_1610:
a6472533 927 spin_lock_irqsave(&bank->lock, flags);
b3bb4f68 928 if (enable)
92105bb7 929 bank->suspend_wakeup |= (1 << gpio);
b3bb4f68 930 else
92105bb7 931 bank->suspend_wakeup &= ~(1 << gpio);
a6472533 932 spin_unlock_irqrestore(&bank->lock, flags);
92105bb7 933 return 0;
3ac4fa99 934#endif
5492fb1a 935#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
3ac4fa99 936 case METHOD_GPIO_24XX:
11a78b79
DB		 937 if (bank->non_wakeup_gpios & (1 << gpio)) {
938 printk(KERN_ERR "Unable to modify wakeup on "
939 "non-wakeup GPIO%d\n",
940 (bank - gpio_bank) * 32 + gpio);
941 return -EINVAL;
942 }
a6472533 943 spin_lock_irqsave(&bank->lock, flags);
b3bb4f68 944 if (enable)
3ac4fa99 945 bank->suspend_wakeup |= (1 << gpio);
b3bb4f68 946 else
3ac4fa99 947 bank->suspend_wakeup &= ~(1 << gpio);
a6472533 948 spin_unlock_irqrestore(&bank->lock, flags);
3ac4fa99
JY		 949 return 0;
950#endif
92105bb7
TL		 951 default:
952 printk(KERN_ERR "Can't enable GPIO wakeup for method %i\n",
953 bank->method);
954 return -EINVAL;
955 }
956}
957
4196dd6b
TL		 958static void _reset_gpio(struct gpio_bank *bank, int gpio)
959{
960 _set_gpio_direction(bank, get_gpio_index(gpio), 1);
961 _set_gpio_irqenable(bank, gpio, 0);
962 _clear_gpio_irqstatus(bank, gpio);
6cab4860 963 _set_gpio_triggering(bank, get_gpio_index(gpio), IRQ_TYPE_NONE);
4196dd6b
TL		 964}
965
92105bb7
TL		 966/* Use disable_irq_wake() and enable_irq_wake() functions from drivers */
967static int gpio_wake_enable(unsigned int irq, unsigned int enable)
968{
969 unsigned int gpio = irq - IH_GPIO_BASE;
970 struct gpio_bank *bank;
971 int retval;
972
973 if (check_gpio(gpio) < 0)
974 return -ENODEV;
58781016 975 bank = get_irq_chip_data(irq);
92105bb7 976 retval = _set_gpio_wakeup(bank, get_gpio_index(gpio), enable);
92105bb7
TL		 977
978 return retval;
979}
980
3ff164e1 981static int omap_gpio_request(struct gpio_chip *chip, unsigned offset)
5e1c5ff4 982{
3ff164e1 983 struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
a6472533 984 unsigned long flags;
52e31344 985
a6472533 986 spin_lock_irqsave(&bank->lock, flags);
92105bb7 987
4196dd6b
TL		 988 /* Set trigger to none. You need to enable the desired trigger with
989 * request_irq() or set_irq_type().
990 */
3ff164e1 991 _set_gpio_triggering(bank, offset, IRQ_TYPE_NONE);
92105bb7 992
1a8bfa1e 993#ifdef CONFIG_ARCH_OMAP15XX
5e1c5ff4 994 if (bank->method == METHOD_GPIO_1510) {
92105bb7 995 void __iomem *reg;
5e1c5ff4 996
92105bb7 997 /* Claim the pin for MPU */
5e1c5ff4 998 reg = bank->base + OMAP1510_GPIO_PIN_CONTROL;
3ff164e1 999 __raw_writel(__raw_readl(reg) | (1 << offset), reg);
5e1c5ff4
TL		 1000 }
1001#endif
a6472533 1002 spin_unlock_irqrestore(&bank->lock, flags);
5e1c5ff4
TL		 1003
1004 return 0;
1005}
1006
3ff164e1 1007static void omap_gpio_free(struct gpio_chip *chip, unsigned offset)
5e1c5ff4 1008{
3ff164e1 1009 struct gpio_bank *bank = container_of(chip, struct gpio_bank, chip);
a6472533 1010 unsigned long flags;
5e1c5ff4 1011
a6472533 1012 spin_lock_irqsave(&bank->lock, flags);
92105bb7
TL		 1013#ifdef CONFIG_ARCH_OMAP16XX
1014 if (bank->method == METHOD_GPIO_1610) {
1015 /* Disable wake-up during idle for dynamic tick */
1016 void __iomem *reg = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
3ff164e1 1017 __raw_writel(1 << offset, reg);
92105bb7
TL		 1018 }
1019#endif
5492fb1a 1020#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
92105bb7
TL		 1021 if (bank->method == METHOD_GPIO_24XX) {
1022 /* Disable wake-up during idle for dynamic tick */
1023 void __iomem *reg = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
3ff164e1 1024 __raw_writel(1 << offset, reg);
92105bb7
TL		 1025 }
1026#endif
3ff164e1 1027 _reset_gpio(bank, bank->chip.base + offset);
a6472533 1028 spin_unlock_irqrestore(&bank->lock, flags);
5e1c5ff4
TL		 1029}
1030
1031/*
1032 * We need to unmask the GPIO bank interrupt as soon as possible to
1033 * avoid missing GPIO interrupts for other lines in the bank.
1034 * Then we need to mask-read-clear-unmask the triggered GPIO lines
1035 * in the bank to avoid missing nested interrupts for a GPIO line.
1036 * If we wait to unmask individual GPIO lines in the bank after the
1037 * line's interrupt handler has been run, we may miss some nested
1038 * interrupts.
1039 */
10dd5ce2 1040static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
5e1c5ff4 1041{
92105bb7 1042 void __iomem *isr_reg = NULL;
5e1c5ff4
TL		 1043 u32 isr;
1044 unsigned int gpio_irq;
1045 struct gpio_bank *bank;
ea6dedd7
ID		 1046 u32 retrigger = 0;
1047 int unmasked = 0;
5e1c5ff4
TL		 1048
1049 desc->chip->ack(irq);
1050
418ca1f0 1051 bank = get_irq_data(irq);
e5c56ed3 1052#ifdef CONFIG_ARCH_OMAP1
5e1c5ff4
TL		 1053 if (bank->method == METHOD_MPUIO)
1054 isr_reg = bank->base + OMAP_MPUIO_GPIO_INT;
e5c56ed3 1055#endif
1a8bfa1e 1056#ifdef CONFIG_ARCH_OMAP15XX
5e1c5ff4
TL		 1057 if (bank->method == METHOD_GPIO_1510)
1058 isr_reg = bank->base + OMAP1510_GPIO_INT_STATUS;
1059#endif
1060#if defined(CONFIG_ARCH_OMAP16XX)
1061 if (bank->method == METHOD_GPIO_1610)
1062 isr_reg = bank->base + OMAP1610_GPIO_IRQSTATUS1;
1063#endif
1064#ifdef CONFIG_ARCH_OMAP730
1065 if (bank->method == METHOD_GPIO_730)
1066 isr_reg = bank->base + OMAP730_GPIO_INT_STATUS;
1067#endif
56739a69
ZM		 1068#ifdef CONFIG_ARCH_OMAP850
1069 if (bank->method == METHOD_GPIO_850)
1070 isr_reg = bank->base + OMAP850_GPIO_INT_STATUS;
1071#endif
5492fb1a 1072#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
92105bb7
TL		 1073 if (bank->method == METHOD_GPIO_24XX)
1074 isr_reg = bank->base + OMAP24XX_GPIO_IRQSTATUS1;
1075#endif
92105bb7 1076 while(1) {
6e60e79a 1077 u32 isr_saved, level_mask = 0;
ea6dedd7 1078 u32 enabled;
6e60e79a 1079
ea6dedd7
ID		 1080 enabled = _get_gpio_irqbank_mask(bank);
1081 isr_saved = isr = __raw_readl(isr_reg) & enabled;
6e60e79a
TL		 1082
1083 if (cpu_is_omap15xx() && (bank->method == METHOD_MPUIO))
1084 isr &= 0x0000ffff;
1085
5492fb1a 1086 if (cpu_class_is_omap2()) {
b144ff6f 1087 level_mask = bank->level_mask & enabled;
ea6dedd7 1088 }
6e60e79a
TL		 1089
1090 /* clear edge sensitive interrupts before handler(s) are
1091 called so that we don't miss any interrupt occurred while
1092 executing them */
1093 _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 0);
1094 _clear_gpio_irqbank(bank, isr_saved & ~level_mask);
1095 _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 1);
1096
1097 /* if there is only edge sensitive GPIO pin interrupts
1098 configured, we could unmask GPIO bank interrupt immediately */
ea6dedd7
ID		 1099 if (!level_mask && !unmasked) {
1100 unmasked = 1;
6e60e79a 1101 desc->chip->unmask(irq);
ea6dedd7 1102 }
92105bb7 1103
ea6dedd7
ID		 1104 isr |= retrigger;
1105 retrigger = 0;
92105bb7
TL		 1106 if (!isr)
1107 break;
1108
1109 gpio_irq = bank->virtual_irq_start;
1110 for (; isr != 0; isr >>= 1, gpio_irq++) {
92105bb7
TL		 1111 if (!(isr & 1))
1112 continue;
29454dde 1113
d8aa0251 1114 generic_handle_irq(gpio_irq);
92105bb7 1115 }
1a8bfa1e 1116 }
ea6dedd7
ID		 1117 /* if bank has any level sensitive GPIO pin interrupt
1118 configured, we must unmask the bank interrupt only after
1119 handler(s) are executed in order to avoid spurious bank
1120 interrupt */
1121 if (!unmasked)
1122 desc->chip->unmask(irq);
1123
5e1c5ff4
TL		 1124}
1125
4196dd6b
TL		 1126static void gpio_irq_shutdown(unsigned int irq)
1127{
1128 unsigned int gpio = irq - IH_GPIO_BASE;
58781016 1129 struct gpio_bank *bank = get_irq_chip_data(irq);
4196dd6b
TL		 1130
1131 _reset_gpio(bank, gpio);
1132}
1133
5e1c5ff4
TL		 1134static void gpio_ack_irq(unsigned int irq)
1135{
1136 unsigned int gpio = irq - IH_GPIO_BASE;
58781016 1137 struct gpio_bank *bank = get_irq_chip_data(irq);
5e1c5ff4
TL		 1138
1139 _clear_gpio_irqstatus(bank, gpio);
1140}
1141
1142static void gpio_mask_irq(unsigned int irq)
1143{
1144 unsigned int gpio = irq - IH_GPIO_BASE;
58781016 1145 struct gpio_bank *bank = get_irq_chip_data(irq);
5e1c5ff4
TL		 1146
1147 _set_gpio_irqenable(bank, gpio, 0);
1148}
1149
1150static void gpio_unmask_irq(unsigned int irq)
1151{
1152 unsigned int gpio = irq - IH_GPIO_BASE;
58781016 1153 struct gpio_bank *bank = get_irq_chip_data(irq);
b144ff6f
KH		 1154 unsigned int irq_mask = 1 << get_gpio_index(gpio);
1155
1156 /* For level-triggered GPIOs, the clearing must be done after
1157 * the HW source is cleared, thus after the handler has run */
1158 if (bank->level_mask & irq_mask) {
1159 _set_gpio_irqenable(bank, gpio, 0);
1160 _clear_gpio_irqstatus(bank, gpio);
1161 }
5e1c5ff4 1162
4de8c75b 1163 _set_gpio_irqenable(bank, gpio, 1);
5e1c5ff4
TL		 1164}
1165
e5c56ed3
DB		 1166static struct irq_chip gpio_irq_chip = {
1167 .name = "GPIO",
1168 .shutdown = gpio_irq_shutdown,
1169 .ack = gpio_ack_irq,
1170 .mask = gpio_mask_irq,
1171 .unmask = gpio_unmask_irq,
1172 .set_type = gpio_irq_type,
1173 .set_wake = gpio_wake_enable,
1174};
1175
1176/*---------------------------------------------------------------------*/
1177
1178#ifdef CONFIG_ARCH_OMAP1
1179
1180/* MPUIO uses the always-on 32k clock */
1181
5e1c5ff4
TL		 1182static void mpuio_ack_irq(unsigned int irq)
1183{
1184 /* The ISR is reset automatically, so do nothing here. */
1185}
1186
1187static void mpuio_mask_irq(unsigned int irq)
1188{
1189 unsigned int gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
58781016 1190 struct gpio_bank *bank = get_irq_chip_data(irq);
5e1c5ff4
TL		 1191
1192 _set_gpio_irqenable(bank, gpio, 0);
1193}
1194
1195static void mpuio_unmask_irq(unsigned int irq)
1196{
1197 unsigned int gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
58781016 1198 struct gpio_bank *bank = get_irq_chip_data(irq);
5e1c5ff4
TL		 1199
1200 _set_gpio_irqenable(bank, gpio, 1);
1201}
1202
e5c56ed3
DB		 1203static struct irq_chip mpuio_irq_chip = {
1204 .name = "MPUIO",
1205 .ack = mpuio_ack_irq,
1206 .mask = mpuio_mask_irq,
1207 .unmask = mpuio_unmask_irq,
92105bb7 1208 .set_type = gpio_irq_type,
11a78b79
DB		 1209#ifdef CONFIG_ARCH_OMAP16XX
1210 /* REVISIT: assuming only 16xx supports MPUIO wake events */
1211 .set_wake = gpio_wake_enable,
1212#endif
5e1c5ff4
TL		 1213};
1214
e5c56ed3
DB		 1215
1216#define bank_is_mpuio(bank) ((bank)->method == METHOD_MPUIO)
1217
11a78b79
DB		 1218
1219#ifdef CONFIG_ARCH_OMAP16XX
1220
1221#include <linux/platform_device.h>
1222
1223static int omap_mpuio_suspend_late(struct platform_device *pdev, pm_message_t mesg)
1224{
1225 struct gpio_bank *bank = platform_get_drvdata(pdev);
1226 void __iomem *mask_reg = bank->base + OMAP_MPUIO_GPIO_MASKIT;
a6472533 1227 unsigned long flags;
11a78b79 1228
a6472533 1229 spin_lock_irqsave(&bank->lock, flags);
11a78b79
DB		 1230 bank->saved_wakeup = __raw_readl(mask_reg);
1231 __raw_writel(0xffff & ~bank->suspend_wakeup, mask_reg);
a6472533 1232 spin_unlock_irqrestore(&bank->lock, flags);
11a78b79
DB		 1233
1234 return 0;
1235}
1236
1237static int omap_mpuio_resume_early(struct platform_device *pdev)
1238{
1239 struct gpio_bank *bank = platform_get_drvdata(pdev);
1240 void __iomem *mask_reg = bank->base + OMAP_MPUIO_GPIO_MASKIT;
a6472533 1241 unsigned long flags;
11a78b79 1242
a6472533 1243 spin_lock_irqsave(&bank->lock, flags);
11a78b79 1244 __raw_writel(bank->saved_wakeup, mask_reg);
a6472533 1245 spin_unlock_irqrestore(&bank->lock, flags);
11a78b79
DB		 1246
1247 return 0;
1248}
1249
1250/* use platform_driver for this, now that there's no longer any
1251 * point to sys_device (other than not disturbing old code).
1252 */
1253static struct platform_driver omap_mpuio_driver = {
1254 .suspend_late = omap_mpuio_suspend_late,
1255 .resume_early = omap_mpuio_resume_early,
1256 .driver = {
1257 .name = "mpuio",
1258 },
1259};
1260
1261static struct platform_device omap_mpuio_device = {
1262 .name = "mpuio",
1263 .id = -1,
1264 .dev = {
1265 .driver = &omap_mpuio_driver.driver,
1266 }
1267 /* could list the /proc/iomem resources */
1268};
1269
1270static inline void mpuio_init(void)
1271{
fcf126d8
DB		 1272 platform_set_drvdata(&omap_mpuio_device, &gpio_bank_1610[0]);
1273
11a78b79
DB		 1274 if (platform_driver_register(&omap_mpuio_driver) == 0)
1275 (void) platform_device_register(&omap_mpuio_device);
1276}
1277
1278#else
1279static inline void mpuio_init(void) {}
1280#endif /* 16xx */
1281
e5c56ed3
DB		 1282#else
1283
1284extern struct irq_chip mpuio_irq_chip;
1285
1286#define bank_is_mpuio(bank) 0
11a78b79 1287static inline void mpuio_init(void) {}
e5c56ed3
DB		 1288
1289#endif
1290
1291/*---------------------------------------------------------------------*/
5e1c5ff4 1292
52e31344
DB		 1293/* REVISIT these are stupid implementations! replace by ones that
1294 * don't switch on METHOD_* and which mostly avoid spinlocks
1295 */
1296
1297static int gpio_input(struct gpio_chip *chip, unsigned offset)
1298{
1299 struct gpio_bank *bank;
1300 unsigned long flags;
1301
1302 bank = container_of(chip, struct gpio_bank, chip);
1303 spin_lock_irqsave(&bank->lock, flags);
1304 _set_gpio_direction(bank, offset, 1);
1305 spin_unlock_irqrestore(&bank->lock, flags);
1306 return 0;
1307}
1308
1309static int gpio_get(struct gpio_chip *chip, unsigned offset)
1310{
0b84b5ca 1311 return __omap_get_gpio_datain(chip->base + offset);
52e31344
DB		 1312}
1313
1314static int gpio_output(struct gpio_chip *chip, unsigned offset, int value)
1315{
1316 struct gpio_bank *bank;
1317 unsigned long flags;
1318
1319 bank = container_of(chip, struct gpio_bank, chip);
1320 spin_lock_irqsave(&bank->lock, flags);
1321 _set_gpio_dataout(bank, offset, value);
1322 _set_gpio_direction(bank, offset, 0);
1323 spin_unlock_irqrestore(&bank->lock, flags);
1324 return 0;
1325}
1326
1327static void gpio_set(struct gpio_chip *chip, unsigned offset, int value)
1328{
1329 struct gpio_bank *bank;
1330 unsigned long flags;
1331
1332 bank = container_of(chip, struct gpio_bank, chip);
1333 spin_lock_irqsave(&bank->lock, flags);
1334 _set_gpio_dataout(bank, offset, value);
1335 spin_unlock_irqrestore(&bank->lock, flags);
1336}
1337
a007b709
DB		 1338static int gpio_2irq(struct gpio_chip *chip, unsigned offset)
1339{
1340 struct gpio_bank *bank;
1341
1342 bank = container_of(chip, struct gpio_bank, chip);
1343 return bank->virtual_irq_start + offset;
1344}
1345
52e31344
DB		 1346/*---------------------------------------------------------------------*/
1347
1a8bfa1e 1348static int initialized;
5492fb1a 1349#if !defined(CONFIG_ARCH_OMAP3)
1a8bfa1e 1350static struct clk * gpio_ick;
5492fb1a
SMK		 1351#endif
1352
1353#if defined(CONFIG_ARCH_OMAP2)
1a8bfa1e 1354static struct clk * gpio_fck;
5492fb1a 1355#endif
5e1c5ff4 1356
5492fb1a 1357#if defined(CONFIG_ARCH_OMAP2430)
56a25641
SMK		 1358static struct clk * gpio5_ick;
1359static struct clk * gpio5_fck;
1360#endif
1361
5492fb1a 1362#if defined(CONFIG_ARCH_OMAP3)
5492fb1a
SMK		 1363static struct clk *gpio_iclks[OMAP34XX_NR_GPIOS];
1364#endif
1365
8ba55c5c
DB		 1366/* This lock class tells lockdep that GPIO irqs are in a different
1367 * category than their parents, so it won't report false recursion.
1368 */
1369static struct lock_class_key gpio_lock_class;
1370
5e1c5ff4
TL		 1371static int __init _omap_gpio_init(void)
1372{
1373 int i;
52e31344 1374 int gpio = 0;
5e1c5ff4 1375 struct gpio_bank *bank;
5492fb1a 1376 char clk_name[11];
5e1c5ff4
TL		 1377
1378 initialized = 1;
1379
5492fb1a 1380#if defined(CONFIG_ARCH_OMAP1)
6e60e79a 1381 if (cpu_is_omap15xx()) {
1a8bfa1e
TL		 1382 gpio_ick = clk_get(NULL, "arm_gpio_ck");
1383 if (IS_ERR(gpio_ick))
92105bb7
TL		 1384 printk("Could not get arm_gpio_ck\n");
1385 else
30ff720b 1386 clk_enable(gpio_ick);
1a8bfa1e 1387 }
5492fb1a
SMK		 1388#endif
1389#if defined(CONFIG_ARCH_OMAP2)
1390 if (cpu_class_is_omap2()) {
1a8bfa1e
TL		 1391 gpio_ick = clk_get(NULL, "gpios_ick");
1392 if (IS_ERR(gpio_ick))
1393 printk("Could not get gpios_ick\n");
1394 else
30ff720b 1395 clk_enable(gpio_ick);
1a8bfa1e 1396 gpio_fck = clk_get(NULL, "gpios_fck");
1630b52d 1397 if (IS_ERR(gpio_fck))
1a8bfa1e
TL		 1398 printk("Could not get gpios_fck\n");
1399 else
30ff720b 1400 clk_enable(gpio_fck);
56a25641
SMK		 1401
1402 /*
5492fb1a 1403 * On 2430 & 3430 GPIO 5 uses CORE L4 ICLK
56a25641 1404 */
5492fb1a 1405#if defined(CONFIG_ARCH_OMAP2430)
56a25641
SMK		 1406 if (cpu_is_omap2430()) {
1407 gpio5_ick = clk_get(NULL, "gpio5_ick");
1408 if (IS_ERR(gpio5_ick))
1409 printk("Could not get gpio5_ick\n");
1410 else
1411 clk_enable(gpio5_ick);
1412 gpio5_fck = clk_get(NULL, "gpio5_fck");
1413 if (IS_ERR(gpio5_fck))
1414 printk("Could not get gpio5_fck\n");
1415 else
1416 clk_enable(gpio5_fck);
1417 }
1418#endif
5492fb1a
SMK		 1419 }
1420#endif
1421
1422#if defined(CONFIG_ARCH_OMAP3)
1423 if (cpu_is_omap34xx()) {
1424 for (i = 0; i < OMAP34XX_NR_GPIOS; i++) {
1425 sprintf(clk_name, "gpio%d_ick", i + 1);
1426 gpio_iclks[i] = clk_get(NULL, clk_name);
1427 if (IS_ERR(gpio_iclks[i]))
1428 printk(KERN_ERR "Could not get %s\n", clk_name);
1429 else
1430 clk_enable(gpio_iclks[i]);
5492fb1a
SMK		 1431 }
1432 }
1433#endif
1434
92105bb7 1435
1a8bfa1e 1436#ifdef CONFIG_ARCH_OMAP15XX
6e60e79a 1437 if (cpu_is_omap15xx()) {
5e1c5ff4
TL		 1438 printk(KERN_INFO "OMAP1510 GPIO hardware\n");
1439 gpio_bank_count = 2;
1440 gpio_bank = gpio_bank_1510;
1441 }
1442#endif
1443#if defined(CONFIG_ARCH_OMAP16XX)
1444 if (cpu_is_omap16xx()) {
92105bb7 1445 u32 rev;
5e1c5ff4
TL		 1446
1447 gpio_bank_count = 5;
1448 gpio_bank = gpio_bank_1610;
7c7095aa 1449 rev = __raw_readw(gpio_bank[1].base + OMAP1610_GPIO_REVISION);
5e1c5ff4
TL		 1450 printk(KERN_INFO "OMAP GPIO hardware version %d.%d\n",
1451 (rev >> 4) & 0x0f, rev & 0x0f);
1452 }
1453#endif
1454#ifdef CONFIG_ARCH_OMAP730
1455 if (cpu_is_omap730()) {
1456 printk(KERN_INFO "OMAP730 GPIO hardware\n");
1457 gpio_bank_count = 7;
1458 gpio_bank = gpio_bank_730;
1459 }
92105bb7 1460#endif
56739a69
ZM		 1461#ifdef CONFIG_ARCH_OMAP850
1462 if (cpu_is_omap850()) {
1463 printk(KERN_INFO "OMAP850 GPIO hardware\n");
1464 gpio_bank_count = 7;
1465 gpio_bank = gpio_bank_850;
1466 }
1467#endif
56a25641 1468
92105bb7 1469#ifdef CONFIG_ARCH_OMAP24XX
56a25641 1470 if (cpu_is_omap242x()) {
92105bb7
TL		 1471 int rev;
1472
1473 gpio_bank_count = 4;
56a25641 1474 gpio_bank = gpio_bank_242x;
7c7095aa 1475 rev = __raw_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
56a25641
SMK		 1476 printk(KERN_INFO "OMAP242x GPIO hardware version %d.%d\n",
1477 (rev >> 4) & 0x0f, rev & 0x0f);
1478 }
1479 if (cpu_is_omap243x()) {
1480 int rev;
1481
1482 gpio_bank_count = 5;
1483 gpio_bank = gpio_bank_243x;
7c7095aa 1484 rev = __raw_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
56a25641 1485 printk(KERN_INFO "OMAP243x GPIO hardware version %d.%d\n",
92105bb7
TL		 1486 (rev >> 4) & 0x0f, rev & 0x0f);
1487 }
5492fb1a
SMK		 1488#endif
1489#ifdef CONFIG_ARCH_OMAP34XX
1490 if (cpu_is_omap34xx()) {
1491 int rev;
1492
1493 gpio_bank_count = OMAP34XX_NR_GPIOS;
1494 gpio_bank = gpio_bank_34xx;
7c7095aa 1495 rev = __raw_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
5492fb1a
SMK		 1496 printk(KERN_INFO "OMAP34xx GPIO hardware version %d.%d\n",
1497 (rev >> 4) & 0x0f, rev & 0x0f);
1498 }
5e1c5ff4
TL		 1499#endif
1500 for (i = 0; i < gpio_bank_count; i++) {
1501 int j, gpio_count = 16;
1502
1503 bank = &gpio_bank[i];
5e1c5ff4 1504 spin_lock_init(&bank->lock);
e5c56ed3 1505 if (bank_is_mpuio(bank))
7c7095aa 1506 __raw_writew(0xffff, bank->base + OMAP_MPUIO_GPIO_MASKIT);
d11ac979 1507 if (cpu_is_omap15xx() && bank->method == METHOD_GPIO_1510) {
5e1c5ff4
TL		 1508 __raw_writew(0xffff, bank->base + OMAP1510_GPIO_INT_MASK);
1509 __raw_writew(0x0000, bank->base + OMAP1510_GPIO_INT_STATUS);
1510 }
d11ac979 1511 if (cpu_is_omap16xx() && bank->method == METHOD_GPIO_1610) {
5e1c5ff4
TL		 1512 __raw_writew(0x0000, bank->base + OMAP1610_GPIO_IRQENABLE1);
1513 __raw_writew(0xffff, bank->base + OMAP1610_GPIO_IRQSTATUS1);
92105bb7 1514 __raw_writew(0x0014, bank->base + OMAP1610_GPIO_SYSCONFIG);
5e1c5ff4 1515 }
56739a69 1516 if (cpu_is_omap7xx() && bank->method == METHOD_GPIO_730) {
5e1c5ff4
TL		 1517 __raw_writel(0xffffffff, bank->base + OMAP730_GPIO_INT_MASK);
1518 __raw_writel(0x00000000, bank->base + OMAP730_GPIO_INT_STATUS);
1519
1520 gpio_count = 32; /* 730 has 32-bit GPIOs */
1521 }
d11ac979 1522
5492fb1a 1523#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
92105bb7 1524 if (bank->method == METHOD_GPIO_24XX) {
3ac4fa99
JY		 1525 static const u32 non_wakeup_gpios[] = {
1526 0xe203ffc0, 0x08700040
1527 };
1528
92105bb7
TL		 1529 __raw_writel(0x00000000, bank->base + OMAP24XX_GPIO_IRQENABLE1);
1530 __raw_writel(0xffffffff, bank->base + OMAP24XX_GPIO_IRQSTATUS1);
14f1c3bf
JY		 1531 __raw_writew(0x0015, bank->base + OMAP24XX_GPIO_SYSCONFIG);
1532
1533 /* Initialize interface clock ungated, module enabled */
1534 __raw_writel(0, bank->base + OMAP24XX_GPIO_CTRL);
3ac4fa99
JY		 1535 if (i < ARRAY_SIZE(non_wakeup_gpios))
1536 bank->non_wakeup_gpios = non_wakeup_gpios[i];
92105bb7
TL		 1537 gpio_count = 32;
1538 }
5e1c5ff4 1539#endif
52e31344
DB		 1540
1541 /* REVISIT eventually switch from OMAP-specific gpio structs
1542 * over to the generic ones
1543 */
3ff164e1
JN		 1544 bank->chip.request = omap_gpio_request;
1545 bank->chip.free = omap_gpio_free;
52e31344
DB		 1546 bank->chip.direction_input = gpio_input;
1547 bank->chip.get = gpio_get;
1548 bank->chip.direction_output = gpio_output;
1549 bank->chip.set = gpio_set;
a007b709 1550 bank->chip.to_irq = gpio_2irq;
52e31344
DB		 1551 if (bank_is_mpuio(bank)) {
1552 bank->chip.label = "mpuio";
69114a47 1553#ifdef CONFIG_ARCH_OMAP16XX
d8f388d8
DB		 1554 bank->chip.dev = &omap_mpuio_device.dev;
1555#endif
52e31344
DB		 1556 bank->chip.base = OMAP_MPUIO(0);
1557 } else {
1558 bank->chip.label = "gpio";
1559 bank->chip.base = gpio;
1560 gpio += gpio_count;
1561 }
1562 bank->chip.ngpio = gpio_count;
1563
1564 gpiochip_add(&bank->chip);
1565
5e1c5ff4
TL		 1566 for (j = bank->virtual_irq_start;
1567 j < bank->virtual_irq_start + gpio_count; j++) {
8ba55c5c 1568 lockdep_set_class(&irq_desc[j].lock, &gpio_lock_class);
58781016 1569 set_irq_chip_data(j, bank);
e5c56ed3 1570 if (bank_is_mpuio(bank))
5e1c5ff4
TL		 1571 set_irq_chip(j, &mpuio_irq_chip);
1572 else
1573 set_irq_chip(j, &gpio_irq_chip);
10dd5ce2 1574 set_irq_handler(j, handle_simple_irq);
5e1c5ff4
TL		 1575 set_irq_flags(j, IRQF_VALID);
1576 }
1577 set_irq_chained_handler(bank->irq, gpio_irq_handler);
1578 set_irq_data(bank->irq, bank);
89db9482
JH		 1579
1580 if (cpu_is_omap34xx()) {
1581 sprintf(clk_name, "gpio%d_dbck", i + 1);
1582 bank->dbck = clk_get(NULL, clk_name);
1583 if (IS_ERR(bank->dbck))
1584 printk(KERN_ERR "Could not get %s\n", clk_name);
1585 }
5e1c5ff4
TL		 1586 }
1587
1588 /* Enable system clock for GPIO module.
1589 * The CAM_CLK_CTRL *is* really the right place. */
92105bb7 1590 if (cpu_is_omap16xx())
5e1c5ff4
TL		 1591 omap_writel(omap_readl(ULPD_CAM_CLK_CTRL) | 0x04, ULPD_CAM_CLK_CTRL);
1592
14f1c3bf
JY		 1593 /* Enable autoidle for the OCP interface */
1594 if (cpu_is_omap24xx())
1595 omap_writel(1 << 0, 0x48019010);
5492fb1a
SMK		 1596 if (cpu_is_omap34xx())
1597 omap_writel(1 << 0, 0x48306814);
d11ac979 1598
5e1c5ff4
TL		 1599 return 0;
1600}
1601
5492fb1a 1602#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
92105bb7
TL		 1603static int omap_gpio_suspend(struct sys_device *dev, pm_message_t mesg)
1604{
1605 int i;
1606
5492fb1a 1607 if (!cpu_class_is_omap2() && !cpu_is_omap16xx())
92105bb7
TL		 1608 return 0;
1609
1610 for (i = 0; i < gpio_bank_count; i++) {
1611 struct gpio_bank *bank = &gpio_bank[i];
1612 void __iomem *wake_status;
1613 void __iomem *wake_clear;
1614 void __iomem *wake_set;
a6472533 1615 unsigned long flags;
92105bb7
TL		 1616
1617 switch (bank->method) {
e5c56ed3 1618#ifdef CONFIG_ARCH_OMAP16XX
92105bb7
TL		 1619 case METHOD_GPIO_1610:
1620 wake_status = bank->base + OMAP1610_GPIO_WAKEUPENABLE;
1621 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1622 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1623 break;
e5c56ed3 1624#endif
5492fb1a 1625#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
92105bb7 1626 case METHOD_GPIO_24XX:
723fdb78 1627 wake_status = bank->base + OMAP24XX_GPIO_WAKE_EN;
92105bb7
TL		 1628 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1629 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
1630 break;
e5c56ed3 1631#endif
92105bb7
TL		 1632 default:
1633 continue;
1634 }
1635
a6472533 1636 spin_lock_irqsave(&bank->lock, flags);
92105bb7
TL		 1637 bank->saved_wakeup = __raw_readl(wake_status);
1638 __raw_writel(0xffffffff, wake_clear);
1639 __raw_writel(bank->suspend_wakeup, wake_set);
a6472533 1640 spin_unlock_irqrestore(&bank->lock, flags);
92105bb7
TL		 1641 }
1642
1643 return 0;
1644}
1645
1646static int omap_gpio_resume(struct sys_device *dev)
1647{
1648 int i;
1649
723fdb78 1650 if (!cpu_class_is_omap2() && !cpu_is_omap16xx())
92105bb7
TL		 1651 return 0;
1652
1653 for (i = 0; i < gpio_bank_count; i++) {
1654 struct gpio_bank *bank = &gpio_bank[i];
1655 void __iomem *wake_clear;
1656 void __iomem *wake_set;
a6472533 1657 unsigned long flags;
92105bb7
TL		 1658
1659 switch (bank->method) {
e5c56ed3 1660#ifdef CONFIG_ARCH_OMAP16XX
92105bb7
TL		 1661 case METHOD_GPIO_1610:
1662 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1663 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1664 break;
e5c56ed3 1665#endif
5492fb1a 1666#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
92105bb7 1667 case METHOD_GPIO_24XX:
0d9356cb
TL		 1668 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1669 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
92105bb7 1670 break;
e5c56ed3 1671#endif
92105bb7
TL		 1672 default:
1673 continue;
1674 }
1675
a6472533 1676 spin_lock_irqsave(&bank->lock, flags);
92105bb7
TL		 1677 __raw_writel(0xffffffff, wake_clear);
1678 __raw_writel(bank->saved_wakeup, wake_set);
a6472533 1679 spin_unlock_irqrestore(&bank->lock, flags);
92105bb7
TL		 1680 }
1681
1682 return 0;
1683}
1684
1685static struct sysdev_class omap_gpio_sysclass = {
af5ca3f4 1686 .name = "gpio",
92105bb7
TL		 1687 .suspend = omap_gpio_suspend,
1688 .resume = omap_gpio_resume,
1689};
1690
1691static struct sys_device omap_gpio_device = {
1692 .id = 0,
1693 .cls = &omap_gpio_sysclass,
1694};
3ac4fa99
JY		 1695
1696#endif
1697
5492fb1a 1698#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
3ac4fa99
JY		 1699
1700static int workaround_enabled;
1701
1702void omap2_gpio_prepare_for_retention(void)
1703{
1704 int i, c = 0;
1705
1706 /* Remove triggering for all non-wakeup GPIOs. Otherwise spurious
1707 * IRQs will be generated. See OMAP2420 Errata item 1.101. */
1708 for (i = 0; i < gpio_bank_count; i++) {
1709 struct gpio_bank *bank = &gpio_bank[i];
1710 u32 l1, l2;
1711
1712 if (!(bank->enabled_non_wakeup_gpios))
1713 continue;
5492fb1a 1714#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
3ac4fa99
JY		 1715 bank->saved_datain = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN);
1716 l1 = __raw_readl(bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1717 l2 = __raw_readl(bank->base + OMAP24XX_GPIO_RISINGDETECT);
5492fb1a 1718#endif
3ac4fa99
JY		 1719 bank->saved_fallingdetect = l1;
1720 bank->saved_risingdetect = l2;
1721 l1 &= ~bank->enabled_non_wakeup_gpios;
1722 l2 &= ~bank->enabled_non_wakeup_gpios;
5492fb1a 1723#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
3ac4fa99
JY		 1724 __raw_writel(l1, bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1725 __raw_writel(l2, bank->base + OMAP24XX_GPIO_RISINGDETECT);
5492fb1a 1726#endif
3ac4fa99
JY		 1727 c++;
1728 }
1729 if (!c) {
1730 workaround_enabled = 0;
1731 return;
1732 }
1733 workaround_enabled = 1;
1734}
1735
1736void omap2_gpio_resume_after_retention(void)
1737{
1738 int i;
1739
1740 if (!workaround_enabled)
1741 return;
1742 for (i = 0; i < gpio_bank_count; i++) {
1743 struct gpio_bank *bank = &gpio_bank[i];
1744 u32 l;
1745
1746 if (!(bank->enabled_non_wakeup_gpios))
1747 continue;
5492fb1a 1748#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
3ac4fa99
JY		 1749 __raw_writel(bank->saved_fallingdetect,
1750 bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1751 __raw_writel(bank->saved_risingdetect,
1752 bank->base + OMAP24XX_GPIO_RISINGDETECT);
5492fb1a 1753#endif
3ac4fa99
JY		 1754 /* Check if any of the non-wakeup interrupt GPIOs have changed
1755 * state. If so, generate an IRQ by software. This is
1756 * horribly racy, but it's the best we can do to work around
1757 * this silicon bug. */
5492fb1a 1758#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
3ac4fa99 1759 l = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN);
5492fb1a 1760#endif
3ac4fa99
JY		 1761 l ^= bank->saved_datain;
1762 l &= bank->non_wakeup_gpios;
1763 if (l) {
1764 u32 old0, old1;
5492fb1a 1765#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
3ac4fa99
JY		 1766 old0 = __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0);
1767 old1 = __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
1768 __raw_writel(old0 | l, bank->base + OMAP24XX_GPIO_LEVELDETECT0);
1769 __raw_writel(old1 | l, bank->base + OMAP24XX_GPIO_LEVELDETECT1);
1770 __raw_writel(old0, bank->base + OMAP24XX_GPIO_LEVELDETECT0);
1771 __raw_writel(old1, bank->base + OMAP24XX_GPIO_LEVELDETECT1);
5492fb1a 1772#endif
3ac4fa99
JY		 1773 }
1774 }
1775
1776}
1777
92105bb7
TL		 1778#endif
1779
5e1c5ff4
TL		 1780/*
1781 * This may get called early from board specific init
1a8bfa1e 1782 * for boards that have interrupts routed via FPGA.
5e1c5ff4 1783 */
277d58ef 1784int __init omap_gpio_init(void)
5e1c5ff4
TL		 1785{
1786 if (!initialized)
1787 return _omap_gpio_init();
1788 else
1789 return 0;
1790}
1791
92105bb7
TL		 1792static int __init omap_gpio_sysinit(void)
1793{
1794 int ret = 0;
1795
1796 if (!initialized)
1797 ret = _omap_gpio_init();
1798
11a78b79
DB		 1799 mpuio_init();
1800
5492fb1a
SMK		 1801#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1802 if (cpu_is_omap16xx() || cpu_class_is_omap2()) {
92105bb7
TL		 1803 if (ret == 0) {
1804 ret = sysdev_class_register(&omap_gpio_sysclass);
1805 if (ret == 0)
1806 ret = sysdev_register(&omap_gpio_device);
1807 }
1808 }
1809#endif
1810
1811 return ret;
1812}
1813
92105bb7 1814arch_initcall(omap_gpio_sysinit);
b9772a22
DB		 1815
1816
1817#ifdef CONFIG_DEBUG_FS
1818
1819#include <linux/debugfs.h>
1820#include <linux/seq_file.h>
1821
1822static int gpio_is_input(struct gpio_bank *bank, int mask)
1823{
1824 void __iomem *reg = bank->base;
1825
1826 switch (bank->method) {
1827 case METHOD_MPUIO:
1828 reg += OMAP_MPUIO_IO_CNTL;
1829 break;
1830 case METHOD_GPIO_1510:
1831 reg += OMAP1510_GPIO_DIR_CONTROL;
1832 break;
1833 case METHOD_GPIO_1610:
1834 reg += OMAP1610_GPIO_DIRECTION;
1835 break;
1836 case METHOD_GPIO_730:
1837 reg += OMAP730_GPIO_DIR_CONTROL;
1838 break;
56739a69
ZM		 1839 case METHOD_GPIO_850:
1840 reg += OMAP850_GPIO_DIR_CONTROL;
1841 break;
b9772a22
DB		 1842 case METHOD_GPIO_24XX:
1843 reg += OMAP24XX_GPIO_OE;
1844 break;
1845 }
1846 return __raw_readl(reg) & mask;
1847}
1848
1849
1850static int dbg_gpio_show(struct seq_file *s, void *unused)
1851{
1852 unsigned i, j, gpio;
1853
1854 for (i = 0, gpio = 0; i < gpio_bank_count; i++) {
1855 struct gpio_bank *bank = gpio_bank + i;
1856 unsigned bankwidth = 16;
1857 u32 mask = 1;
1858
e5c56ed3 1859 if (bank_is_mpuio(bank))
b9772a22 1860 gpio = OMAP_MPUIO(0);
56739a69
ZM		 1861 else if (cpu_class_is_omap2() || cpu_is_omap730() ||
1862 cpu_is_omap850())
b9772a22
DB		 1863 bankwidth = 32;
1864
1865 for (j = 0; j < bankwidth; j++, gpio++, mask <<= 1) {
1866 unsigned irq, value, is_in, irqstat;
52e31344 1867 const char *label;
b9772a22 1868
52e31344
DB		 1869 label = gpiochip_is_requested(&bank->chip, j);
1870 if (!label)
b9772a22
DB		 1871 continue;
1872
1873 irq = bank->virtual_irq_start + j;
0b84b5ca 1874 value = gpio_get_value(gpio);
b9772a22
DB		 1875 is_in = gpio_is_input(bank, mask);
1876
e5c56ed3 1877 if (bank_is_mpuio(bank))
52e31344 1878 seq_printf(s, "MPUIO %2d ", j);
b9772a22 1879 else
52e31344 1880 seq_printf(s, "GPIO %3d ", gpio);
21c867f1 1881 seq_printf(s, "(%-20.20s): %s %s",
52e31344 1882 label,
b9772a22
DB		 1883 is_in ? "in " : "out",
1884 value ? "hi" : "lo");
1885
52e31344
DB		 1886/* FIXME for at least omap2, show pullup/pulldown state */
1887
b9772a22 1888 irqstat = irq_desc[irq].status;
3a26e331
TL		 1889#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || \
1890 defined(CONFIG_ARCH_OMAP34XX)
b9772a22
DB		 1891 if (is_in && ((bank->suspend_wakeup & mask)
1892 || irqstat & IRQ_TYPE_SENSE_MASK)) {
1893 char *trigger = NULL;
1894
1895 switch (irqstat & IRQ_TYPE_SENSE_MASK) {
1896 case IRQ_TYPE_EDGE_FALLING:
1897 trigger = "falling";
1898 break;
1899 case IRQ_TYPE_EDGE_RISING:
1900 trigger = "rising";
1901 break;
1902 case IRQ_TYPE_EDGE_BOTH:
1903 trigger = "bothedge";
1904 break;
1905 case IRQ_TYPE_LEVEL_LOW:
1906 trigger = "low";
1907 break;
1908 case IRQ_TYPE_LEVEL_HIGH:
1909 trigger = "high";
1910 break;
1911 case IRQ_TYPE_NONE:
52e31344 1912 trigger = "(?)";
b9772a22
DB		 1913 break;
1914 }
52e31344 1915 seq_printf(s, ", irq-%d %-8s%s",
b9772a22
DB		 1916 irq, trigger,
1917 (bank->suspend_wakeup & mask)
1918 ? " wakeup" : "");
1919 }
3a26e331 1920#endif
b9772a22
DB		 1921 seq_printf(s, "\n");
1922 }
1923
e5c56ed3 1924 if (bank_is_mpuio(bank)) {
b9772a22
DB		 1925 seq_printf(s, "\n");
1926 gpio = 0;
1927 }
1928 }
1929 return 0;
1930}
1931
1932static int dbg_gpio_open(struct inode *inode, struct file *file)
1933{
e5c56ed3 1934 return single_open(file, dbg_gpio_show, &inode->i_private);
b9772a22
DB		 1935}
1936
1937static const struct file_operations debug_fops = {
1938 .open = dbg_gpio_open,
1939 .read = seq_read,
1940 .llseek = seq_lseek,
1941 .release = single_release,
1942};
1943
1944static int __init omap_gpio_debuginit(void)
1945{
e5c56ed3
DB		 1946 (void) debugfs_create_file("omap_gpio", S_IRUGO,
1947 NULL, NULL, &debug_fops);
b9772a22
DB		 1948 return 0;
1949}
1950late_initcall(omap_gpio_debuginit);
1951#endif
Linux kernel - Deliverables
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