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[ARM] Convert asm/io.h to linux/io.h
[deliverable/linux.git] / arch / arm / plat-omap / gpio.c
CommitLineData
5e1c5ff4
TL		 1/*
2 * linux/arch/arm/plat-omap/gpio.c
3 *
4 * Support functions for OMAP GPIO
5 *
92105bb7 6 * Copyright (C) 2003-2005 Nokia Corporation
96de0e25 7 * Written by Juha Yrjölä <juha.yrjola@nokia.com>
5e1c5ff4
TL		 8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
12 */
13
5e1c5ff4
TL		 14#include <linux/init.h>
15#include <linux/module.h>
5e1c5ff4 16#include <linux/interrupt.h>
92105bb7
TL		 17#include <linux/sysdev.h>
18#include <linux/err.h>
f8ce2547 19#include <linux/clk.h>
fced80c7 20#include <linux/io.h>
5e1c5ff4 21
a09e64fb 22#include <mach/hardware.h>
5e1c5ff4 23#include <asm/irq.h>
a09e64fb
RK		 24#include <mach/irqs.h>
25#include <mach/gpio.h>
5e1c5ff4
TL		 26#include <asm/mach/irq.h>
27
5e1c5ff4
TL		 28/*
29 * OMAP1510 GPIO registers
30 */
92105bb7 31#define OMAP1510_GPIO_BASE (void __iomem *)0xfffce000
5e1c5ff4
TL		 32#define OMAP1510_GPIO_DATA_INPUT 0x00
33#define OMAP1510_GPIO_DATA_OUTPUT 0x04
34#define OMAP1510_GPIO_DIR_CONTROL 0x08
35#define OMAP1510_GPIO_INT_CONTROL 0x0c
36#define OMAP1510_GPIO_INT_MASK 0x10
37#define OMAP1510_GPIO_INT_STATUS 0x14
38#define OMAP1510_GPIO_PIN_CONTROL 0x18
39
40#define OMAP1510_IH_GPIO_BASE 64
41
42/*
43 * OMAP1610 specific GPIO registers
44 */
92105bb7
TL		 45#define OMAP1610_GPIO1_BASE (void __iomem *)0xfffbe400
46#define OMAP1610_GPIO2_BASE (void __iomem *)0xfffbec00
47#define OMAP1610_GPIO3_BASE (void __iomem *)0xfffbb400
48#define OMAP1610_GPIO4_BASE (void __iomem *)0xfffbbc00
5e1c5ff4
TL		 49#define OMAP1610_GPIO_REVISION 0x0000
50#define OMAP1610_GPIO_SYSCONFIG 0x0010
51#define OMAP1610_GPIO_SYSSTATUS 0x0014
52#define OMAP1610_GPIO_IRQSTATUS1 0x0018
53#define OMAP1610_GPIO_IRQENABLE1 0x001c
92105bb7 54#define OMAP1610_GPIO_WAKEUPENABLE 0x0028
5e1c5ff4
TL		 55#define OMAP1610_GPIO_DATAIN 0x002c
56#define OMAP1610_GPIO_DATAOUT 0x0030
57#define OMAP1610_GPIO_DIRECTION 0x0034
58#define OMAP1610_GPIO_EDGE_CTRL1 0x0038
59#define OMAP1610_GPIO_EDGE_CTRL2 0x003c
60#define OMAP1610_GPIO_CLEAR_IRQENABLE1 0x009c
92105bb7 61#define OMAP1610_GPIO_CLEAR_WAKEUPENA 0x00a8
5e1c5ff4
TL		 62#define OMAP1610_GPIO_CLEAR_DATAOUT 0x00b0
63#define OMAP1610_GPIO_SET_IRQENABLE1 0x00dc
92105bb7 64#define OMAP1610_GPIO_SET_WAKEUPENA 0x00e8
5e1c5ff4
TL		 65#define OMAP1610_GPIO_SET_DATAOUT 0x00f0
66
67/*
68 * OMAP730 specific GPIO registers
69 */
92105bb7
TL		 70#define OMAP730_GPIO1_BASE (void __iomem *)0xfffbc000
71#define OMAP730_GPIO2_BASE (void __iomem *)0xfffbc800
72#define OMAP730_GPIO3_BASE (void __iomem *)0xfffbd000
73#define OMAP730_GPIO4_BASE (void __iomem *)0xfffbd800
74#define OMAP730_GPIO5_BASE (void __iomem *)0xfffbe000
75#define OMAP730_GPIO6_BASE (void __iomem *)0xfffbe800
5e1c5ff4
TL		 76#define OMAP730_GPIO_DATA_INPUT 0x00
77#define OMAP730_GPIO_DATA_OUTPUT 0x04
78#define OMAP730_GPIO_DIR_CONTROL 0x08
79#define OMAP730_GPIO_INT_CONTROL 0x0c
80#define OMAP730_GPIO_INT_MASK 0x10
81#define OMAP730_GPIO_INT_STATUS 0x14
82
92105bb7
TL		 83/*
84 * omap24xx specific GPIO registers
85 */
56a25641
SMK		 86#define OMAP242X_GPIO1_BASE (void __iomem *)0x48018000
87#define OMAP242X_GPIO2_BASE (void __iomem *)0x4801a000
88#define OMAP242X_GPIO3_BASE (void __iomem *)0x4801c000
89#define OMAP242X_GPIO4_BASE (void __iomem *)0x4801e000
90
91#define OMAP243X_GPIO1_BASE (void __iomem *)0x4900C000
92#define OMAP243X_GPIO2_BASE (void __iomem *)0x4900E000
93#define OMAP243X_GPIO3_BASE (void __iomem *)0x49010000
94#define OMAP243X_GPIO4_BASE (void __iomem *)0x49012000
95#define OMAP243X_GPIO5_BASE (void __iomem *)0x480B6000
96
92105bb7
TL		 97#define OMAP24XX_GPIO_REVISION 0x0000
98#define OMAP24XX_GPIO_SYSCONFIG 0x0010
99#define OMAP24XX_GPIO_SYSSTATUS 0x0014
100#define OMAP24XX_GPIO_IRQSTATUS1 0x0018
bee7930f
HD		 101#define OMAP24XX_GPIO_IRQSTATUS2 0x0028
102#define OMAP24XX_GPIO_IRQENABLE2 0x002c
92105bb7
TL		 103#define OMAP24XX_GPIO_IRQENABLE1 0x001c
104#define OMAP24XX_GPIO_CTRL 0x0030
105#define OMAP24XX_GPIO_OE 0x0034
106#define OMAP24XX_GPIO_DATAIN 0x0038
107#define OMAP24XX_GPIO_DATAOUT 0x003c
108#define OMAP24XX_GPIO_LEVELDETECT0 0x0040
109#define OMAP24XX_GPIO_LEVELDETECT1 0x0044
110#define OMAP24XX_GPIO_RISINGDETECT 0x0048
111#define OMAP24XX_GPIO_FALLINGDETECT 0x004c
5eb3bb9c
KH		 112#define OMAP24XX_GPIO_DEBOUNCE_EN 0x0050
113#define OMAP24XX_GPIO_DEBOUNCE_VAL 0x0054
92105bb7
TL		 114#define OMAP24XX_GPIO_CLEARIRQENABLE1 0x0060
115#define OMAP24XX_GPIO_SETIRQENABLE1 0x0064
116#define OMAP24XX_GPIO_CLEARWKUENA 0x0080
117#define OMAP24XX_GPIO_SETWKUENA 0x0084
118#define OMAP24XX_GPIO_CLEARDATAOUT 0x0090
119#define OMAP24XX_GPIO_SETDATAOUT 0x0094
120
5492fb1a
SMK		 121/*
122 * omap34xx specific GPIO registers
123 */
124
125#define OMAP34XX_GPIO1_BASE (void __iomem *)0x48310000
126#define OMAP34XX_GPIO2_BASE (void __iomem *)0x49050000
127#define OMAP34XX_GPIO3_BASE (void __iomem *)0x49052000
128#define OMAP34XX_GPIO4_BASE (void __iomem *)0x49054000
129#define OMAP34XX_GPIO5_BASE (void __iomem *)0x49056000
130#define OMAP34XX_GPIO6_BASE (void __iomem *)0x49058000
131
132
5e1c5ff4 133struct gpio_bank {
92105bb7 134 void __iomem *base;
5e1c5ff4
TL		 135 u16 irq;
136 u16 virtual_irq_start;
92105bb7 137 int method;
5492fb1a 138#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
92105bb7
TL		 139 u32 suspend_wakeup;
140 u32 saved_wakeup;
3ac4fa99 141#endif
5492fb1a 142#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
3ac4fa99
JY		 143 u32 non_wakeup_gpios;
144 u32 enabled_non_wakeup_gpios;
145
146 u32 saved_datain;
147 u32 saved_fallingdetect;
148 u32 saved_risingdetect;
149#endif
b144ff6f 150 u32 level_mask;
5e1c5ff4 151 spinlock_t lock;
52e31344 152 struct gpio_chip chip;
5e1c5ff4
TL		 153};
154
155#define METHOD_MPUIO 0
156#define METHOD_GPIO_1510 1
157#define METHOD_GPIO_1610 2
158#define METHOD_GPIO_730 3
92105bb7 159#define METHOD_GPIO_24XX 4
5e1c5ff4 160
92105bb7 161#ifdef CONFIG_ARCH_OMAP16XX
5e1c5ff4
TL		 162static struct gpio_bank gpio_bank_1610[5] = {
163 { OMAP_MPUIO_BASE, INT_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO},
164 { OMAP1610_GPIO1_BASE, INT_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_1610 },
165 { OMAP1610_GPIO2_BASE, INT_1610_GPIO_BANK2, IH_GPIO_BASE + 16, METHOD_GPIO_1610 },
166 { OMAP1610_GPIO3_BASE, INT_1610_GPIO_BANK3, IH_GPIO_BASE + 32, METHOD_GPIO_1610 },
167 { OMAP1610_GPIO4_BASE, INT_1610_GPIO_BANK4, IH_GPIO_BASE + 48, METHOD_GPIO_1610 },
168};
169#endif
170
1a8bfa1e 171#ifdef CONFIG_ARCH_OMAP15XX
5e1c5ff4
TL		 172static struct gpio_bank gpio_bank_1510[2] = {
173 { OMAP_MPUIO_BASE, INT_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO },
174 { OMAP1510_GPIO_BASE, INT_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_1510 }
175};
176#endif
177
178#ifdef CONFIG_ARCH_OMAP730
179static struct gpio_bank gpio_bank_730[7] = {
180 { OMAP_MPUIO_BASE, INT_730_MPUIO, IH_MPUIO_BASE, METHOD_MPUIO },
181 { OMAP730_GPIO1_BASE, INT_730_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_730 },
182 { OMAP730_GPIO2_BASE, INT_730_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_730 },
183 { OMAP730_GPIO3_BASE, INT_730_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_730 },
184 { OMAP730_GPIO4_BASE, INT_730_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_730 },
185 { OMAP730_GPIO5_BASE, INT_730_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_730 },
186 { OMAP730_GPIO6_BASE, INT_730_GPIO_BANK6, IH_GPIO_BASE + 160, METHOD_GPIO_730 },
187};
188#endif
189
92105bb7 190#ifdef CONFIG_ARCH_OMAP24XX
56a25641
SMK		 191
192static struct gpio_bank gpio_bank_242x[4] = {
193 { OMAP242X_GPIO1_BASE, INT_24XX_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_24XX },
194 { OMAP242X_GPIO2_BASE, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_24XX },
195 { OMAP242X_GPIO3_BASE, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_24XX },
196 { OMAP242X_GPIO4_BASE, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_24XX },
92105bb7 197};
56a25641
SMK		 198
199static struct gpio_bank gpio_bank_243x[5] = {
200 { OMAP243X_GPIO1_BASE, INT_24XX_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_24XX },
201 { OMAP243X_GPIO2_BASE, INT_24XX_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_24XX },
202 { OMAP243X_GPIO3_BASE, INT_24XX_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_24XX },
203 { OMAP243X_GPIO4_BASE, INT_24XX_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_24XX },
204 { OMAP243X_GPIO5_BASE, INT_24XX_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_24XX },
205};
206
92105bb7
TL		 207#endif
208
5492fb1a
SMK		 209#ifdef CONFIG_ARCH_OMAP34XX
210static struct gpio_bank gpio_bank_34xx[6] = {
211 { OMAP34XX_GPIO1_BASE, INT_34XX_GPIO_BANK1, IH_GPIO_BASE, METHOD_GPIO_24XX },
212 { OMAP34XX_GPIO2_BASE, INT_34XX_GPIO_BANK2, IH_GPIO_BASE + 32, METHOD_GPIO_24XX },
213 { OMAP34XX_GPIO3_BASE, INT_34XX_GPIO_BANK3, IH_GPIO_BASE + 64, METHOD_GPIO_24XX },
214 { OMAP34XX_GPIO4_BASE, INT_34XX_GPIO_BANK4, IH_GPIO_BASE + 96, METHOD_GPIO_24XX },
215 { OMAP34XX_GPIO5_BASE, INT_34XX_GPIO_BANK5, IH_GPIO_BASE + 128, METHOD_GPIO_24XX },
216 { OMAP34XX_GPIO6_BASE, INT_34XX_GPIO_BANK6, IH_GPIO_BASE + 160, METHOD_GPIO_24XX },
217};
218
219#endif
220
5e1c5ff4
TL		 221static struct gpio_bank *gpio_bank;
222static int gpio_bank_count;
223
224static inline struct gpio_bank *get_gpio_bank(int gpio)
225{
6e60e79a 226 if (cpu_is_omap15xx()) {
5e1c5ff4
TL		 227 if (OMAP_GPIO_IS_MPUIO(gpio))
228 return &gpio_bank[0];
229 return &gpio_bank[1];
230 }
5e1c5ff4
TL		 231 if (cpu_is_omap16xx()) {
232 if (OMAP_GPIO_IS_MPUIO(gpio))
233 return &gpio_bank[0];
234 return &gpio_bank[1 + (gpio >> 4)];
235 }
5e1c5ff4
TL		 236 if (cpu_is_omap730()) {
237 if (OMAP_GPIO_IS_MPUIO(gpio))
238 return &gpio_bank[0];
239 return &gpio_bank[1 + (gpio >> 5)];
240 }
92105bb7
TL		 241 if (cpu_is_omap24xx())
242 return &gpio_bank[gpio >> 5];
5492fb1a
SMK		 243 if (cpu_is_omap34xx())
244 return &gpio_bank[gpio >> 5];
5e1c5ff4
TL		 245}
246
247static inline int get_gpio_index(int gpio)
248{
249 if (cpu_is_omap730())
250 return gpio & 0x1f;
92105bb7
TL		 251 if (cpu_is_omap24xx())
252 return gpio & 0x1f;
5492fb1a
SMK		 253 if (cpu_is_omap34xx())
254 return gpio & 0x1f;
92105bb7 255 return gpio & 0x0f;
5e1c5ff4
TL		 256}
257
258static inline int gpio_valid(int gpio)
259{
260 if (gpio < 0)
261 return -1;
d11ac979 262 if (cpu_class_is_omap1() && OMAP_GPIO_IS_MPUIO(gpio)) {
193e68be 263 if (gpio >= OMAP_MAX_GPIO_LINES + 16)
5e1c5ff4
TL		 264 return -1;
265 return 0;
266 }
6e60e79a 267 if (cpu_is_omap15xx() && gpio < 16)
5e1c5ff4 268 return 0;
5e1c5ff4
TL		 269 if ((cpu_is_omap16xx()) && gpio < 64)
270 return 0;
5e1c5ff4
TL		 271 if (cpu_is_omap730() && gpio < 192)
272 return 0;
92105bb7
TL		 273 if (cpu_is_omap24xx() && gpio < 128)
274 return 0;
5492fb1a
SMK		 275 if (cpu_is_omap34xx() && gpio < 160)
276 return 0;
5e1c5ff4
TL		 277 return -1;
278}
279
280static int check_gpio(int gpio)
281{
282 if (unlikely(gpio_valid(gpio)) < 0) {
283 printk(KERN_ERR "omap-gpio: invalid GPIO %d\n", gpio);
284 dump_stack();
285 return -1;
286 }
287 return 0;
288}
289
290static void _set_gpio_direction(struct gpio_bank *bank, int gpio, int is_input)
291{
92105bb7 292 void __iomem *reg = bank->base;
5e1c5ff4
TL		 293 u32 l;
294
295 switch (bank->method) {
e5c56ed3 296#ifdef CONFIG_ARCH_OMAP1
5e1c5ff4
TL		 297 case METHOD_MPUIO:
298 reg += OMAP_MPUIO_IO_CNTL;
299 break;
e5c56ed3
DB		 300#endif
301#ifdef CONFIG_ARCH_OMAP15XX
5e1c5ff4
TL		 302 case METHOD_GPIO_1510:
303 reg += OMAP1510_GPIO_DIR_CONTROL;
304 break;
e5c56ed3
DB		 305#endif
306#ifdef CONFIG_ARCH_OMAP16XX
5e1c5ff4
TL		 307 case METHOD_GPIO_1610:
308 reg += OMAP1610_GPIO_DIRECTION;
309 break;
e5c56ed3
DB		 310#endif
311#ifdef CONFIG_ARCH_OMAP730
5e1c5ff4
TL		 312 case METHOD_GPIO_730:
313 reg += OMAP730_GPIO_DIR_CONTROL;
314 break;
e5c56ed3 315#endif
5492fb1a 316#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
92105bb7
TL		 317 case METHOD_GPIO_24XX:
318 reg += OMAP24XX_GPIO_OE;
319 break;
e5c56ed3
DB		 320#endif
321 default:
322 WARN_ON(1);
323 return;
5e1c5ff4
TL		 324 }
325 l = __raw_readl(reg);
326 if (is_input)
327 l |= 1 << gpio;
328 else
329 l &= ~(1 << gpio);
330 __raw_writel(l, reg);
331}
332
333void omap_set_gpio_direction(int gpio, int is_input)
334{
335 struct gpio_bank *bank;
a6472533 336 unsigned long flags;
5e1c5ff4
TL		 337
338 if (check_gpio(gpio) < 0)
339 return;
340 bank = get_gpio_bank(gpio);
a6472533 341 spin_lock_irqsave(&bank->lock, flags);
5e1c5ff4 342 _set_gpio_direction(bank, get_gpio_index(gpio), is_input);
a6472533 343 spin_unlock_irqrestore(&bank->lock, flags);
5e1c5ff4
TL		 344}
345
346static void _set_gpio_dataout(struct gpio_bank *bank, int gpio, int enable)
347{
92105bb7 348 void __iomem *reg = bank->base;
5e1c5ff4
TL		 349 u32 l = 0;
350
351 switch (bank->method) {
e5c56ed3 352#ifdef CONFIG_ARCH_OMAP1
5e1c5ff4
TL		 353 case METHOD_MPUIO:
354 reg += OMAP_MPUIO_OUTPUT;
355 l = __raw_readl(reg);
356 if (enable)
357 l |= 1 << gpio;
358 else
359 l &= ~(1 << gpio);
360 break;
e5c56ed3
DB		 361#endif
362#ifdef CONFIG_ARCH_OMAP15XX
5e1c5ff4
TL		 363 case METHOD_GPIO_1510:
364 reg += OMAP1510_GPIO_DATA_OUTPUT;
365 l = __raw_readl(reg);
366 if (enable)
367 l |= 1 << gpio;
368 else
369 l &= ~(1 << gpio);
370 break;
e5c56ed3
DB		 371#endif
372#ifdef CONFIG_ARCH_OMAP16XX
5e1c5ff4
TL		 373 case METHOD_GPIO_1610:
374 if (enable)
375 reg += OMAP1610_GPIO_SET_DATAOUT;
376 else
377 reg += OMAP1610_GPIO_CLEAR_DATAOUT;
378 l = 1 << gpio;
379 break;
e5c56ed3
DB		 380#endif
381#ifdef CONFIG_ARCH_OMAP730
5e1c5ff4
TL		 382 case METHOD_GPIO_730:
383 reg += OMAP730_GPIO_DATA_OUTPUT;
384 l = __raw_readl(reg);
385 if (enable)
386 l |= 1 << gpio;
387 else
388 l &= ~(1 << gpio);
389 break;
e5c56ed3 390#endif
5492fb1a 391#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
92105bb7
TL		 392 case METHOD_GPIO_24XX:
393 if (enable)
394 reg += OMAP24XX_GPIO_SETDATAOUT;
395 else
396 reg += OMAP24XX_GPIO_CLEARDATAOUT;
397 l = 1 << gpio;
398 break;
e5c56ed3 399#endif
5e1c5ff4 400 default:
e5c56ed3 401 WARN_ON(1);
5e1c5ff4
TL		 402 return;
403 }
404 __raw_writel(l, reg);
405}
406
407void omap_set_gpio_dataout(int gpio, int enable)
408{
409 struct gpio_bank *bank;
a6472533 410 unsigned long flags;
5e1c5ff4
TL		 411
412 if (check_gpio(gpio) < 0)
413 return;
414 bank = get_gpio_bank(gpio);
a6472533 415 spin_lock_irqsave(&bank->lock, flags);
5e1c5ff4 416 _set_gpio_dataout(bank, get_gpio_index(gpio), enable);
a6472533 417 spin_unlock_irqrestore(&bank->lock, flags);
5e1c5ff4
TL		 418}
419
420int omap_get_gpio_datain(int gpio)
421{
422 struct gpio_bank *bank;
92105bb7 423 void __iomem *reg;
5e1c5ff4
TL		 424
425 if (check_gpio(gpio) < 0)
e5c56ed3 426 return -EINVAL;
5e1c5ff4
TL		 427 bank = get_gpio_bank(gpio);
428 reg = bank->base;
429 switch (bank->method) {
e5c56ed3 430#ifdef CONFIG_ARCH_OMAP1
5e1c5ff4
TL		 431 case METHOD_MPUIO:
432 reg += OMAP_MPUIO_INPUT_LATCH;
433 break;
e5c56ed3
DB		 434#endif
435#ifdef CONFIG_ARCH_OMAP15XX
5e1c5ff4
TL		 436 case METHOD_GPIO_1510:
437 reg += OMAP1510_GPIO_DATA_INPUT;
438 break;
e5c56ed3
DB		 439#endif
440#ifdef CONFIG_ARCH_OMAP16XX
5e1c5ff4
TL		 441 case METHOD_GPIO_1610:
442 reg += OMAP1610_GPIO_DATAIN;
443 break;
e5c56ed3
DB		 444#endif
445#ifdef CONFIG_ARCH_OMAP730
5e1c5ff4
TL		 446 case METHOD_GPIO_730:
447 reg += OMAP730_GPIO_DATA_INPUT;
448 break;
e5c56ed3 449#endif
5492fb1a 450#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
92105bb7
TL		 451 case METHOD_GPIO_24XX:
452 reg += OMAP24XX_GPIO_DATAIN;
453 break;
e5c56ed3 454#endif
5e1c5ff4 455 default:
e5c56ed3 456 return -EINVAL;
5e1c5ff4 457 }
92105bb7
TL		 458 return (__raw_readl(reg)
459 & (1 << get_gpio_index(gpio))) != 0;
5e1c5ff4
TL		 460}
461
92105bb7
TL		 462#define MOD_REG_BIT(reg, bit_mask, set) \
463do { \
464 int l = __raw_readl(base + reg); \
465 if (set) l |= bit_mask; \
466 else l &= ~bit_mask; \
467 __raw_writel(l, base + reg); \
468} while(0)
469
5eb3bb9c
KH		 470void omap_set_gpio_debounce(int gpio, int enable)
471{
472 struct gpio_bank *bank;
473 void __iomem *reg;
474 u32 val, l = 1 << get_gpio_index(gpio);
475
476 if (cpu_class_is_omap1())
477 return;
478
479 bank = get_gpio_bank(gpio);
480 reg = bank->base;
481
482 reg += OMAP24XX_GPIO_DEBOUNCE_EN;
483 val = __raw_readl(reg);
484
485 if (enable)
486 val |= l;
487 else
488 val &= ~l;
489
490 __raw_writel(val, reg);
491}
492EXPORT_SYMBOL(omap_set_gpio_debounce);
493
494void omap_set_gpio_debounce_time(int gpio, int enc_time)
495{
496 struct gpio_bank *bank;
497 void __iomem *reg;
498
499 if (cpu_class_is_omap1())
500 return;
501
502 bank = get_gpio_bank(gpio);
503 reg = bank->base;
504
505 enc_time &= 0xff;
506 reg += OMAP24XX_GPIO_DEBOUNCE_VAL;
507 __raw_writel(enc_time, reg);
508}
509EXPORT_SYMBOL(omap_set_gpio_debounce_time);
510
5492fb1a 511#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
5eb3bb9c
KH		 512static inline void set_24xx_gpio_triggering(struct gpio_bank *bank, int gpio,
513 int trigger)
5e1c5ff4 514{
3ac4fa99 515 void __iomem *base = bank->base;
92105bb7
TL		 516 u32 gpio_bit = 1 << gpio;
517
518 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT0, gpio_bit,
6cab4860 519 trigger & IRQ_TYPE_LEVEL_LOW);
92105bb7 520 MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT1, gpio_bit,
6cab4860 521 trigger & IRQ_TYPE_LEVEL_HIGH);
92105bb7 522 MOD_REG_BIT(OMAP24XX_GPIO_RISINGDETECT, gpio_bit,
6cab4860 523 trigger & IRQ_TYPE_EDGE_RISING);
92105bb7 524 MOD_REG_BIT(OMAP24XX_GPIO_FALLINGDETECT, gpio_bit,
6cab4860 525 trigger & IRQ_TYPE_EDGE_FALLING);
5eb3bb9c 526
3ac4fa99
JY		 527 if (likely(!(bank->non_wakeup_gpios & gpio_bit))) {
528 if (trigger != 0)
5eb3bb9c
KH		 529 __raw_writel(1 << gpio, bank->base
530 + OMAP24XX_GPIO_SETWKUENA);
3ac4fa99 531 else
5eb3bb9c
KH		 532 __raw_writel(1 << gpio, bank->base
533 + OMAP24XX_GPIO_CLEARWKUENA);
3ac4fa99
JY		 534 } else {
535 if (trigger != 0)
536 bank->enabled_non_wakeup_gpios |= gpio_bit;
537 else
538 bank->enabled_non_wakeup_gpios &= ~gpio_bit;
539 }
5eb3bb9c 540
b144ff6f
KH		 541 bank->level_mask =
542 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0) |
543 __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
92105bb7 544}
3ac4fa99 545#endif
92105bb7
TL		 546
547static int _set_gpio_triggering(struct gpio_bank *bank, int gpio, int trigger)
548{
549 void __iomem *reg = bank->base;
550 u32 l = 0;
5e1c5ff4
TL		 551
552 switch (bank->method) {
e5c56ed3 553#ifdef CONFIG_ARCH_OMAP1
5e1c5ff4
TL		 554 case METHOD_MPUIO:
555 reg += OMAP_MPUIO_GPIO_INT_EDGE;
556 l = __raw_readl(reg);
6cab4860 557 if (trigger & IRQ_TYPE_EDGE_RISING)
5e1c5ff4 558 l |= 1 << gpio;
6cab4860 559 else if (trigger & IRQ_TYPE_EDGE_FALLING)
5e1c5ff4 560 l &= ~(1 << gpio);
92105bb7
TL		 561 else
562 goto bad;
5e1c5ff4 563 break;
e5c56ed3
DB		 564#endif
565#ifdef CONFIG_ARCH_OMAP15XX
5e1c5ff4
TL		 566 case METHOD_GPIO_1510:
567 reg += OMAP1510_GPIO_INT_CONTROL;
568 l = __raw_readl(reg);
6cab4860 569 if (trigger & IRQ_TYPE_EDGE_RISING)
5e1c5ff4 570 l |= 1 << gpio;
6cab4860 571 else if (trigger & IRQ_TYPE_EDGE_FALLING)
5e1c5ff4 572 l &= ~(1 << gpio);
92105bb7
TL		 573 else
574 goto bad;
5e1c5ff4 575 break;
e5c56ed3 576#endif
3ac4fa99 577#ifdef CONFIG_ARCH_OMAP16XX
5e1c5ff4 578 case METHOD_GPIO_1610:
5e1c5ff4
TL		 579 if (gpio & 0x08)
580 reg += OMAP1610_GPIO_EDGE_CTRL2;
581 else
582 reg += OMAP1610_GPIO_EDGE_CTRL1;
583 gpio &= 0x07;
584 l = __raw_readl(reg);
585 l &= ~(3 << (gpio << 1));
6cab4860 586 if (trigger & IRQ_TYPE_EDGE_RISING)
6e60e79a 587 l |= 2 << (gpio << 1);
6cab4860 588 if (trigger & IRQ_TYPE_EDGE_FALLING)
6e60e79a 589 l |= 1 << (gpio << 1);
3ac4fa99
JY		 590 if (trigger)
591 /* Enable wake-up during idle for dynamic tick */
592 __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_SET_WAKEUPENA);
593 else
594 __raw_writel(1 << gpio, bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA);
5e1c5ff4 595 break;
3ac4fa99
JY		 596#endif
597#ifdef CONFIG_ARCH_OMAP730
5e1c5ff4
TL		 598 case METHOD_GPIO_730:
599 reg += OMAP730_GPIO_INT_CONTROL;
600 l = __raw_readl(reg);
6cab4860 601 if (trigger & IRQ_TYPE_EDGE_RISING)
5e1c5ff4 602 l |= 1 << gpio;
6cab4860 603 else if (trigger & IRQ_TYPE_EDGE_FALLING)
5e1c5ff4 604 l &= ~(1 << gpio);
92105bb7
TL		 605 else
606 goto bad;
607 break;
3ac4fa99 608#endif
5492fb1a 609#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
92105bb7 610 case METHOD_GPIO_24XX:
3ac4fa99 611 set_24xx_gpio_triggering(bank, gpio, trigger);
5e1c5ff4 612 break;
3ac4fa99 613#endif
5e1c5ff4 614 default:
92105bb7 615 goto bad;
5e1c5ff4 616 }
92105bb7
TL		 617 __raw_writel(l, reg);
618 return 0;
619bad:
620 return -EINVAL;
5e1c5ff4
TL		 621}
622
92105bb7 623static int gpio_irq_type(unsigned irq, unsigned type)
5e1c5ff4
TL		 624{
625 struct gpio_bank *bank;
92105bb7
TL		 626 unsigned gpio;
627 int retval;
a6472533 628 unsigned long flags;
92105bb7 629
5492fb1a 630 if (!cpu_class_is_omap2() && irq > IH_MPUIO_BASE)
92105bb7
TL		 631 gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
632 else
633 gpio = irq - IH_GPIO_BASE;
5e1c5ff4
TL		 634
635 if (check_gpio(gpio) < 0)
92105bb7
TL		 636 return -EINVAL;
637
e5c56ed3 638 if (type & ~IRQ_TYPE_SENSE_MASK)
6e60e79a 639 return -EINVAL;
e5c56ed3
DB		 640
641 /* OMAP1 allows only only edge triggering */
5492fb1a 642 if (!cpu_class_is_omap2()
e5c56ed3 643 && (type & (IRQ_TYPE_LEVEL_LOW|IRQ_TYPE_LEVEL_HIGH)))
92105bb7
TL		 644 return -EINVAL;
645
58781016 646 bank = get_irq_chip_data(irq);
a6472533 647 spin_lock_irqsave(&bank->lock, flags);
92105bb7 648 retval = _set_gpio_triggering(bank, get_gpio_index(gpio), type);
b9772a22
DB		 649 if (retval == 0) {
650 irq_desc[irq].status &= ~IRQ_TYPE_SENSE_MASK;
651 irq_desc[irq].status |= type;
652 }
a6472533 653 spin_unlock_irqrestore(&bank->lock, flags);
672e302e
KH		 654
655 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_LEVEL_HIGH))
656 __set_irq_handler_unlocked(irq, handle_level_irq);
657 else if (type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_EDGE_RISING))
658 __set_irq_handler_unlocked(irq, handle_edge_irq);
659
92105bb7 660 return retval;
5e1c5ff4
TL		 661}
662
663static void _clear_gpio_irqbank(struct gpio_bank *bank, int gpio_mask)
664{
92105bb7 665 void __iomem *reg = bank->base;
5e1c5ff4
TL		 666
667 switch (bank->method) {
e5c56ed3 668#ifdef CONFIG_ARCH_OMAP1
5e1c5ff4
TL		 669 case METHOD_MPUIO:
670 /* MPUIO irqstatus is reset by reading the status register,
671 * so do nothing here */
672 return;
e5c56ed3
DB		 673#endif
674#ifdef CONFIG_ARCH_OMAP15XX
5e1c5ff4
TL		 675 case METHOD_GPIO_1510:
676 reg += OMAP1510_GPIO_INT_STATUS;
677 break;
e5c56ed3
DB		 678#endif
679#ifdef CONFIG_ARCH_OMAP16XX
5e1c5ff4
TL		 680 case METHOD_GPIO_1610:
681 reg += OMAP1610_GPIO_IRQSTATUS1;
682 break;
e5c56ed3
DB		 683#endif
684#ifdef CONFIG_ARCH_OMAP730
5e1c5ff4
TL		 685 case METHOD_GPIO_730:
686 reg += OMAP730_GPIO_INT_STATUS;
687 break;
e5c56ed3 688#endif
5492fb1a 689#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
92105bb7
TL		 690 case METHOD_GPIO_24XX:
691 reg += OMAP24XX_GPIO_IRQSTATUS1;
692 break;
e5c56ed3 693#endif
5e1c5ff4 694 default:
e5c56ed3 695 WARN_ON(1);
5e1c5ff4
TL		 696 return;
697 }
698 __raw_writel(gpio_mask, reg);
bee7930f
HD		 699
700 /* Workaround for clearing DSP GPIO interrupts to allow retention */
5492fb1a
SMK		 701#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
702 if (cpu_is_omap24xx() || cpu_is_omap34xx())
bee7930f 703 __raw_writel(gpio_mask, bank->base + OMAP24XX_GPIO_IRQSTATUS2);
5492fb1a 704#endif
5e1c5ff4
TL		 705}
706
707static inline void _clear_gpio_irqstatus(struct gpio_bank *bank, int gpio)
708{
709 _clear_gpio_irqbank(bank, 1 << get_gpio_index(gpio));
710}
711
ea6dedd7
ID		 712static u32 _get_gpio_irqbank_mask(struct gpio_bank *bank)
713{
714 void __iomem *reg = bank->base;
99c47707
ID		 715 int inv = 0;
716 u32 l;
717 u32 mask;
ea6dedd7
ID		 718
719 switch (bank->method) {
e5c56ed3 720#ifdef CONFIG_ARCH_OMAP1
ea6dedd7
ID		 721 case METHOD_MPUIO:
722 reg += OMAP_MPUIO_GPIO_MASKIT;
99c47707
ID		 723 mask = 0xffff;
724 inv = 1;
ea6dedd7 725 break;
e5c56ed3
DB		 726#endif
727#ifdef CONFIG_ARCH_OMAP15XX
ea6dedd7
ID		 728 case METHOD_GPIO_1510:
729 reg += OMAP1510_GPIO_INT_MASK;
99c47707
ID		 730 mask = 0xffff;
731 inv = 1;
ea6dedd7 732 break;
e5c56ed3
DB		 733#endif
734#ifdef CONFIG_ARCH_OMAP16XX
ea6dedd7
ID		 735 case METHOD_GPIO_1610:
736 reg += OMAP1610_GPIO_IRQENABLE1;
99c47707 737 mask = 0xffff;
ea6dedd7 738 break;
e5c56ed3
DB		 739#endif
740#ifdef CONFIG_ARCH_OMAP730
ea6dedd7
ID		 741 case METHOD_GPIO_730:
742 reg += OMAP730_GPIO_INT_MASK;
99c47707
ID		 743 mask = 0xffffffff;
744 inv = 1;
ea6dedd7 745 break;
e5c56ed3 746#endif
5492fb1a 747#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
ea6dedd7
ID		 748 case METHOD_GPIO_24XX:
749 reg += OMAP24XX_GPIO_IRQENABLE1;
99c47707 750 mask = 0xffffffff;
ea6dedd7 751 break;
e5c56ed3 752#endif
ea6dedd7 753 default:
e5c56ed3 754 WARN_ON(1);
ea6dedd7
ID		 755 return 0;
756 }
757
99c47707
ID		 758 l = __raw_readl(reg);
759 if (inv)
760 l = ~l;
761 l &= mask;
762 return l;
ea6dedd7
ID		 763}
764
5e1c5ff4
TL		 765static void _enable_gpio_irqbank(struct gpio_bank *bank, int gpio_mask, int enable)
766{
92105bb7 767 void __iomem *reg = bank->base;
5e1c5ff4
TL		 768 u32 l;
769
770 switch (bank->method) {
e5c56ed3 771#ifdef CONFIG_ARCH_OMAP1
5e1c5ff4
TL		 772 case METHOD_MPUIO:
773 reg += OMAP_MPUIO_GPIO_MASKIT;
774 l = __raw_readl(reg);
775 if (enable)
776 l &= ~(gpio_mask);
777 else
778 l |= gpio_mask;
779 break;
e5c56ed3
DB		 780#endif
781#ifdef CONFIG_ARCH_OMAP15XX
5e1c5ff4
TL		 782 case METHOD_GPIO_1510:
783 reg += OMAP1510_GPIO_INT_MASK;
784 l = __raw_readl(reg);
785 if (enable)
786 l &= ~(gpio_mask);
787 else
788 l |= gpio_mask;
789 break;
e5c56ed3
DB		 790#endif
791#ifdef CONFIG_ARCH_OMAP16XX
5e1c5ff4
TL		 792 case METHOD_GPIO_1610:
793 if (enable)
794 reg += OMAP1610_GPIO_SET_IRQENABLE1;
795 else
796 reg += OMAP1610_GPIO_CLEAR_IRQENABLE1;
797 l = gpio_mask;
798 break;
e5c56ed3
DB		 799#endif
800#ifdef CONFIG_ARCH_OMAP730
5e1c5ff4
TL		 801 case METHOD_GPIO_730:
802 reg += OMAP730_GPIO_INT_MASK;
803 l = __raw_readl(reg);
804 if (enable)
805 l &= ~(gpio_mask);
806 else
807 l |= gpio_mask;
808 break;
e5c56ed3 809#endif
5492fb1a 810#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
92105bb7
TL		 811 case METHOD_GPIO_24XX:
812 if (enable)
813 reg += OMAP24XX_GPIO_SETIRQENABLE1;
814 else
815 reg += OMAP24XX_GPIO_CLEARIRQENABLE1;
816 l = gpio_mask;
817 break;
e5c56ed3 818#endif
5e1c5ff4 819 default:
e5c56ed3 820 WARN_ON(1);
5e1c5ff4
TL		 821 return;
822 }
823 __raw_writel(l, reg);
824}
825
826static inline void _set_gpio_irqenable(struct gpio_bank *bank, int gpio, int enable)
827{
828 _enable_gpio_irqbank(bank, 1 << get_gpio_index(gpio), enable);
829}
830
92105bb7
TL		 831/*
832 * Note that ENAWAKEUP needs to be enabled in GPIO_SYSCONFIG register.
833 * 1510 does not seem to have a wake-up register. If JTAG is connected
834 * to the target, system will wake up always on GPIO events. While
835 * system is running all registered GPIO interrupts need to have wake-up
836 * enabled. When system is suspended, only selected GPIO interrupts need
837 * to have wake-up enabled.
838 */
839static int _set_gpio_wakeup(struct gpio_bank *bank, int gpio, int enable)
840{
a6472533
DB		 841 unsigned long flags;
842
92105bb7 843 switch (bank->method) {
3ac4fa99 844#ifdef CONFIG_ARCH_OMAP16XX
11a78b79 845 case METHOD_MPUIO:
92105bb7 846 case METHOD_GPIO_1610:
a6472533 847 spin_lock_irqsave(&bank->lock, flags);
11a78b79 848 if (enable) {
92105bb7 849 bank->suspend_wakeup |= (1 << gpio);
11a78b79
DB		 850 enable_irq_wake(bank->irq);
851 } else {
852 disable_irq_wake(bank->irq);
92105bb7 853 bank->suspend_wakeup &= ~(1 << gpio);
11a78b79 854 }
a6472533 855 spin_unlock_irqrestore(&bank->lock, flags);
92105bb7 856 return 0;
3ac4fa99 857#endif
5492fb1a 858#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
3ac4fa99 859 case METHOD_GPIO_24XX:
11a78b79
DB		 860 if (bank->non_wakeup_gpios & (1 << gpio)) {
861 printk(KERN_ERR "Unable to modify wakeup on "
862 "non-wakeup GPIO%d\n",
863 (bank - gpio_bank) * 32 + gpio);
864 return -EINVAL;
865 }
a6472533 866 spin_lock_irqsave(&bank->lock, flags);
3ac4fa99 867 if (enable) {
3ac4fa99 868 bank->suspend_wakeup |= (1 << gpio);
11a78b79
DB		 869 enable_irq_wake(bank->irq);
870 } else {
871 disable_irq_wake(bank->irq);
3ac4fa99 872 bank->suspend_wakeup &= ~(1 << gpio);
11a78b79 873 }
a6472533 874 spin_unlock_irqrestore(&bank->lock, flags);
3ac4fa99
JY		 875 return 0;
876#endif
92105bb7
TL		 877 default:
878 printk(KERN_ERR "Can't enable GPIO wakeup for method %i\n",
879 bank->method);
880 return -EINVAL;
881 }
882}
883
4196dd6b
TL		 884static void _reset_gpio(struct gpio_bank *bank, int gpio)
885{
886 _set_gpio_direction(bank, get_gpio_index(gpio), 1);
887 _set_gpio_irqenable(bank, gpio, 0);
888 _clear_gpio_irqstatus(bank, gpio);
6cab4860 889 _set_gpio_triggering(bank, get_gpio_index(gpio), IRQ_TYPE_NONE);
4196dd6b
TL		 890}
891
92105bb7
TL		 892/* Use disable_irq_wake() and enable_irq_wake() functions from drivers */
893static int gpio_wake_enable(unsigned int irq, unsigned int enable)
894{
895 unsigned int gpio = irq - IH_GPIO_BASE;
896 struct gpio_bank *bank;
897 int retval;
898
899 if (check_gpio(gpio) < 0)
900 return -ENODEV;
58781016 901 bank = get_irq_chip_data(irq);
92105bb7 902 retval = _set_gpio_wakeup(bank, get_gpio_index(gpio), enable);
92105bb7
TL		 903
904 return retval;
905}
906
5e1c5ff4
TL		 907int omap_request_gpio(int gpio)
908{
909 struct gpio_bank *bank;
a6472533 910 unsigned long flags;
52e31344 911 int status;
5e1c5ff4
TL		 912
913 if (check_gpio(gpio) < 0)
914 return -EINVAL;
915
52e31344
DB		 916 status = gpio_request(gpio, NULL);
917 if (status < 0)
918 return status;
919
5e1c5ff4 920 bank = get_gpio_bank(gpio);
a6472533 921 spin_lock_irqsave(&bank->lock, flags);
92105bb7 922
4196dd6b
TL		 923 /* Set trigger to none. You need to enable the desired trigger with
924 * request_irq() or set_irq_type().
925 */
6cab4860 926 _set_gpio_triggering(bank, get_gpio_index(gpio), IRQ_TYPE_NONE);
92105bb7 927
1a8bfa1e 928#ifdef CONFIG_ARCH_OMAP15XX
5e1c5ff4 929 if (bank->method == METHOD_GPIO_1510) {
92105bb7 930 void __iomem *reg;
5e1c5ff4 931
92105bb7 932 /* Claim the pin for MPU */
5e1c5ff4
TL		 933 reg = bank->base + OMAP1510_GPIO_PIN_CONTROL;
934 __raw_writel(__raw_readl(reg) | (1 << get_gpio_index(gpio)), reg);
935 }
936#endif
a6472533 937 spin_unlock_irqrestore(&bank->lock, flags);
5e1c5ff4
TL		 938
939 return 0;
940}
941
942void omap_free_gpio(int gpio)
943{
944 struct gpio_bank *bank;
a6472533 945 unsigned long flags;
5e1c5ff4
TL		 946
947 if (check_gpio(gpio) < 0)
948 return;
949 bank = get_gpio_bank(gpio);
a6472533 950 spin_lock_irqsave(&bank->lock, flags);
52e31344
DB		 951 if (unlikely(!gpiochip_is_requested(&bank->chip,
952 get_gpio_index(gpio)))) {
953 spin_unlock_irqrestore(&bank->lock, flags);
5e1c5ff4
TL		 954 printk(KERN_ERR "omap-gpio: GPIO %d wasn't reserved!\n", gpio);
955 dump_stack();
5e1c5ff4
TL		 956 return;
957 }
92105bb7
TL		 958#ifdef CONFIG_ARCH_OMAP16XX
959 if (bank->method == METHOD_GPIO_1610) {
960 /* Disable wake-up during idle for dynamic tick */
961 void __iomem *reg = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
962 __raw_writel(1 << get_gpio_index(gpio), reg);
963 }
964#endif
5492fb1a 965#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
92105bb7
TL		 966 if (bank->method == METHOD_GPIO_24XX) {
967 /* Disable wake-up during idle for dynamic tick */
968 void __iomem *reg = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
969 __raw_writel(1 << get_gpio_index(gpio), reg);
970 }
971#endif
4196dd6b 972 _reset_gpio(bank, gpio);
a6472533 973 spin_unlock_irqrestore(&bank->lock, flags);
52e31344 974 gpio_free(gpio);
5e1c5ff4
TL		 975}
976
977/*
978 * We need to unmask the GPIO bank interrupt as soon as possible to
979 * avoid missing GPIO interrupts for other lines in the bank.
980 * Then we need to mask-read-clear-unmask the triggered GPIO lines
981 * in the bank to avoid missing nested interrupts for a GPIO line.
982 * If we wait to unmask individual GPIO lines in the bank after the
983 * line's interrupt handler has been run, we may miss some nested
984 * interrupts.
985 */
10dd5ce2 986static void gpio_irq_handler(unsigned int irq, struct irq_desc *desc)
5e1c5ff4 987{
92105bb7 988 void __iomem *isr_reg = NULL;
5e1c5ff4
TL		 989 u32 isr;
990 unsigned int gpio_irq;
991 struct gpio_bank *bank;
ea6dedd7
ID		 992 u32 retrigger = 0;
993 int unmasked = 0;
5e1c5ff4
TL		 994
995 desc->chip->ack(irq);
996
418ca1f0 997 bank = get_irq_data(irq);
e5c56ed3 998#ifdef CONFIG_ARCH_OMAP1
5e1c5ff4
TL		 999 if (bank->method == METHOD_MPUIO)
1000 isr_reg = bank->base + OMAP_MPUIO_GPIO_INT;
e5c56ed3 1001#endif
1a8bfa1e 1002#ifdef CONFIG_ARCH_OMAP15XX
5e1c5ff4
TL		 1003 if (bank->method == METHOD_GPIO_1510)
1004 isr_reg = bank->base + OMAP1510_GPIO_INT_STATUS;
1005#endif
1006#if defined(CONFIG_ARCH_OMAP16XX)
1007 if (bank->method == METHOD_GPIO_1610)
1008 isr_reg = bank->base + OMAP1610_GPIO_IRQSTATUS1;
1009#endif
1010#ifdef CONFIG_ARCH_OMAP730
1011 if (bank->method == METHOD_GPIO_730)
1012 isr_reg = bank->base + OMAP730_GPIO_INT_STATUS;
1013#endif
5492fb1a 1014#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
92105bb7
TL		 1015 if (bank->method == METHOD_GPIO_24XX)
1016 isr_reg = bank->base + OMAP24XX_GPIO_IRQSTATUS1;
1017#endif
92105bb7 1018 while(1) {
6e60e79a 1019 u32 isr_saved, level_mask = 0;
ea6dedd7 1020 u32 enabled;
6e60e79a 1021
ea6dedd7
ID		 1022 enabled = _get_gpio_irqbank_mask(bank);
1023 isr_saved = isr = __raw_readl(isr_reg) & enabled;
6e60e79a
TL		 1024
1025 if (cpu_is_omap15xx() && (bank->method == METHOD_MPUIO))
1026 isr &= 0x0000ffff;
1027
5492fb1a 1028 if (cpu_class_is_omap2()) {
b144ff6f 1029 level_mask = bank->level_mask & enabled;
ea6dedd7 1030 }
6e60e79a
TL		 1031
1032 /* clear edge sensitive interrupts before handler(s) are
1033 called so that we don't miss any interrupt occurred while
1034 executing them */
1035 _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 0);
1036 _clear_gpio_irqbank(bank, isr_saved & ~level_mask);
1037 _enable_gpio_irqbank(bank, isr_saved & ~level_mask, 1);
1038
1039 /* if there is only edge sensitive GPIO pin interrupts
1040 configured, we could unmask GPIO bank interrupt immediately */
ea6dedd7
ID		 1041 if (!level_mask && !unmasked) {
1042 unmasked = 1;
6e60e79a 1043 desc->chip->unmask(irq);
ea6dedd7 1044 }
92105bb7 1045
ea6dedd7
ID		 1046 isr |= retrigger;
1047 retrigger = 0;
92105bb7
TL		 1048 if (!isr)
1049 break;
1050
1051 gpio_irq = bank->virtual_irq_start;
1052 for (; isr != 0; isr >>= 1, gpio_irq++) {
10dd5ce2 1053 struct irq_desc *d;
672e302e 1054
92105bb7
TL		 1055 if (!(isr & 1))
1056 continue;
1057 d = irq_desc + gpio_irq;
29454dde 1058
0cd61b68 1059 desc_handle_irq(gpio_irq, d);
92105bb7 1060 }
1a8bfa1e 1061 }
ea6dedd7
ID		 1062 /* if bank has any level sensitive GPIO pin interrupt
1063 configured, we must unmask the bank interrupt only after
1064 handler(s) are executed in order to avoid spurious bank
1065 interrupt */
1066 if (!unmasked)
1067 desc->chip->unmask(irq);
1068
5e1c5ff4
TL		 1069}
1070
4196dd6b
TL		 1071static void gpio_irq_shutdown(unsigned int irq)
1072{
1073 unsigned int gpio = irq - IH_GPIO_BASE;
58781016 1074 struct gpio_bank *bank = get_irq_chip_data(irq);
4196dd6b
TL		 1075
1076 _reset_gpio(bank, gpio);
1077}
1078
5e1c5ff4
TL		 1079static void gpio_ack_irq(unsigned int irq)
1080{
1081 unsigned int gpio = irq - IH_GPIO_BASE;
58781016 1082 struct gpio_bank *bank = get_irq_chip_data(irq);
5e1c5ff4
TL		 1083
1084 _clear_gpio_irqstatus(bank, gpio);
1085}
1086
1087static void gpio_mask_irq(unsigned int irq)
1088{
1089 unsigned int gpio = irq - IH_GPIO_BASE;
58781016 1090 struct gpio_bank *bank = get_irq_chip_data(irq);
5e1c5ff4
TL		 1091
1092 _set_gpio_irqenable(bank, gpio, 0);
1093}
1094
1095static void gpio_unmask_irq(unsigned int irq)
1096{
1097 unsigned int gpio = irq - IH_GPIO_BASE;
58781016 1098 struct gpio_bank *bank = get_irq_chip_data(irq);
b144ff6f
KH		 1099 unsigned int irq_mask = 1 << get_gpio_index(gpio);
1100
1101 /* For level-triggered GPIOs, the clearing must be done after
1102 * the HW source is cleared, thus after the handler has run */
1103 if (bank->level_mask & irq_mask) {
1104 _set_gpio_irqenable(bank, gpio, 0);
1105 _clear_gpio_irqstatus(bank, gpio);
1106 }
5e1c5ff4 1107
4de8c75b 1108 _set_gpio_irqenable(bank, gpio, 1);
5e1c5ff4
TL		 1109}
1110
e5c56ed3
DB		 1111static struct irq_chip gpio_irq_chip = {
1112 .name = "GPIO",
1113 .shutdown = gpio_irq_shutdown,
1114 .ack = gpio_ack_irq,
1115 .mask = gpio_mask_irq,
1116 .unmask = gpio_unmask_irq,
1117 .set_type = gpio_irq_type,
1118 .set_wake = gpio_wake_enable,
1119};
1120
1121/*---------------------------------------------------------------------*/
1122
1123#ifdef CONFIG_ARCH_OMAP1
1124
1125/* MPUIO uses the always-on 32k clock */
1126
5e1c5ff4
TL		 1127static void mpuio_ack_irq(unsigned int irq)
1128{
1129 /* The ISR is reset automatically, so do nothing here. */
1130}
1131
1132static void mpuio_mask_irq(unsigned int irq)
1133{
1134 unsigned int gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
58781016 1135 struct gpio_bank *bank = get_irq_chip_data(irq);
5e1c5ff4
TL		 1136
1137 _set_gpio_irqenable(bank, gpio, 0);
1138}
1139
1140static void mpuio_unmask_irq(unsigned int irq)
1141{
1142 unsigned int gpio = OMAP_MPUIO(irq - IH_MPUIO_BASE);
58781016 1143 struct gpio_bank *bank = get_irq_chip_data(irq);
5e1c5ff4
TL		 1144
1145 _set_gpio_irqenable(bank, gpio, 1);
1146}
1147
e5c56ed3
DB		 1148static struct irq_chip mpuio_irq_chip = {
1149 .name = "MPUIO",
1150 .ack = mpuio_ack_irq,
1151 .mask = mpuio_mask_irq,
1152 .unmask = mpuio_unmask_irq,
92105bb7 1153 .set_type = gpio_irq_type,
11a78b79
DB		 1154#ifdef CONFIG_ARCH_OMAP16XX
1155 /* REVISIT: assuming only 16xx supports MPUIO wake events */
1156 .set_wake = gpio_wake_enable,
1157#endif
5e1c5ff4
TL		 1158};
1159
e5c56ed3
DB		 1160
1161#define bank_is_mpuio(bank) ((bank)->method == METHOD_MPUIO)
1162
11a78b79
DB		 1163
1164#ifdef CONFIG_ARCH_OMAP16XX
1165
1166#include <linux/platform_device.h>
1167
1168static int omap_mpuio_suspend_late(struct platform_device *pdev, pm_message_t mesg)
1169{
1170 struct gpio_bank *bank = platform_get_drvdata(pdev);
1171 void __iomem *mask_reg = bank->base + OMAP_MPUIO_GPIO_MASKIT;
a6472533 1172 unsigned long flags;
11a78b79 1173
a6472533 1174 spin_lock_irqsave(&bank->lock, flags);
11a78b79
DB		 1175 bank->saved_wakeup = __raw_readl(mask_reg);
1176 __raw_writel(0xffff & ~bank->suspend_wakeup, mask_reg);
a6472533 1177 spin_unlock_irqrestore(&bank->lock, flags);
11a78b79
DB		 1178
1179 return 0;
1180}
1181
1182static int omap_mpuio_resume_early(struct platform_device *pdev)
1183{
1184 struct gpio_bank *bank = platform_get_drvdata(pdev);
1185 void __iomem *mask_reg = bank->base + OMAP_MPUIO_GPIO_MASKIT;
a6472533 1186 unsigned long flags;
11a78b79 1187
a6472533 1188 spin_lock_irqsave(&bank->lock, flags);
11a78b79 1189 __raw_writel(bank->saved_wakeup, mask_reg);
a6472533 1190 spin_unlock_irqrestore(&bank->lock, flags);
11a78b79
DB		 1191
1192 return 0;
1193}
1194
1195/* use platform_driver for this, now that there's no longer any
1196 * point to sys_device (other than not disturbing old code).
1197 */
1198static struct platform_driver omap_mpuio_driver = {
1199 .suspend_late = omap_mpuio_suspend_late,
1200 .resume_early = omap_mpuio_resume_early,
1201 .driver = {
1202 .name = "mpuio",
1203 },
1204};
1205
1206static struct platform_device omap_mpuio_device = {
1207 .name = "mpuio",
1208 .id = -1,
1209 .dev = {
1210 .driver = &omap_mpuio_driver.driver,
1211 }
1212 /* could list the /proc/iomem resources */
1213};
1214
1215static inline void mpuio_init(void)
1216{
fcf126d8
DB		 1217 platform_set_drvdata(&omap_mpuio_device, &gpio_bank_1610[0]);
1218
11a78b79
DB		 1219 if (platform_driver_register(&omap_mpuio_driver) == 0)
1220 (void) platform_device_register(&omap_mpuio_device);
1221}
1222
1223#else
1224static inline void mpuio_init(void) {}
1225#endif /* 16xx */
1226
e5c56ed3
DB		 1227#else
1228
1229extern struct irq_chip mpuio_irq_chip;
1230
1231#define bank_is_mpuio(bank) 0
11a78b79 1232static inline void mpuio_init(void) {}
e5c56ed3
DB		 1233
1234#endif
1235
1236/*---------------------------------------------------------------------*/
5e1c5ff4 1237
52e31344
DB		 1238/* REVISIT these are stupid implementations! replace by ones that
1239 * don't switch on METHOD_* and which mostly avoid spinlocks
1240 */
1241
1242static int gpio_input(struct gpio_chip *chip, unsigned offset)
1243{
1244 struct gpio_bank *bank;
1245 unsigned long flags;
1246
1247 bank = container_of(chip, struct gpio_bank, chip);
1248 spin_lock_irqsave(&bank->lock, flags);
1249 _set_gpio_direction(bank, offset, 1);
1250 spin_unlock_irqrestore(&bank->lock, flags);
1251 return 0;
1252}
1253
1254static int gpio_get(struct gpio_chip *chip, unsigned offset)
1255{
1256 return omap_get_gpio_datain(chip->base + offset);
1257}
1258
1259static int gpio_output(struct gpio_chip *chip, unsigned offset, int value)
1260{
1261 struct gpio_bank *bank;
1262 unsigned long flags;
1263
1264 bank = container_of(chip, struct gpio_bank, chip);
1265 spin_lock_irqsave(&bank->lock, flags);
1266 _set_gpio_dataout(bank, offset, value);
1267 _set_gpio_direction(bank, offset, 0);
1268 spin_unlock_irqrestore(&bank->lock, flags);
1269 return 0;
1270}
1271
1272static void gpio_set(struct gpio_chip *chip, unsigned offset, int value)
1273{
1274 struct gpio_bank *bank;
1275 unsigned long flags;
1276
1277 bank = container_of(chip, struct gpio_bank, chip);
1278 spin_lock_irqsave(&bank->lock, flags);
1279 _set_gpio_dataout(bank, offset, value);
1280 spin_unlock_irqrestore(&bank->lock, flags);
1281}
1282
1283/*---------------------------------------------------------------------*/
1284
1a8bfa1e 1285static int initialized;
5492fb1a 1286#if !defined(CONFIG_ARCH_OMAP3)
1a8bfa1e 1287static struct clk * gpio_ick;
5492fb1a
SMK		 1288#endif
1289
1290#if defined(CONFIG_ARCH_OMAP2)
1a8bfa1e 1291static struct clk * gpio_fck;
5492fb1a 1292#endif
5e1c5ff4 1293
5492fb1a 1294#if defined(CONFIG_ARCH_OMAP2430)
56a25641
SMK		 1295static struct clk * gpio5_ick;
1296static struct clk * gpio5_fck;
1297#endif
1298
5492fb1a
SMK		 1299#if defined(CONFIG_ARCH_OMAP3)
1300static struct clk *gpio_fclks[OMAP34XX_NR_GPIOS];
1301static struct clk *gpio_iclks[OMAP34XX_NR_GPIOS];
1302#endif
1303
8ba55c5c
DB		 1304/* This lock class tells lockdep that GPIO irqs are in a different
1305 * category than their parents, so it won't report false recursion.
1306 */
1307static struct lock_class_key gpio_lock_class;
1308
5e1c5ff4
TL		 1309static int __init _omap_gpio_init(void)
1310{
1311 int i;
52e31344 1312 int gpio = 0;
5e1c5ff4 1313 struct gpio_bank *bank;
5492fb1a
SMK		 1314#if defined(CONFIG_ARCH_OMAP3)
1315 char clk_name[11];
1316#endif
5e1c5ff4
TL		 1317
1318 initialized = 1;
1319
5492fb1a 1320#if defined(CONFIG_ARCH_OMAP1)
6e60e79a 1321 if (cpu_is_omap15xx()) {
1a8bfa1e
TL		 1322 gpio_ick = clk_get(NULL, "arm_gpio_ck");
1323 if (IS_ERR(gpio_ick))
92105bb7
TL		 1324 printk("Could not get arm_gpio_ck\n");
1325 else
30ff720b 1326 clk_enable(gpio_ick);
1a8bfa1e 1327 }
5492fb1a
SMK		 1328#endif
1329#if defined(CONFIG_ARCH_OMAP2)
1330 if (cpu_class_is_omap2()) {
1a8bfa1e
TL		 1331 gpio_ick = clk_get(NULL, "gpios_ick");
1332 if (IS_ERR(gpio_ick))
1333 printk("Could not get gpios_ick\n");
1334 else
30ff720b 1335 clk_enable(gpio_ick);
1a8bfa1e 1336 gpio_fck = clk_get(NULL, "gpios_fck");
1630b52d 1337 if (IS_ERR(gpio_fck))
1a8bfa1e
TL		 1338 printk("Could not get gpios_fck\n");
1339 else
30ff720b 1340 clk_enable(gpio_fck);
56a25641
SMK		 1341
1342 /*
5492fb1a 1343 * On 2430 & 3430 GPIO 5 uses CORE L4 ICLK
56a25641 1344 */
5492fb1a 1345#if defined(CONFIG_ARCH_OMAP2430)
56a25641
SMK		 1346 if (cpu_is_omap2430()) {
1347 gpio5_ick = clk_get(NULL, "gpio5_ick");
1348 if (IS_ERR(gpio5_ick))
1349 printk("Could not get gpio5_ick\n");
1350 else
1351 clk_enable(gpio5_ick);
1352 gpio5_fck = clk_get(NULL, "gpio5_fck");
1353 if (IS_ERR(gpio5_fck))
1354 printk("Could not get gpio5_fck\n");
1355 else
1356 clk_enable(gpio5_fck);
1357 }
1358#endif
5492fb1a
SMK		 1359 }
1360#endif
1361
1362#if defined(CONFIG_ARCH_OMAP3)
1363 if (cpu_is_omap34xx()) {
1364 for (i = 0; i < OMAP34XX_NR_GPIOS; i++) {
1365 sprintf(clk_name, "gpio%d_ick", i + 1);
1366 gpio_iclks[i] = clk_get(NULL, clk_name);
1367 if (IS_ERR(gpio_iclks[i]))
1368 printk(KERN_ERR "Could not get %s\n", clk_name);
1369 else
1370 clk_enable(gpio_iclks[i]);
1371 sprintf(clk_name, "gpio%d_fck", i + 1);
1372 gpio_fclks[i] = clk_get(NULL, clk_name);
1373 if (IS_ERR(gpio_fclks[i]))
1374 printk(KERN_ERR "Could not get %s\n", clk_name);
1375 else
1376 clk_enable(gpio_fclks[i]);
1377 }
1378 }
1379#endif
1380
92105bb7 1381
1a8bfa1e 1382#ifdef CONFIG_ARCH_OMAP15XX
6e60e79a 1383 if (cpu_is_omap15xx()) {
5e1c5ff4
TL		 1384 printk(KERN_INFO "OMAP1510 GPIO hardware\n");
1385 gpio_bank_count = 2;
1386 gpio_bank = gpio_bank_1510;
1387 }
1388#endif
1389#if defined(CONFIG_ARCH_OMAP16XX)
1390 if (cpu_is_omap16xx()) {
92105bb7 1391 u32 rev;
5e1c5ff4
TL		 1392
1393 gpio_bank_count = 5;
1394 gpio_bank = gpio_bank_1610;
1395 rev = omap_readw(gpio_bank[1].base + OMAP1610_GPIO_REVISION);
1396 printk(KERN_INFO "OMAP GPIO hardware version %d.%d\n",
1397 (rev >> 4) & 0x0f, rev & 0x0f);
1398 }
1399#endif
1400#ifdef CONFIG_ARCH_OMAP730
1401 if (cpu_is_omap730()) {
1402 printk(KERN_INFO "OMAP730 GPIO hardware\n");
1403 gpio_bank_count = 7;
1404 gpio_bank = gpio_bank_730;
1405 }
92105bb7 1406#endif
56a25641 1407
92105bb7 1408#ifdef CONFIG_ARCH_OMAP24XX
56a25641 1409 if (cpu_is_omap242x()) {
92105bb7
TL		 1410 int rev;
1411
1412 gpio_bank_count = 4;
56a25641
SMK		 1413 gpio_bank = gpio_bank_242x;
1414 rev = omap_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
1415 printk(KERN_INFO "OMAP242x GPIO hardware version %d.%d\n",
1416 (rev >> 4) & 0x0f, rev & 0x0f);
1417 }
1418 if (cpu_is_omap243x()) {
1419 int rev;
1420
1421 gpio_bank_count = 5;
1422 gpio_bank = gpio_bank_243x;
92105bb7 1423 rev = omap_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
56a25641 1424 printk(KERN_INFO "OMAP243x GPIO hardware version %d.%d\n",
92105bb7
TL		 1425 (rev >> 4) & 0x0f, rev & 0x0f);
1426 }
5492fb1a
SMK		 1427#endif
1428#ifdef CONFIG_ARCH_OMAP34XX
1429 if (cpu_is_omap34xx()) {
1430 int rev;
1431
1432 gpio_bank_count = OMAP34XX_NR_GPIOS;
1433 gpio_bank = gpio_bank_34xx;
1434 rev = omap_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
1435 printk(KERN_INFO "OMAP34xx GPIO hardware version %d.%d\n",
1436 (rev >> 4) & 0x0f, rev & 0x0f);
1437 }
5e1c5ff4
TL		 1438#endif
1439 for (i = 0; i < gpio_bank_count; i++) {
1440 int j, gpio_count = 16;
1441
1442 bank = &gpio_bank[i];
5e1c5ff4
TL		 1443 bank->base = IO_ADDRESS(bank->base);
1444 spin_lock_init(&bank->lock);
e5c56ed3 1445 if (bank_is_mpuio(bank))
5e1c5ff4 1446 omap_writew(0xFFFF, OMAP_MPUIO_BASE + OMAP_MPUIO_GPIO_MASKIT);
d11ac979 1447 if (cpu_is_omap15xx() && bank->method == METHOD_GPIO_1510) {
5e1c5ff4
TL		 1448 __raw_writew(0xffff, bank->base + OMAP1510_GPIO_INT_MASK);
1449 __raw_writew(0x0000, bank->base + OMAP1510_GPIO_INT_STATUS);
1450 }
d11ac979 1451 if (cpu_is_omap16xx() && bank->method == METHOD_GPIO_1610) {
5e1c5ff4
TL		 1452 __raw_writew(0x0000, bank->base + OMAP1610_GPIO_IRQENABLE1);
1453 __raw_writew(0xffff, bank->base + OMAP1610_GPIO_IRQSTATUS1);
92105bb7 1454 __raw_writew(0x0014, bank->base + OMAP1610_GPIO_SYSCONFIG);
5e1c5ff4 1455 }
d11ac979 1456 if (cpu_is_omap730() && bank->method == METHOD_GPIO_730) {
5e1c5ff4
TL		 1457 __raw_writel(0xffffffff, bank->base + OMAP730_GPIO_INT_MASK);
1458 __raw_writel(0x00000000, bank->base + OMAP730_GPIO_INT_STATUS);
1459
1460 gpio_count = 32; /* 730 has 32-bit GPIOs */
1461 }
d11ac979 1462
5492fb1a 1463#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
92105bb7 1464 if (bank->method == METHOD_GPIO_24XX) {
3ac4fa99
JY		 1465 static const u32 non_wakeup_gpios[] = {
1466 0xe203ffc0, 0x08700040
1467 };
1468
92105bb7
TL		 1469 __raw_writel(0x00000000, bank->base + OMAP24XX_GPIO_IRQENABLE1);
1470 __raw_writel(0xffffffff, bank->base + OMAP24XX_GPIO_IRQSTATUS1);
14f1c3bf
JY		 1471 __raw_writew(0x0015, bank->base + OMAP24XX_GPIO_SYSCONFIG);
1472
1473 /* Initialize interface clock ungated, module enabled */
1474 __raw_writel(0, bank->base + OMAP24XX_GPIO_CTRL);
3ac4fa99
JY		 1475 if (i < ARRAY_SIZE(non_wakeup_gpios))
1476 bank->non_wakeup_gpios = non_wakeup_gpios[i];
92105bb7
TL		 1477 gpio_count = 32;
1478 }
5e1c5ff4 1479#endif
52e31344
DB		 1480
1481 /* REVISIT eventually switch from OMAP-specific gpio structs
1482 * over to the generic ones
1483 */
1484 bank->chip.direction_input = gpio_input;
1485 bank->chip.get = gpio_get;
1486 bank->chip.direction_output = gpio_output;
1487 bank->chip.set = gpio_set;
1488 if (bank_is_mpuio(bank)) {
1489 bank->chip.label = "mpuio";
d8f388d8
DB		 1490#ifdef CONFIG_ARCH_OMAP1
1491 bank->chip.dev = &omap_mpuio_device.dev;
1492#endif
52e31344
DB		 1493 bank->chip.base = OMAP_MPUIO(0);
1494 } else {
1495 bank->chip.label = "gpio";
1496 bank->chip.base = gpio;
1497 gpio += gpio_count;
1498 }
1499 bank->chip.ngpio = gpio_count;
1500
1501 gpiochip_add(&bank->chip);
1502
5e1c5ff4
TL		 1503 for (j = bank->virtual_irq_start;
1504 j < bank->virtual_irq_start + gpio_count; j++) {
8ba55c5c 1505 lockdep_set_class(&irq_desc[j].lock, &gpio_lock_class);
58781016 1506 set_irq_chip_data(j, bank);
e5c56ed3 1507 if (bank_is_mpuio(bank))
5e1c5ff4
TL		 1508 set_irq_chip(j, &mpuio_irq_chip);
1509 else
1510 set_irq_chip(j, &gpio_irq_chip);
10dd5ce2 1511 set_irq_handler(j, handle_simple_irq);
5e1c5ff4
TL		 1512 set_irq_flags(j, IRQF_VALID);
1513 }
1514 set_irq_chained_handler(bank->irq, gpio_irq_handler);
1515 set_irq_data(bank->irq, bank);
1516 }
1517
1518 /* Enable system clock for GPIO module.
1519 * The CAM_CLK_CTRL *is* really the right place. */
92105bb7 1520 if (cpu_is_omap16xx())
5e1c5ff4
TL		 1521 omap_writel(omap_readl(ULPD_CAM_CLK_CTRL) | 0x04, ULPD_CAM_CLK_CTRL);
1522
14f1c3bf
JY		 1523 /* Enable autoidle for the OCP interface */
1524 if (cpu_is_omap24xx())
1525 omap_writel(1 << 0, 0x48019010);
5492fb1a
SMK		 1526 if (cpu_is_omap34xx())
1527 omap_writel(1 << 0, 0x48306814);
d11ac979 1528
5e1c5ff4
TL		 1529 return 0;
1530}
1531
5492fb1a 1532#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
92105bb7
TL		 1533static int omap_gpio_suspend(struct sys_device *dev, pm_message_t mesg)
1534{
1535 int i;
1536
5492fb1a 1537 if (!cpu_class_is_omap2() && !cpu_is_omap16xx())
92105bb7
TL		 1538 return 0;
1539
1540 for (i = 0; i < gpio_bank_count; i++) {
1541 struct gpio_bank *bank = &gpio_bank[i];
1542 void __iomem *wake_status;
1543 void __iomem *wake_clear;
1544 void __iomem *wake_set;
a6472533 1545 unsigned long flags;
92105bb7
TL		 1546
1547 switch (bank->method) {
e5c56ed3 1548#ifdef CONFIG_ARCH_OMAP16XX
92105bb7
TL		 1549 case METHOD_GPIO_1610:
1550 wake_status = bank->base + OMAP1610_GPIO_WAKEUPENABLE;
1551 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1552 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1553 break;
e5c56ed3 1554#endif
5492fb1a 1555#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
92105bb7
TL		 1556 case METHOD_GPIO_24XX:
1557 wake_status = bank->base + OMAP24XX_GPIO_SETWKUENA;
1558 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1559 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
1560 break;
e5c56ed3 1561#endif
92105bb7
TL		 1562 default:
1563 continue;
1564 }
1565
a6472533 1566 spin_lock_irqsave(&bank->lock, flags);
92105bb7
TL		 1567 bank->saved_wakeup = __raw_readl(wake_status);
1568 __raw_writel(0xffffffff, wake_clear);
1569 __raw_writel(bank->suspend_wakeup, wake_set);
a6472533 1570 spin_unlock_irqrestore(&bank->lock, flags);
92105bb7
TL		 1571 }
1572
1573 return 0;
1574}
1575
1576static int omap_gpio_resume(struct sys_device *dev)
1577{
1578 int i;
1579
1580 if (!cpu_is_omap24xx() && !cpu_is_omap16xx())
1581 return 0;
1582
1583 for (i = 0; i < gpio_bank_count; i++) {
1584 struct gpio_bank *bank = &gpio_bank[i];
1585 void __iomem *wake_clear;
1586 void __iomem *wake_set;
a6472533 1587 unsigned long flags;
92105bb7
TL		 1588
1589 switch (bank->method) {
e5c56ed3 1590#ifdef CONFIG_ARCH_OMAP16XX
92105bb7
TL		 1591 case METHOD_GPIO_1610:
1592 wake_clear = bank->base + OMAP1610_GPIO_CLEAR_WAKEUPENA;
1593 wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
1594 break;
e5c56ed3 1595#endif
5492fb1a 1596#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
92105bb7 1597 case METHOD_GPIO_24XX:
0d9356cb
TL		 1598 wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
1599 wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
92105bb7 1600 break;
e5c56ed3 1601#endif
92105bb7
TL		 1602 default:
1603 continue;
1604 }
1605
a6472533 1606 spin_lock_irqsave(&bank->lock, flags);
92105bb7
TL		 1607 __raw_writel(0xffffffff, wake_clear);
1608 __raw_writel(bank->saved_wakeup, wake_set);
a6472533 1609 spin_unlock_irqrestore(&bank->lock, flags);
92105bb7
TL		 1610 }
1611
1612 return 0;
1613}
1614
1615static struct sysdev_class omap_gpio_sysclass = {
af5ca3f4 1616 .name = "gpio",
92105bb7
TL		 1617 .suspend = omap_gpio_suspend,
1618 .resume = omap_gpio_resume,
1619};
1620
1621static struct sys_device omap_gpio_device = {
1622 .id = 0,
1623 .cls = &omap_gpio_sysclass,
1624};
3ac4fa99
JY		 1625
1626#endif
1627
5492fb1a 1628#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
3ac4fa99
JY		 1629
1630static int workaround_enabled;
1631
1632void omap2_gpio_prepare_for_retention(void)
1633{
1634 int i, c = 0;
1635
1636 /* Remove triggering for all non-wakeup GPIOs. Otherwise spurious
1637 * IRQs will be generated. See OMAP2420 Errata item 1.101. */
1638 for (i = 0; i < gpio_bank_count; i++) {
1639 struct gpio_bank *bank = &gpio_bank[i];
1640 u32 l1, l2;
1641
1642 if (!(bank->enabled_non_wakeup_gpios))
1643 continue;
5492fb1a 1644#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
3ac4fa99
JY		 1645 bank->saved_datain = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN);
1646 l1 = __raw_readl(bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1647 l2 = __raw_readl(bank->base + OMAP24XX_GPIO_RISINGDETECT);
5492fb1a 1648#endif
3ac4fa99
JY		 1649 bank->saved_fallingdetect = l1;
1650 bank->saved_risingdetect = l2;
1651 l1 &= ~bank->enabled_non_wakeup_gpios;
1652 l2 &= ~bank->enabled_non_wakeup_gpios;
5492fb1a 1653#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
3ac4fa99
JY		 1654 __raw_writel(l1, bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1655 __raw_writel(l2, bank->base + OMAP24XX_GPIO_RISINGDETECT);
5492fb1a 1656#endif
3ac4fa99
JY		 1657 c++;
1658 }
1659 if (!c) {
1660 workaround_enabled = 0;
1661 return;
1662 }
1663 workaround_enabled = 1;
1664}
1665
1666void omap2_gpio_resume_after_retention(void)
1667{
1668 int i;
1669
1670 if (!workaround_enabled)
1671 return;
1672 for (i = 0; i < gpio_bank_count; i++) {
1673 struct gpio_bank *bank = &gpio_bank[i];
1674 u32 l;
1675
1676 if (!(bank->enabled_non_wakeup_gpios))
1677 continue;
5492fb1a 1678#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
3ac4fa99
JY		 1679 __raw_writel(bank->saved_fallingdetect,
1680 bank->base + OMAP24XX_GPIO_FALLINGDETECT);
1681 __raw_writel(bank->saved_risingdetect,
1682 bank->base + OMAP24XX_GPIO_RISINGDETECT);
5492fb1a 1683#endif
3ac4fa99
JY		 1684 /* Check if any of the non-wakeup interrupt GPIOs have changed
1685 * state. If so, generate an IRQ by software. This is
1686 * horribly racy, but it's the best we can do to work around
1687 * this silicon bug. */
5492fb1a 1688#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
3ac4fa99 1689 l = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN);
5492fb1a 1690#endif
3ac4fa99
JY		 1691 l ^= bank->saved_datain;
1692 l &= bank->non_wakeup_gpios;
1693 if (l) {
1694 u32 old0, old1;
5492fb1a 1695#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
3ac4fa99
JY		 1696 old0 = __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0);
1697 old1 = __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
1698 __raw_writel(old0 | l, bank->base + OMAP24XX_GPIO_LEVELDETECT0);
1699 __raw_writel(old1 | l, bank->base + OMAP24XX_GPIO_LEVELDETECT1);
1700 __raw_writel(old0, bank->base + OMAP24XX_GPIO_LEVELDETECT0);
1701 __raw_writel(old1, bank->base + OMAP24XX_GPIO_LEVELDETECT1);
5492fb1a 1702#endif
3ac4fa99
JY		 1703 }
1704 }
1705
1706}
1707
92105bb7
TL		 1708#endif
1709
5e1c5ff4
TL		 1710/*
1711 * This may get called early from board specific init
1a8bfa1e 1712 * for boards that have interrupts routed via FPGA.
5e1c5ff4 1713 */
277d58ef 1714int __init omap_gpio_init(void)
5e1c5ff4
TL		 1715{
1716 if (!initialized)
1717 return _omap_gpio_init();
1718 else
1719 return 0;
1720}
1721
92105bb7
TL		 1722static int __init omap_gpio_sysinit(void)
1723{
1724 int ret = 0;
1725
1726 if (!initialized)
1727 ret = _omap_gpio_init();
1728
11a78b79
DB		 1729 mpuio_init();
1730
5492fb1a
SMK		 1731#if defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
1732 if (cpu_is_omap16xx() || cpu_class_is_omap2()) {
92105bb7
TL		 1733 if (ret == 0) {
1734 ret = sysdev_class_register(&omap_gpio_sysclass);
1735 if (ret == 0)
1736 ret = sysdev_register(&omap_gpio_device);
1737 }
1738 }
1739#endif
1740
1741 return ret;
1742}
1743
5e1c5ff4
TL		 1744EXPORT_SYMBOL(omap_request_gpio);
1745EXPORT_SYMBOL(omap_free_gpio);
1746EXPORT_SYMBOL(omap_set_gpio_direction);
1747EXPORT_SYMBOL(omap_set_gpio_dataout);
1748EXPORT_SYMBOL(omap_get_gpio_datain);
5e1c5ff4 1749
92105bb7 1750arch_initcall(omap_gpio_sysinit);
b9772a22
DB		 1751
1752
1753#ifdef CONFIG_DEBUG_FS
1754
1755#include <linux/debugfs.h>
1756#include <linux/seq_file.h>
1757
1758static int gpio_is_input(struct gpio_bank *bank, int mask)
1759{
1760 void __iomem *reg = bank->base;
1761
1762 switch (bank->method) {
1763 case METHOD_MPUIO:
1764 reg += OMAP_MPUIO_IO_CNTL;
1765 break;
1766 case METHOD_GPIO_1510:
1767 reg += OMAP1510_GPIO_DIR_CONTROL;
1768 break;
1769 case METHOD_GPIO_1610:
1770 reg += OMAP1610_GPIO_DIRECTION;
1771 break;
1772 case METHOD_GPIO_730:
1773 reg += OMAP730_GPIO_DIR_CONTROL;
1774 break;
1775 case METHOD_GPIO_24XX:
1776 reg += OMAP24XX_GPIO_OE;
1777 break;
1778 }
1779 return __raw_readl(reg) & mask;
1780}
1781
1782
1783static int dbg_gpio_show(struct seq_file *s, void *unused)
1784{
1785 unsigned i, j, gpio;
1786
1787 for (i = 0, gpio = 0; i < gpio_bank_count; i++) {
1788 struct gpio_bank *bank = gpio_bank + i;
1789 unsigned bankwidth = 16;
1790 u32 mask = 1;
1791
e5c56ed3 1792 if (bank_is_mpuio(bank))
b9772a22 1793 gpio = OMAP_MPUIO(0);
5492fb1a 1794 else if (cpu_class_is_omap2() || cpu_is_omap730())
b9772a22
DB		 1795 bankwidth = 32;
1796
1797 for (j = 0; j < bankwidth; j++, gpio++, mask <<= 1) {
1798 unsigned irq, value, is_in, irqstat;
52e31344 1799 const char *label;
b9772a22 1800
52e31344
DB		 1801 label = gpiochip_is_requested(&bank->chip, j);
1802 if (!label)
b9772a22
DB		 1803 continue;
1804
1805 irq = bank->virtual_irq_start + j;
1806 value = omap_get_gpio_datain(gpio);
1807 is_in = gpio_is_input(bank, mask);
1808
e5c56ed3 1809 if (bank_is_mpuio(bank))
52e31344 1810 seq_printf(s, "MPUIO %2d ", j);
b9772a22 1811 else
52e31344
DB		 1812 seq_printf(s, "GPIO %3d ", gpio);
1813 seq_printf(s, "(%10s): %s %s",
1814 label,
b9772a22
DB		 1815 is_in ? "in " : "out",
1816 value ? "hi" : "lo");
1817
52e31344
DB		 1818/* FIXME for at least omap2, show pullup/pulldown state */
1819
b9772a22
DB		 1820 irqstat = irq_desc[irq].status;
1821 if (is_in && ((bank->suspend_wakeup & mask)
1822 || irqstat & IRQ_TYPE_SENSE_MASK)) {
1823 char *trigger = NULL;
1824
1825 switch (irqstat & IRQ_TYPE_SENSE_MASK) {
1826 case IRQ_TYPE_EDGE_FALLING:
1827 trigger = "falling";
1828 break;
1829 case IRQ_TYPE_EDGE_RISING:
1830 trigger = "rising";
1831 break;
1832 case IRQ_TYPE_EDGE_BOTH:
1833 trigger = "bothedge";
1834 break;
1835 case IRQ_TYPE_LEVEL_LOW:
1836 trigger = "low";
1837 break;
1838 case IRQ_TYPE_LEVEL_HIGH:
1839 trigger = "high";
1840 break;
1841 case IRQ_TYPE_NONE:
52e31344 1842 trigger = "(?)";
b9772a22
DB		 1843 break;
1844 }
52e31344 1845 seq_printf(s, ", irq-%d %-8s%s",
b9772a22
DB		 1846 irq, trigger,
1847 (bank->suspend_wakeup & mask)
1848 ? " wakeup" : "");
1849 }
1850 seq_printf(s, "\n");
1851 }
1852
e5c56ed3 1853 if (bank_is_mpuio(bank)) {
b9772a22
DB		 1854 seq_printf(s, "\n");
1855 gpio = 0;
1856 }
1857 }
1858 return 0;
1859}
1860
1861static int dbg_gpio_open(struct inode *inode, struct file *file)
1862{
e5c56ed3 1863 return single_open(file, dbg_gpio_show, &inode->i_private);
b9772a22
DB		 1864}
1865
1866static const struct file_operations debug_fops = {
1867 .open = dbg_gpio_open,
1868 .read = seq_read,
1869 .llseek = seq_lseek,
1870 .release = single_release,
1871};
1872
1873static int __init omap_gpio_debuginit(void)
1874{
e5c56ed3
DB		 1875 (void) debugfs_create_file("omap_gpio", S_IRUGO,
1876 NULL, NULL, &debug_fops);
b9772a22
DB		 1877 return 0;
1878}
1879late_initcall(omap_gpio_debuginit);
1880#endif
Linux kernel - Deliverables
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