Commit | Line | Data |
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1da177e4 | 1 | /* |
a09e64fb | 2 | * arch/arm/plat-omap/include/mach/mcbsp.h |
1da177e4 LT |
3 | * |
4 | * Defines for Multi-Channel Buffered Serial Port | |
5 | * | |
6 | * Copyright (C) 2002 RidgeRun, Inc. | |
7 | * Author: Steve Johnson | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or modify | |
10 | * it under the terms of the GNU General Public License as published by | |
11 | * the Free Software Foundation; either version 2 of the License, or | |
12 | * (at your option) any later version. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
22 | * | |
23 | */ | |
24 | #ifndef __ASM_ARCH_OMAP_MCBSP_H | |
25 | #define __ASM_ARCH_OMAP_MCBSP_H | |
26 | ||
bc5d0c89 EV |
27 | #include <linux/completion.h> |
28 | #include <linux/spinlock.h> | |
29 | ||
a09e64fb RK |
30 | #include <mach/hardware.h> |
31 | #include <mach/clock.h> | |
1da177e4 | 32 | |
7c006926 AB |
33 | #define OMAP7XX_MCBSP1_BASE 0xfffb1000 |
34 | #define OMAP7XX_MCBSP2_BASE 0xfffb1800 | |
1da177e4 LT |
35 | |
36 | #define OMAP1510_MCBSP1_BASE 0xe1011800 | |
37 | #define OMAP1510_MCBSP2_BASE 0xfffb1000 | |
38 | #define OMAP1510_MCBSP3_BASE 0xe1017000 | |
39 | ||
40 | #define OMAP1610_MCBSP1_BASE 0xe1011800 | |
41 | #define OMAP1610_MCBSP2_BASE 0xfffb1000 | |
42 | #define OMAP1610_MCBSP3_BASE 0xe1017000 | |
43 | ||
120db2cb TL |
44 | #define OMAP24XX_MCBSP1_BASE 0x48074000 |
45 | #define OMAP24XX_MCBSP2_BASE 0x48076000 | |
05228c35 JN |
46 | #define OMAP2430_MCBSP3_BASE 0x4808c000 |
47 | #define OMAP2430_MCBSP4_BASE 0x4808e000 | |
48 | #define OMAP2430_MCBSP5_BASE 0x48096000 | |
120db2cb | 49 | |
bc5d0c89 EV |
50 | #define OMAP34XX_MCBSP1_BASE 0x48074000 |
51 | #define OMAP34XX_MCBSP2_BASE 0x49022000 | |
9c8e3a0f CS |
52 | #define OMAP34XX_MCBSP3_BASE 0x49024000 |
53 | #define OMAP34XX_MCBSP4_BASE 0x49026000 | |
54 | #define OMAP34XX_MCBSP5_BASE 0x48096000 | |
bc5d0c89 | 55 | |
a5b92cc3 SR |
56 | #define OMAP44XX_MCBSP1_BASE 0x49022000 |
57 | #define OMAP44XX_MCBSP2_BASE 0x49024000 | |
58 | #define OMAP44XX_MCBSP3_BASE 0x49026000 | |
59 | #define OMAP44XX_MCBSP4_BASE 0x48074000 | |
60 | ||
bf1cb7eb | 61 | #if defined(CONFIG_ARCH_OMAP15XX) || defined(CONFIG_ARCH_OMAP16XX) || defined(CONFIG_ARCH_OMAP730) || defined(CONFIG_ARCH_OMAP850) |
120db2cb | 62 | |
1da177e4 LT |
63 | #define OMAP_MCBSP_REG_DRR2 0x00 |
64 | #define OMAP_MCBSP_REG_DRR1 0x02 | |
65 | #define OMAP_MCBSP_REG_DXR2 0x04 | |
66 | #define OMAP_MCBSP_REG_DXR1 0x06 | |
67 | #define OMAP_MCBSP_REG_SPCR2 0x08 | |
68 | #define OMAP_MCBSP_REG_SPCR1 0x0a | |
69 | #define OMAP_MCBSP_REG_RCR2 0x0c | |
70 | #define OMAP_MCBSP_REG_RCR1 0x0e | |
71 | #define OMAP_MCBSP_REG_XCR2 0x10 | |
72 | #define OMAP_MCBSP_REG_XCR1 0x12 | |
73 | #define OMAP_MCBSP_REG_SRGR2 0x14 | |
74 | #define OMAP_MCBSP_REG_SRGR1 0x16 | |
75 | #define OMAP_MCBSP_REG_MCR2 0x18 | |
76 | #define OMAP_MCBSP_REG_MCR1 0x1a | |
77 | #define OMAP_MCBSP_REG_RCERA 0x1c | |
78 | #define OMAP_MCBSP_REG_RCERB 0x1e | |
79 | #define OMAP_MCBSP_REG_XCERA 0x20 | |
80 | #define OMAP_MCBSP_REG_XCERB 0x22 | |
81 | #define OMAP_MCBSP_REG_PCR0 0x24 | |
82 | #define OMAP_MCBSP_REG_RCERC 0x26 | |
83 | #define OMAP_MCBSP_REG_RCERD 0x28 | |
84 | #define OMAP_MCBSP_REG_XCERC 0x2A | |
85 | #define OMAP_MCBSP_REG_XCERD 0x2C | |
86 | #define OMAP_MCBSP_REG_RCERE 0x2E | |
87 | #define OMAP_MCBSP_REG_RCERF 0x30 | |
88 | #define OMAP_MCBSP_REG_XCERE 0x32 | |
89 | #define OMAP_MCBSP_REG_XCERF 0x34 | |
90 | #define OMAP_MCBSP_REG_RCERG 0x36 | |
91 | #define OMAP_MCBSP_REG_RCERH 0x38 | |
92 | #define OMAP_MCBSP_REG_XCERG 0x3A | |
93 | #define OMAP_MCBSP_REG_XCERH 0x3C | |
94 | ||
3127f8f8 TL |
95 | /* Dummy defines, these are not available on omap1 */ |
96 | #define OMAP_MCBSP_REG_XCCR 0x00 | |
97 | #define OMAP_MCBSP_REG_RCCR 0x00 | |
98 | ||
120db2cb TL |
99 | #define AUDIO_MCBSP_DATAWRITE (OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DXR1) |
100 | #define AUDIO_MCBSP_DATAREAD (OMAP1510_MCBSP1_BASE + OMAP_MCBSP_REG_DRR1) | |
101 | ||
102 | #define AUDIO_MCBSP OMAP_MCBSP1 | |
103 | #define AUDIO_DMA_TX OMAP_DMA_MCBSP1_TX | |
104 | #define AUDIO_DMA_RX OMAP_DMA_MCBSP1_RX | |
105 | ||
a5b92cc3 SR |
106 | #elif defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \ |
107 | defined(CONFIG_ARCH_OMAP4) | |
120db2cb TL |
108 | |
109 | #define OMAP_MCBSP_REG_DRR2 0x00 | |
110 | #define OMAP_MCBSP_REG_DRR1 0x04 | |
111 | #define OMAP_MCBSP_REG_DXR2 0x08 | |
112 | #define OMAP_MCBSP_REG_DXR1 0x0C | |
b4b58f58 CS |
113 | #define OMAP_MCBSP_REG_DRR 0x00 |
114 | #define OMAP_MCBSP_REG_DXR 0x08 | |
120db2cb TL |
115 | #define OMAP_MCBSP_REG_SPCR2 0x10 |
116 | #define OMAP_MCBSP_REG_SPCR1 0x14 | |
117 | #define OMAP_MCBSP_REG_RCR2 0x18 | |
118 | #define OMAP_MCBSP_REG_RCR1 0x1C | |
119 | #define OMAP_MCBSP_REG_XCR2 0x20 | |
120 | #define OMAP_MCBSP_REG_XCR1 0x24 | |
121 | #define OMAP_MCBSP_REG_SRGR2 0x28 | |
122 | #define OMAP_MCBSP_REG_SRGR1 0x2C | |
123 | #define OMAP_MCBSP_REG_MCR2 0x30 | |
124 | #define OMAP_MCBSP_REG_MCR1 0x34 | |
125 | #define OMAP_MCBSP_REG_RCERA 0x38 | |
126 | #define OMAP_MCBSP_REG_RCERB 0x3C | |
127 | #define OMAP_MCBSP_REG_XCERA 0x40 | |
128 | #define OMAP_MCBSP_REG_XCERB 0x44 | |
129 | #define OMAP_MCBSP_REG_PCR0 0x48 | |
130 | #define OMAP_MCBSP_REG_RCERC 0x4C | |
131 | #define OMAP_MCBSP_REG_RCERD 0x50 | |
132 | #define OMAP_MCBSP_REG_XCERC 0x54 | |
133 | #define OMAP_MCBSP_REG_XCERD 0x58 | |
134 | #define OMAP_MCBSP_REG_RCERE 0x5C | |
135 | #define OMAP_MCBSP_REG_RCERF 0x60 | |
136 | #define OMAP_MCBSP_REG_XCERE 0x64 | |
137 | #define OMAP_MCBSP_REG_XCERF 0x68 | |
138 | #define OMAP_MCBSP_REG_RCERG 0x6C | |
139 | #define OMAP_MCBSP_REG_RCERH 0x70 | |
140 | #define OMAP_MCBSP_REG_XCERG 0x74 | |
141 | #define OMAP_MCBSP_REG_XCERH 0x78 | |
b4b58f58 | 142 | #define OMAP_MCBSP_REG_SYSCON 0x8C |
946a49a9 EV |
143 | #define OMAP_MCBSP_REG_THRSH2 0x90 |
144 | #define OMAP_MCBSP_REG_THRSH1 0x94 | |
145 | #define OMAP_MCBSP_REG_IRQST 0xA0 | |
146 | #define OMAP_MCBSP_REG_IRQEN 0xA4 | |
2122fdc6 | 147 | #define OMAP_MCBSP_REG_WAKEUPEN 0xA8 |
b4b58f58 CS |
148 | #define OMAP_MCBSP_REG_XCCR 0xAC |
149 | #define OMAP_MCBSP_REG_RCCR 0xB0 | |
120db2cb TL |
150 | |
151 | #define AUDIO_MCBSP_DATAWRITE (OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DXR1) | |
152 | #define AUDIO_MCBSP_DATAREAD (OMAP24XX_MCBSP2_BASE + OMAP_MCBSP_REG_DRR1) | |
153 | ||
154 | #define AUDIO_MCBSP OMAP_MCBSP2 | |
155 | #define AUDIO_DMA_TX OMAP24XX_DMA_MCBSP2_TX | |
156 | #define AUDIO_DMA_RX OMAP24XX_DMA_MCBSP2_RX | |
157 | ||
158 | #endif | |
159 | ||
1da177e4 LT |
160 | /************************** McBSP SPCR1 bit definitions ***********************/ |
161 | #define RRST 0x0001 | |
162 | #define RRDY 0x0002 | |
163 | #define RFULL 0x0004 | |
164 | #define RSYNC_ERR 0x0008 | |
165 | #define RINTM(value) ((value)<<4) /* bits 4:5 */ | |
166 | #define ABIS 0x0040 | |
167 | #define DXENA 0x0080 | |
168 | #define CLKSTP(value) ((value)<<11) /* bits 11:12 */ | |
169 | #define RJUST(value) ((value)<<13) /* bits 13:14 */ | |
b4b58f58 | 170 | #define ALB 0x8000 |
1da177e4 LT |
171 | #define DLB 0x8000 |
172 | ||
173 | /************************** McBSP SPCR2 bit definitions ***********************/ | |
174 | #define XRST 0x0001 | |
175 | #define XRDY 0x0002 | |
176 | #define XEMPTY 0x0004 | |
177 | #define XSYNC_ERR 0x0008 | |
178 | #define XINTM(value) ((value)<<4) /* bits 4:5 */ | |
179 | #define GRST 0x0040 | |
180 | #define FRST 0x0080 | |
181 | #define SOFT 0x0100 | |
182 | #define FREE 0x0200 | |
183 | ||
184 | /************************** McBSP PCR bit definitions *************************/ | |
185 | #define CLKRP 0x0001 | |
186 | #define CLKXP 0x0002 | |
187 | #define FSRP 0x0004 | |
188 | #define FSXP 0x0008 | |
189 | #define DR_STAT 0x0010 | |
190 | #define DX_STAT 0x0020 | |
191 | #define CLKS_STAT 0x0040 | |
192 | #define SCLKME 0x0080 | |
193 | #define CLKRM 0x0100 | |
194 | #define CLKXM 0x0200 | |
195 | #define FSRM 0x0400 | |
196 | #define FSXM 0x0800 | |
197 | #define RIOEN 0x1000 | |
198 | #define XIOEN 0x2000 | |
199 | #define IDLE_EN 0x4000 | |
200 | ||
201 | /************************** McBSP RCR1 bit definitions ************************/ | |
202 | #define RWDLEN1(value) ((value)<<5) /* Bits 5:7 */ | |
203 | #define RFRLEN1(value) ((value)<<8) /* Bits 8:14 */ | |
204 | ||
205 | /************************** McBSP XCR1 bit definitions ************************/ | |
206 | #define XWDLEN1(value) ((value)<<5) /* Bits 5:7 */ | |
207 | #define XFRLEN1(value) ((value)<<8) /* Bits 8:14 */ | |
208 | ||
209 | /*************************** McBSP RCR2 bit definitions ***********************/ | |
210 | #define RDATDLY(value) (value) /* Bits 0:1 */ | |
211 | #define RFIG 0x0004 | |
212 | #define RCOMPAND(value) ((value)<<3) /* Bits 3:4 */ | |
213 | #define RWDLEN2(value) ((value)<<5) /* Bits 5:7 */ | |
214 | #define RFRLEN2(value) ((value)<<8) /* Bits 8:14 */ | |
215 | #define RPHASE 0x8000 | |
216 | ||
217 | /*************************** McBSP XCR2 bit definitions ***********************/ | |
218 | #define XDATDLY(value) (value) /* Bits 0:1 */ | |
219 | #define XFIG 0x0004 | |
220 | #define XCOMPAND(value) ((value)<<3) /* Bits 3:4 */ | |
221 | #define XWDLEN2(value) ((value)<<5) /* Bits 5:7 */ | |
222 | #define XFRLEN2(value) ((value)<<8) /* Bits 8:14 */ | |
223 | #define XPHASE 0x8000 | |
224 | ||
225 | /************************* McBSP SRGR1 bit definitions ************************/ | |
226 | #define CLKGDV(value) (value) /* Bits 0:7 */ | |
227 | #define FWID(value) ((value)<<8) /* Bits 8:15 */ | |
228 | ||
229 | /************************* McBSP SRGR2 bit definitions ************************/ | |
230 | #define FPER(value) (value) /* Bits 0:11 */ | |
231 | #define FSGM 0x1000 | |
232 | #define CLKSM 0x2000 | |
233 | #define CLKSP 0x4000 | |
234 | #define GSYNC 0x8000 | |
235 | ||
236 | /************************* McBSP MCR1 bit definitions *************************/ | |
237 | #define RMCM 0x0001 | |
238 | #define RCBLK(value) ((value)<<2) /* Bits 2:4 */ | |
239 | #define RPABLK(value) ((value)<<5) /* Bits 5:6 */ | |
240 | #define RPBBLK(value) ((value)<<7) /* Bits 7:8 */ | |
241 | ||
242 | /************************* McBSP MCR2 bit definitions *************************/ | |
243 | #define XMCM(value) (value) /* Bits 0:1 */ | |
244 | #define XCBLK(value) ((value)<<2) /* Bits 2:4 */ | |
245 | #define XPABLK(value) ((value)<<5) /* Bits 5:6 */ | |
246 | #define XPBBLK(value) ((value)<<7) /* Bits 7:8 */ | |
247 | ||
b4b58f58 | 248 | /*********************** McBSP XCCR bit definitions *************************/ |
3127f8f8 TL |
249 | #define EXTCLKGATE 0x8000 |
250 | #define PPCONNECT 0x4000 | |
251 | #define DXENDLY(value) ((value)<<12) /* Bits 12:13 */ | |
252 | #define XFULL_CYCLE 0x0800 | |
b4b58f58 CS |
253 | #define DILB 0x0020 |
254 | #define XDMAEN 0x0008 | |
255 | #define XDISABLE 0x0001 | |
256 | ||
257 | /********************** McBSP RCCR bit definitions *************************/ | |
3127f8f8 | 258 | #define RFULL_CYCLE 0x0800 |
b4b58f58 CS |
259 | #define RDMAEN 0x0008 |
260 | #define RDISABLE 0x0001 | |
261 | ||
262 | /********************** McBSP SYSCONFIG bit definitions ********************/ | |
2ba93f8f | 263 | #define CLOCKACTIVITY(value) ((value)<<8) |
2122fdc6 EN |
264 | #define SIDLEMODE(value) ((value)<<3) |
265 | #define ENAWAKEUP 0x0004 | |
b4b58f58 | 266 | #define SOFTRST 0x0002 |
1da177e4 | 267 | |
98cb20e8 PU |
268 | /********************** McBSP DMA operating modes **************************/ |
269 | #define MCBSP_DMA_MODE_ELEMENT 0 | |
270 | #define MCBSP_DMA_MODE_THRESHOLD 1 | |
271 | #define MCBSP_DMA_MODE_FRAME 2 | |
272 | ||
2122fdc6 EN |
273 | /********************** McBSP WAKEUPEN bit definitions *********************/ |
274 | #define XEMPTYEOFEN 0x4000 | |
275 | #define XRDYEN 0x0400 | |
276 | #define XEOFEN 0x0200 | |
277 | #define XFSXEN 0x0100 | |
278 | #define XSYNCERREN 0x0080 | |
279 | #define RRDYEN 0x0008 | |
280 | #define REOFEN 0x0004 | |
281 | #define RFSREN 0x0002 | |
282 | #define RSYNCERREN 0x0001 | |
2122fdc6 | 283 | |
1da177e4 LT |
284 | /* we don't do multichannel for now */ |
285 | struct omap_mcbsp_reg_cfg { | |
286 | u16 spcr2; | |
287 | u16 spcr1; | |
288 | u16 rcr2; | |
289 | u16 rcr1; | |
290 | u16 xcr2; | |
291 | u16 xcr1; | |
292 | u16 srgr2; | |
293 | u16 srgr1; | |
294 | u16 mcr2; | |
295 | u16 mcr1; | |
296 | u16 pcr0; | |
297 | u16 rcerc; | |
298 | u16 rcerd; | |
299 | u16 xcerc; | |
300 | u16 xcerd; | |
301 | u16 rcere; | |
302 | u16 rcerf; | |
303 | u16 xcere; | |
304 | u16 xcerf; | |
305 | u16 rcerg; | |
306 | u16 rcerh; | |
307 | u16 xcerg; | |
308 | u16 xcerh; | |
3127f8f8 TL |
309 | u16 xccr; |
310 | u16 rccr; | |
1da177e4 LT |
311 | }; |
312 | ||
313 | typedef enum { | |
314 | OMAP_MCBSP1 = 0, | |
315 | OMAP_MCBSP2, | |
316 | OMAP_MCBSP3, | |
9c8e3a0f CS |
317 | OMAP_MCBSP4, |
318 | OMAP_MCBSP5 | |
1da177e4 LT |
319 | } omap_mcbsp_id; |
320 | ||
120db2cb TL |
321 | typedef int __bitwise omap_mcbsp_io_type_t; |
322 | #define OMAP_MCBSP_IRQ_IO ((__force omap_mcbsp_io_type_t) 1) | |
323 | #define OMAP_MCBSP_POLL_IO ((__force omap_mcbsp_io_type_t) 2) | |
324 | ||
1da177e4 LT |
325 | typedef enum { |
326 | OMAP_MCBSP_WORD_8 = 0, | |
327 | OMAP_MCBSP_WORD_12, | |
328 | OMAP_MCBSP_WORD_16, | |
329 | OMAP_MCBSP_WORD_20, | |
330 | OMAP_MCBSP_WORD_24, | |
331 | OMAP_MCBSP_WORD_32, | |
332 | } omap_mcbsp_word_length; | |
333 | ||
334 | typedef enum { | |
335 | OMAP_MCBSP_CLK_RISING = 0, | |
336 | OMAP_MCBSP_CLK_FALLING, | |
337 | } omap_mcbsp_clk_polarity; | |
338 | ||
339 | typedef enum { | |
340 | OMAP_MCBSP_FS_ACTIVE_HIGH = 0, | |
341 | OMAP_MCBSP_FS_ACTIVE_LOW, | |
342 | } omap_mcbsp_fs_polarity; | |
343 | ||
344 | typedef enum { | |
345 | OMAP_MCBSP_CLK_STP_MODE_NO_DELAY = 0, | |
346 | OMAP_MCBSP_CLK_STP_MODE_DELAY, | |
347 | } omap_mcbsp_clk_stp_mode; | |
348 | ||
349 | ||
350 | /******* SPI specific mode **********/ | |
351 | typedef enum { | |
352 | OMAP_MCBSP_SPI_MASTER = 0, | |
353 | OMAP_MCBSP_SPI_SLAVE, | |
354 | } omap_mcbsp_spi_mode; | |
355 | ||
356 | struct omap_mcbsp_spi_cfg { | |
357 | omap_mcbsp_spi_mode spi_mode; | |
358 | omap_mcbsp_clk_polarity rx_clock_polarity; | |
359 | omap_mcbsp_clk_polarity tx_clock_polarity; | |
360 | omap_mcbsp_fs_polarity fsx_polarity; | |
361 | u8 clk_div; | |
362 | omap_mcbsp_clk_stp_mode clk_stp_mode; | |
363 | omap_mcbsp_word_length word_length; | |
364 | }; | |
365 | ||
bc5d0c89 EV |
366 | /* Platform specific configuration */ |
367 | struct omap_mcbsp_ops { | |
368 | void (*request)(unsigned int); | |
369 | void (*free)(unsigned int); | |
bc5d0c89 EV |
370 | }; |
371 | ||
372 | struct omap_mcbsp_platform_data { | |
65846909 | 373 | unsigned long phys_base; |
bc5d0c89 EV |
374 | u8 dma_rx_sync, dma_tx_sync; |
375 | u16 rx_irq, tx_irq; | |
376 | struct omap_mcbsp_ops *ops; | |
a1a56f5f EV |
377 | #ifdef CONFIG_ARCH_OMAP34XX |
378 | u16 buffer_size; | |
379 | #endif | |
bc5d0c89 EV |
380 | }; |
381 | ||
382 | struct omap_mcbsp { | |
383 | struct device *dev; | |
65846909 | 384 | unsigned long phys_base; |
d592dd1a | 385 | void __iomem *io_base; |
bc5d0c89 EV |
386 | u8 id; |
387 | u8 free; | |
388 | omap_mcbsp_word_length rx_word_length; | |
389 | omap_mcbsp_word_length tx_word_length; | |
390 | ||
391 | omap_mcbsp_io_type_t io_type; /* IRQ or poll */ | |
392 | /* IRQ based TX/RX */ | |
393 | int rx_irq; | |
394 | int tx_irq; | |
395 | ||
396 | /* DMA stuff */ | |
397 | u8 dma_rx_sync; | |
398 | short dma_rx_lch; | |
399 | u8 dma_tx_sync; | |
400 | short dma_tx_lch; | |
401 | ||
402 | /* Completion queues */ | |
403 | struct completion tx_irq_completion; | |
404 | struct completion rx_irq_completion; | |
405 | struct completion tx_dma_completion; | |
406 | struct completion rx_dma_completion; | |
407 | ||
408 | /* Protect the field .free, while checking if the mcbsp is in use */ | |
409 | spinlock_t lock; | |
410 | struct omap_mcbsp_platform_data *pdata; | |
b820ce4e RK |
411 | struct clk *iclk; |
412 | struct clk *fclk; | |
a1a56f5f | 413 | #ifdef CONFIG_ARCH_OMAP34XX |
98cb20e8 | 414 | int dma_op_mode; |
a1a56f5f EV |
415 | u16 max_tx_thres; |
416 | u16 max_rx_thres; | |
417 | #endif | |
bc5d0c89 | 418 | }; |
b4b58f58 CS |
419 | extern struct omap_mcbsp **mcbsp_ptr; |
420 | extern int omap_mcbsp_count; | |
bc5d0c89 EV |
421 | |
422 | int omap_mcbsp_init(void); | |
423 | void omap_mcbsp_register_board_cfg(struct omap_mcbsp_platform_data *config, | |
424 | int size); | |
1da177e4 | 425 | void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg * config); |
7aa9ff56 EV |
426 | #ifdef CONFIG_ARCH_OMAP34XX |
427 | void omap_mcbsp_set_tx_threshold(unsigned int id, u16 threshold); | |
428 | void omap_mcbsp_set_rx_threshold(unsigned int id, u16 threshold); | |
a1a56f5f EV |
429 | u16 omap_mcbsp_get_max_tx_threshold(unsigned int id); |
430 | u16 omap_mcbsp_get_max_rx_threshold(unsigned int id); | |
98cb20e8 | 431 | int omap_mcbsp_get_dma_op_mode(unsigned int id); |
7aa9ff56 EV |
432 | #else |
433 | static inline void omap_mcbsp_set_tx_threshold(unsigned int id, u16 threshold) | |
434 | { } | |
435 | static inline void omap_mcbsp_set_rx_threshold(unsigned int id, u16 threshold) | |
436 | { } | |
a1a56f5f EV |
437 | static inline u16 omap_mcbsp_get_max_tx_threshold(unsigned int id) { return 0; } |
438 | static inline u16 omap_mcbsp_get_max_rx_threshold(unsigned int id) { return 0; } | |
98cb20e8 | 439 | static inline int omap_mcbsp_get_dma_op_mode(unsigned int id) { return 0; } |
7aa9ff56 | 440 | #endif |
1da177e4 LT |
441 | int omap_mcbsp_request(unsigned int id); |
442 | void omap_mcbsp_free(unsigned int id); | |
c12abc01 JN |
443 | void omap_mcbsp_start(unsigned int id, int tx, int rx); |
444 | void omap_mcbsp_stop(unsigned int id, int tx, int rx); | |
1da177e4 LT |
445 | void omap_mcbsp_xmit_word(unsigned int id, u32 word); |
446 | u32 omap_mcbsp_recv_word(unsigned int id); | |
447 | ||
448 | int omap_mcbsp_xmit_buffer(unsigned int id, dma_addr_t buffer, unsigned int length); | |
449 | int omap_mcbsp_recv_buffer(unsigned int id, dma_addr_t buffer, unsigned int length); | |
120db2cb TL |
450 | int omap_mcbsp_spi_master_xmit_word_poll(unsigned int id, u32 word); |
451 | int omap_mcbsp_spi_master_recv_word_poll(unsigned int id, u32 * word); | |
452 | ||
1da177e4 LT |
453 | |
454 | /* SPI specific API */ | |
455 | void omap_mcbsp_set_spi_mode(unsigned int id, const struct omap_mcbsp_spi_cfg * spi_cfg); | |
456 | ||
457 | /* Polled read/write functions */ | |
458 | int omap_mcbsp_pollread(unsigned int id, u16 * buf); | |
459 | int omap_mcbsp_pollwrite(unsigned int id, u16 buf); | |
b4b58f58 | 460 | int omap_mcbsp_set_io_type(unsigned int id, omap_mcbsp_io_type_t io_type); |
1da177e4 LT |
461 | |
462 | #endif |