[deliverable/linux.git] / arch / arm / plat-omap / include / plat / mcbsp.h

/*
 * arch/arm/plat-omap/include/mach/mcbsp.h
 *
 * Defines for Multi-Channel Buffered Serial Port
 *
 * Copyright (C) 2002 RidgeRun, Inc.
 * Author: Steve Johnson
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
 *
 */
#ifndef __ASM_ARCH_OMAP_MCBSP_H
#define __ASM_ARCH_OMAP_MCBSP_H

#include <linux/spinlock.h>

#include <mach/hardware.h>
#include <plat/clock.h>

/* macro for building platform_device for McBSP ports */
#define OMAP_MCBSP_PLATFORM_DEVICE(port_nr)		\
static struct platform_device omap_mcbsp##port_nr = {	\
	.name	= "omap-mcbsp-dai",			\
	.id	= port_nr - 1,			\
}

#define MCBSP_CONFIG_TYPE2	0x2
#define MCBSP_CONFIG_TYPE3	0x3
#define MCBSP_CONFIG_TYPE4	0x4

#define OMAP7XX_MCBSP1_BASE	0xfffb1000
#define OMAP7XX_MCBSP2_BASE	0xfffb1800

#define OMAP1510_MCBSP1_BASE	0xe1011800
#define OMAP1510_MCBSP2_BASE	0xfffb1000
#define OMAP1510_MCBSP3_BASE	0xe1017000

#define OMAP1610_MCBSP1_BASE	0xe1011800
#define OMAP1610_MCBSP2_BASE	0xfffb1000
#define OMAP1610_MCBSP3_BASE	0xe1017000

/* McBSP register numbers. Register address offset = num * reg_step */
enum {
	/* Common registers */
	OMAP_MCBSP_REG_SPCR2 = 4,
	OMAP_MCBSP_REG_SPCR1,
	OMAP_MCBSP_REG_RCR2,
	OMAP_MCBSP_REG_RCR1,
	OMAP_MCBSP_REG_XCR2,
	OMAP_MCBSP_REG_XCR1,
	OMAP_MCBSP_REG_SRGR2,
	OMAP_MCBSP_REG_SRGR1,
	OMAP_MCBSP_REG_MCR2,
	OMAP_MCBSP_REG_MCR1,
	OMAP_MCBSP_REG_RCERA,
	OMAP_MCBSP_REG_RCERB,
	OMAP_MCBSP_REG_XCERA,
	OMAP_MCBSP_REG_XCERB,
	OMAP_MCBSP_REG_PCR0,
	OMAP_MCBSP_REG_RCERC,
	OMAP_MCBSP_REG_RCERD,
	OMAP_MCBSP_REG_XCERC,
	OMAP_MCBSP_REG_XCERD,
	OMAP_MCBSP_REG_RCERE,
	OMAP_MCBSP_REG_RCERF,
	OMAP_MCBSP_REG_XCERE,
	OMAP_MCBSP_REG_XCERF,
	OMAP_MCBSP_REG_RCERG,
	OMAP_MCBSP_REG_RCERH,
	OMAP_MCBSP_REG_XCERG,
	OMAP_MCBSP_REG_XCERH,

	/* OMAP1-OMAP2420 registers */
	OMAP_MCBSP_REG_DRR2 = 0,
	OMAP_MCBSP_REG_DRR1,
	OMAP_MCBSP_REG_DXR2,
	OMAP_MCBSP_REG_DXR1,

	/* OMAP2430 and onwards */
	OMAP_MCBSP_REG_DRR = 0,
	OMAP_MCBSP_REG_DXR = 2,
	OMAP_MCBSP_REG_SYSCON =	35,
	OMAP_MCBSP_REG_THRSH2,
	OMAP_MCBSP_REG_THRSH1,
	OMAP_MCBSP_REG_IRQST = 40,
	OMAP_MCBSP_REG_IRQEN,
	OMAP_MCBSP_REG_WAKEUPEN,
	OMAP_MCBSP_REG_XCCR,
	OMAP_MCBSP_REG_RCCR,
	OMAP_MCBSP_REG_XBUFFSTAT,
	OMAP_MCBSP_REG_RBUFFSTAT,
	OMAP_MCBSP_REG_SSELCR,
};

/* OMAP3 sidetone control registers */
#define OMAP_ST_REG_REV		0x00
#define OMAP_ST_REG_SYSCONFIG	0x10
#define OMAP_ST_REG_IRQSTATUS	0x18
#define OMAP_ST_REG_IRQENABLE	0x1C
#define OMAP_ST_REG_SGAINCR	0x24
#define OMAP_ST_REG_SFIRCR	0x28
#define OMAP_ST_REG_SSELCR	0x2C

/************************** McBSP SPCR1 bit definitions ***********************/
#define RRST			0x0001
#define RRDY			0x0002
#define RFULL			0x0004
#define RSYNC_ERR		0x0008
#define RINTM(value)		((value)<<4)	/* bits 4:5 */
#define ABIS			0x0040
#define DXENA			0x0080
#define CLKSTP(value)		((value)<<11)	/* bits 11:12 */
#define RJUST(value)		((value)<<13)	/* bits 13:14 */
#define ALB			0x8000
#define DLB			0x8000

/************************** McBSP SPCR2 bit definitions ***********************/
#define XRST		0x0001
#define XRDY		0x0002
#define XEMPTY		0x0004
#define XSYNC_ERR	0x0008
#define XINTM(value)	((value)<<4)		/* bits 4:5 */
#define GRST		0x0040
#define FRST		0x0080
#define SOFT		0x0100
#define FREE		0x0200

/************************** McBSP PCR bit definitions *************************/
#define CLKRP		0x0001
#define CLKXP		0x0002
#define FSRP		0x0004
#define FSXP		0x0008
#define DR_STAT		0x0010
#define DX_STAT		0x0020
#define CLKS_STAT	0x0040
#define SCLKME		0x0080
#define CLKRM		0x0100
#define CLKXM		0x0200
#define FSRM		0x0400
#define FSXM		0x0800
#define RIOEN		0x1000
#define XIOEN		0x2000
#define IDLE_EN		0x4000

/************************** McBSP RCR1 bit definitions ************************/
#define RWDLEN1(value)		((value)<<5)	/* Bits 5:7 */
#define RFRLEN1(value)		((value)<<8)	/* Bits 8:14 */

/************************** McBSP XCR1 bit definitions ************************/
#define XWDLEN1(value)		((value)<<5)	/* Bits 5:7 */
#define XFRLEN1(value)		((value)<<8)	/* Bits 8:14 */

/*************************** McBSP RCR2 bit definitions ***********************/
#define RDATDLY(value)		(value)		/* Bits 0:1 */
#define RFIG			0x0004
#define RCOMPAND(value)		((value)<<3)	/* Bits 3:4 */
#define RWDLEN2(value)		((value)<<5)	/* Bits 5:7 */
#define RFRLEN2(value)		((value)<<8)	/* Bits 8:14 */
#define RPHASE			0x8000

/*************************** McBSP XCR2 bit definitions ***********************/
#define XDATDLY(value)		(value)		/* Bits 0:1 */
#define XFIG			0x0004
#define XCOMPAND(value)		((value)<<3)	/* Bits 3:4 */
#define XWDLEN2(value)		((value)<<5)	/* Bits 5:7 */
#define XFRLEN2(value)		((value)<<8)	/* Bits 8:14 */
#define XPHASE			0x8000

/************************* McBSP SRGR1 bit definitions ************************/
#define CLKGDV(value)		(value)		/* Bits 0:7 */
#define FWID(value)		((value)<<8)	/* Bits 8:15 */

/************************* McBSP SRGR2 bit definitions ************************/
#define FPER(value)		(value)		/* Bits 0:11 */
#define FSGM			0x1000
#define CLKSM			0x2000
#define CLKSP			0x4000
#define GSYNC			0x8000

/************************* McBSP MCR1 bit definitions *************************/
#define RMCM			0x0001
#define RCBLK(value)		((value)<<2)	/* Bits 2:4 */
#define RPABLK(value)		((value)<<5)	/* Bits 5:6 */
#define RPBBLK(value)		((value)<<7)	/* Bits 7:8 */

/************************* McBSP MCR2 bit definitions *************************/
#define XMCM(value)		(value)		/* Bits 0:1 */
#define XCBLK(value)		((value)<<2)	/* Bits 2:4 */
#define XPABLK(value)		((value)<<5)	/* Bits 5:6 */
#define XPBBLK(value)		((value)<<7)	/* Bits 7:8 */

/*********************** McBSP XCCR bit definitions *************************/
#define EXTCLKGATE		0x8000
#define PPCONNECT		0x4000
#define DXENDLY(value)		((value)<<12)	/* Bits 12:13 */
#define XFULL_CYCLE		0x0800
#define DILB			0x0020
#define XDMAEN			0x0008
#define XDISABLE		0x0001

/********************** McBSP RCCR bit definitions *************************/
#define RFULL_CYCLE		0x0800
#define RDMAEN			0x0008
#define RDISABLE		0x0001

/********************** McBSP SYSCONFIG bit definitions ********************/
#define CLOCKACTIVITY(value)	((value)<<8)
#define SIDLEMODE(value)	((value)<<3)
#define ENAWAKEUP		0x0004
#define SOFTRST			0x0002

/********************** McBSP SSELCR bit definitions ***********************/
#define SIDETONEEN		0x0400

/********************** McBSP Sidetone SYSCONFIG bit definitions ***********/
#define ST_AUTOIDLE		0x0001

/********************** McBSP Sidetone SGAINCR bit definitions *************/
#define ST_CH1GAIN(value)	((value<<16))	/* Bits 16:31 */
#define ST_CH0GAIN(value)	(value)		/* Bits 0:15 */

/********************** McBSP Sidetone SFIRCR bit definitions **************/
#define ST_FIRCOEFF(value)	(value)		/* Bits 0:15 */

/********************** McBSP Sidetone SSELCR bit definitions **************/
#define ST_COEFFWRDONE		0x0004
#define ST_COEFFWREN		0x0002
#define ST_SIDETONEEN		0x0001

/********************** McBSP DMA operating modes **************************/
#define MCBSP_DMA_MODE_ELEMENT		0
#define MCBSP_DMA_MODE_THRESHOLD	1
#define MCBSP_DMA_MODE_FRAME		2

/********************** McBSP WAKEUPEN bit definitions *********************/
#define XEMPTYEOFEN		0x4000
#define XRDYEN			0x0400
#define XEOFEN			0x0200
#define XFSXEN			0x0100
#define XSYNCERREN		0x0080
#define RRDYEN			0x0008
#define REOFEN			0x0004
#define RFSREN			0x0002
#define RSYNCERREN		0x0001

/* CLKR signal muxing options */
#define CLKR_SRC_CLKR		0
#define CLKR_SRC_CLKX		1

/* FSR signal muxing options */
#define FSR_SRC_FSR		0
#define FSR_SRC_FSX		1

/* McBSP functional clock sources */
#define MCBSP_CLKS_PRCM_SRC	0
#define MCBSP_CLKS_PAD_SRC	1

/* we don't do multichannel for now */
struct omap_mcbsp_reg_cfg {
	u16 spcr2;
	u16 spcr1;
	u16 rcr2;
	u16 rcr1;
	u16 xcr2;
	u16 xcr1;
	u16 srgr2;
	u16 srgr1;
	u16 mcr2;
	u16 mcr1;
	u16 pcr0;
	u16 rcerc;
	u16 rcerd;
	u16 xcerc;
	u16 xcerd;
	u16 rcere;
	u16 rcerf;
	u16 xcere;
	u16 xcerf;
	u16 rcerg;
	u16 rcerh;
	u16 xcerg;
	u16 xcerh;
	u16 xccr;
	u16 rccr;
};

typedef enum {
	OMAP_MCBSP_WORD_8 = 0,
	OMAP_MCBSP_WORD_12,
	OMAP_MCBSP_WORD_16,
	OMAP_MCBSP_WORD_20,
	OMAP_MCBSP_WORD_24,
	OMAP_MCBSP_WORD_32,
} omap_mcbsp_word_length;

/* Platform specific configuration */
struct omap_mcbsp_ops {
	void (*request)(unsigned int);
	void (*free)(unsigned int);
	int (*set_clks_src)(u8, u8);
};

struct omap_mcbsp_platform_data {
	struct omap_mcbsp_ops *ops;
	u16 buffer_size;
	u8 reg_size;
	u8 reg_step;

	/* McBSP platform and instance specific features */
	bool has_wakeup; /* Wakeup capability */
};

struct omap_mcbsp_st_data {
	void __iomem *io_base_st;
	bool running;
	bool enabled;
	s16 taps[128];	/* Sidetone filter coefficients */
	int nr_taps;	/* Number of filter coefficients in use */
	s16 ch0gain;
	s16 ch1gain;
};

struct omap_mcbsp {
	struct device *dev;
	unsigned long phys_base;
	unsigned long phys_dma_base;
	void __iomem *io_base;
	u8 id;
	u8 free;

	int rx_irq;
	int tx_irq;

	/* DMA stuff */
	u8 dma_rx_sync;
	u8 dma_tx_sync;

	/* Protect the field .free, while checking if the mcbsp is in use */
	spinlock_t lock;
	struct omap_mcbsp_platform_data *pdata;
	struct clk *fclk;
#ifdef CONFIG_ARCH_OMAP3
	struct omap_mcbsp_st_data *st_data;
	int dma_op_mode;
	u16 max_tx_thres;
	u16 max_rx_thres;
#endif
	void *reg_cache;
};

/**
 * omap_mcbsp_dev_attr - OMAP McBSP device attributes for omap_hwmod
 * @sidetone: name of the sidetone device
 */
struct omap_mcbsp_dev_attr {
	const char *sidetone;
};

extern struct omap_mcbsp **mcbsp_ptr;
extern int omap_mcbsp_count, omap_mcbsp_cache_size;

#define omap_mcbsp_check_valid_id(id)	(id < omap_mcbsp_count)
#define id_to_mcbsp_ptr(id)		mcbsp_ptr[id];

int omap_mcbsp_init(void);
void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg * config);
#ifdef CONFIG_ARCH_OMAP3
void omap_mcbsp_set_tx_threshold(unsigned int id, u16 threshold);
void omap_mcbsp_set_rx_threshold(unsigned int id, u16 threshold);
u16 omap_mcbsp_get_max_tx_threshold(unsigned int id);
u16 omap_mcbsp_get_max_rx_threshold(unsigned int id);
u16 omap_mcbsp_get_fifo_size(unsigned int id);
u16 omap_mcbsp_get_tx_delay(unsigned int id);
u16 omap_mcbsp_get_rx_delay(unsigned int id);
int omap_mcbsp_get_dma_op_mode(unsigned int id);
#else
static inline void omap_mcbsp_set_tx_threshold(unsigned int id, u16 threshold)
{ }
static inline void omap_mcbsp_set_rx_threshold(unsigned int id, u16 threshold)
{ }
static inline u16 omap_mcbsp_get_max_tx_threshold(unsigned int id) { return 0; }
static inline u16 omap_mcbsp_get_max_rx_threshold(unsigned int id) { return 0; }
static inline u16 omap_mcbsp_get_fifo_size(unsigned int id) { return 0; }
static inline u16 omap_mcbsp_get_tx_delay(unsigned int id) { return 0; }
static inline u16 omap_mcbsp_get_rx_delay(unsigned int id) { return 0; }
static inline int omap_mcbsp_get_dma_op_mode(unsigned int id) { return 0; }
#endif
int omap_mcbsp_request(unsigned int id);
void omap_mcbsp_free(unsigned int id);
void omap_mcbsp_start(unsigned int id, int tx, int rx);
void omap_mcbsp_stop(unsigned int id, int tx, int rx);

/* McBSP functional clock source changing function */
extern int omap2_mcbsp_set_clks_src(u8 id, u8 fck_src_id);

/* McBSP signal muxing API */
void omap2_mcbsp1_mux_clkr_src(u8 mux);
void omap2_mcbsp1_mux_fsr_src(u8 mux);

int omap_mcbsp_dma_ch_params(unsigned int id, unsigned int stream);
int omap_mcbsp_dma_reg_params(unsigned int id, unsigned int stream);

#ifdef CONFIG_ARCH_OMAP3
/* Sidetone specific API */
int omap_st_set_chgain(unsigned int id, int channel, s16 chgain);
int omap_st_get_chgain(unsigned int id, int channel, s16 *chgain);
int omap_st_enable(unsigned int id);
int omap_st_disable(unsigned int id);
int omap_st_is_enabled(unsigned int id);
#else
static inline int omap_st_set_chgain(unsigned int id, int channel,
				     s16 chgain) { return 0; }
static inline int omap_st_get_chgain(unsigned int id, int channel,
				     s16 *chgain) { return 0; }
static inline int omap_st_enable(unsigned int id) { return 0; }
static inline int omap_st_disable(unsigned int id) { return 0; }
static inline int omap_st_is_enabled(unsigned int id) {  return 0; }
#endif

#endif
Commit	Line	Data
1da177e4	1	/*
a09e64fb	2	* arch/arm/plat-omap/include/mach/mcbsp.h
1da177e4 LT	3	*
	4	* Defines for Multi-Channel Buffered Serial Port
	5	*
	6	* Copyright (C) 2002 RidgeRun, Inc.
	7	* Author: Steve Johnson
	8	*
	9	* This program is free software; you can redistribute it and/or modify
	10	* it under the terms of the GNU General Public License as published by
	11	* the Free Software Foundation; either version 2 of the License, or
	12	* (at your option) any later version.
	13	*
	14	* This program is distributed in the hope that it will be useful,
	15	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	16	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	17	* GNU General Public License for more details.
	18	*
	19	* You should have received a copy of the GNU General Public License
	20	* along with this program; if not, write to the Free Software
	21	* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	22	*
	23	*/
	24	#ifndef __ASM_ARCH_OMAP_MCBSP_H
	25	#define __ASM_ARCH_OMAP_MCBSP_H
	26
bc5d0c89 EV	27	#include <linux/spinlock.h>
bc5d0c89 EV	28
a09e64fb	29	#include <mach/hardware.h>
ce491cf8	30	#include <plat/clock.h>
1da177e4	31
f0fba2ad LG	32	/* macro for building platform_device for McBSP ports */
	33	#define OMAP_MCBSP_PLATFORM_DEVICE(port_nr) \
	34	static struct platform_device omap_mcbsp##port_nr = { \
	35	.name = "omap-mcbsp-dai", \
fd1ee391	36	.id = port_nr - 1, \
f0fba2ad LG	37	}
f0fba2ad LG	38
37801b3d	39	#define MCBSP_CONFIG_TYPE2 0x2
dc48e5fc	40	#define MCBSP_CONFIG_TYPE3 0x3
cb7e9ded	41	#define MCBSP_CONFIG_TYPE4 0x4
37801b3d	42
7c006926 AB	43	#define OMAP7XX_MCBSP1_BASE 0xfffb1000
7c006926 AB	44	#define OMAP7XX_MCBSP2_BASE 0xfffb1800
1da177e4 LT	45
	46	#define OMAP1510_MCBSP1_BASE 0xe1011800
	47	#define OMAP1510_MCBSP2_BASE 0xfffb1000
	48	#define OMAP1510_MCBSP3_BASE 0xe1017000
	49
	50	#define OMAP1610_MCBSP1_BASE 0xe1011800
	51	#define OMAP1610_MCBSP2_BASE 0xfffb1000
	52	#define OMAP1610_MCBSP3_BASE 0xe1017000
	53
cdc71514 JN	54	/* McBSP register numbers. Register address offset = num * reg_step */
	55	enum {
	56	/* Common registers */
	57	OMAP_MCBSP_REG_SPCR2 = 4,
	58	OMAP_MCBSP_REG_SPCR1,
	59	OMAP_MCBSP_REG_RCR2,
	60	OMAP_MCBSP_REG_RCR1,
	61	OMAP_MCBSP_REG_XCR2,
	62	OMAP_MCBSP_REG_XCR1,
	63	OMAP_MCBSP_REG_SRGR2,
	64	OMAP_MCBSP_REG_SRGR1,
	65	OMAP_MCBSP_REG_MCR2,
	66	OMAP_MCBSP_REG_MCR1,
	67	OMAP_MCBSP_REG_RCERA,
	68	OMAP_MCBSP_REG_RCERB,
	69	OMAP_MCBSP_REG_XCERA,
	70	OMAP_MCBSP_REG_XCERB,
	71	OMAP_MCBSP_REG_PCR0,
	72	OMAP_MCBSP_REG_RCERC,
	73	OMAP_MCBSP_REG_RCERD,
	74	OMAP_MCBSP_REG_XCERC,
	75	OMAP_MCBSP_REG_XCERD,
	76	OMAP_MCBSP_REG_RCERE,
	77	OMAP_MCBSP_REG_RCERF,
	78	OMAP_MCBSP_REG_XCERE,
	79	OMAP_MCBSP_REG_XCERF,
	80	OMAP_MCBSP_REG_RCERG,
	81	OMAP_MCBSP_REG_RCERH,
	82	OMAP_MCBSP_REG_XCERG,
	83	OMAP_MCBSP_REG_XCERH,
	84
	85	/* OMAP1-OMAP2420 registers */
	86	OMAP_MCBSP_REG_DRR2 = 0,
	87	OMAP_MCBSP_REG_DRR1,
	88	OMAP_MCBSP_REG_DXR2,
	89	OMAP_MCBSP_REG_DXR1,
	90
	91	/* OMAP2430 and onwards */
	92	OMAP_MCBSP_REG_DRR = 0,
	93	OMAP_MCBSP_REG_DXR = 2,
	94	OMAP_MCBSP_REG_SYSCON = 35,
	95	OMAP_MCBSP_REG_THRSH2,
	96	OMAP_MCBSP_REG_THRSH1,
	97	OMAP_MCBSP_REG_IRQST = 40,
	98	OMAP_MCBSP_REG_IRQEN,
	99	OMAP_MCBSP_REG_WAKEUPEN,
	100	OMAP_MCBSP_REG_XCCR,
	101	OMAP_MCBSP_REG_RCCR,
	102	OMAP_MCBSP_REG_XBUFFSTAT,
	103	OMAP_MCBSP_REG_RBUFFSTAT,
	104	OMAP_MCBSP_REG_SSELCR,
	105	};
d912fa92	106
cdc71514	107	/* OMAP3 sidetone control registers */
d912fa92 EN	108	#define OMAP_ST_REG_REV 0x00
	109	#define OMAP_ST_REG_SYSCONFIG 0x10
	110	#define OMAP_ST_REG_IRQSTATUS 0x18
	111	#define OMAP_ST_REG_IRQENABLE 0x1C
	112	#define OMAP_ST_REG_SGAINCR 0x24
	113	#define OMAP_ST_REG_SFIRCR 0x28
	114	#define OMAP_ST_REG_SSELCR 0x2C
120db2cb	115
1da177e4 LT	116	/************************ McBSP SPCR1 bit definitions *********************/
	117	#define RRST 0x0001
	118	#define RRDY 0x0002
	119	#define RFULL 0x0004
	120	#define RSYNC_ERR 0x0008
	121	#define RINTM(value) ((value)<<4) /* bits 4:5 */
	122	#define ABIS 0x0040
	123	#define DXENA 0x0080
	124	#define CLKSTP(value) ((value)<<11) /* bits 11:12 */
	125	#define RJUST(value) ((value)<<13) /* bits 13:14 */
b4b58f58	126	#define ALB 0x8000
1da177e4 LT	127	#define DLB 0x8000
	128
	129	/************************ McBSP SPCR2 bit definitions *********************/
	130	#define XRST 0x0001
	131	#define XRDY 0x0002
	132	#define XEMPTY 0x0004
	133	#define XSYNC_ERR 0x0008
	134	#define XINTM(value) ((value)<<4) /* bits 4:5 */
	135	#define GRST 0x0040
	136	#define FRST 0x0080
	137	#define SOFT 0x0100
	138	#define FREE 0x0200
	139
	140	/************************ McBSP PCR bit definitions ***********************/
	141	#define CLKRP 0x0001
	142	#define CLKXP 0x0002
	143	#define FSRP 0x0004
	144	#define FSXP 0x0008
	145	#define DR_STAT 0x0010
	146	#define DX_STAT 0x0020
	147	#define CLKS_STAT 0x0040
	148	#define SCLKME 0x0080
	149	#define CLKRM 0x0100
	150	#define CLKXM 0x0200
	151	#define FSRM 0x0400
	152	#define FSXM 0x0800
	153	#define RIOEN 0x1000
	154	#define XIOEN 0x2000
	155	#define IDLE_EN 0x4000
	156
	157	/************************ McBSP RCR1 bit definitions **********************/
	158	#define RWDLEN1(value) ((value)<<5) /* Bits 5:7 */
	159	#define RFRLEN1(value) ((value)<<8) /* Bits 8:14 */
	160
	161	/************************ McBSP XCR1 bit definitions **********************/
	162	#define XWDLEN1(value) ((value)<<5) /* Bits 5:7 */
	163	#define XFRLEN1(value) ((value)<<8) /* Bits 8:14 */
	164
	165	/************************* McBSP RCR2 bit definitions *********************/
	166	#define RDATDLY(value) (value) /* Bits 0:1 */
	167	#define RFIG 0x0004
	168	#define RCOMPAND(value) ((value)<<3) /* Bits 3:4 */
	169	#define RWDLEN2(value) ((value)<<5) /* Bits 5:7 */
	170	#define RFRLEN2(value) ((value)<<8) /* Bits 8:14 */
	171	#define RPHASE 0x8000
	172
	173	/************************* McBSP XCR2 bit definitions *********************/
	174	#define XDATDLY(value) (value) /* Bits 0:1 */
	175	#define XFIG 0x0004
	176	#define XCOMPAND(value) ((value)<<3) /* Bits 3:4 */
	177	#define XWDLEN2(value) ((value)<<5) /* Bits 5:7 */
	178	#define XFRLEN2(value) ((value)<<8) /* Bits 8:14 */
	179	#define XPHASE 0x8000
	180
	181	/*********************** McBSP SRGR1 bit definitions **********************/
	182	#define CLKGDV(value) (value) /* Bits 0:7 */
	183	#define FWID(value) ((value)<<8) /* Bits 8:15 */
	184
	185	/*********************** McBSP SRGR2 bit definitions **********************/
	186	#define FPER(value) (value) /* Bits 0:11 */
	187	#define FSGM 0x1000
	188	#define CLKSM 0x2000
	189	#define CLKSP 0x4000
	190	#define GSYNC 0x8000
191
192	/*********************** McBSP MCR1 bit definitions ***********************/
193	#define RMCM 0x0001
194	#define RCBLK(value) ((value)<<2) /* Bits 2:4 */
195	#define RPABLK(value) ((value)<<5) /* Bits 5:6 */
196	#define RPBBLK(value) ((value)<<7) /* Bits 7:8 */
197
198	/*********************** McBSP MCR2 bit definitions ***********************/
199	#define XMCM(value) (value) /* Bits 0:1 */
200	#define XCBLK(value) ((value)<<2) /* Bits 2:4 */
201	#define XPABLK(value) ((value)<<5) /* Bits 5:6 */
202	#define XPBBLK(value) ((value)<<7) /* Bits 7:8 */
203
b4b58f58	204	/********************* McBSP XCCR bit definitions ***********************/
3127f8f8 TL	205	#define EXTCLKGATE 0x8000
	206	#define PPCONNECT 0x4000
	207	#define DXENDLY(value) ((value)<<12) /* Bits 12:13 */
	208	#define XFULL_CYCLE 0x0800
b4b58f58 CS	209	#define DILB 0x0020
	210	#define XDMAEN 0x0008
	211	#define XDISABLE 0x0001
	212
	213	/******************** McBSP RCCR bit definitions ***********************/
3127f8f8	214	#define RFULL_CYCLE 0x0800
b4b58f58 CS	215	#define RDMAEN 0x0008
	216	#define RDISABLE 0x0001
	217
	218	/******************** McBSP SYSCONFIG bit definitions ******************/
2ba93f8f	219	#define CLOCKACTIVITY(value) ((value)<<8)
2122fdc6 EN	220	#define SIDLEMODE(value) ((value)<<3)
2122fdc6 EN	221	#define ENAWAKEUP 0x0004
b4b58f58	222	#define SOFTRST 0x0002
1da177e4	223
d912fa92 EN	224	/******************** McBSP SSELCR bit definitions *********************/
	225	#define SIDETONEEN 0x0400
	226
	227	/******************** McBSP Sidetone SYSCONFIG bit definitions *********/
	228	#define ST_AUTOIDLE 0x0001
	229
	230	/******************** McBSP Sidetone SGAINCR bit definitions ***********/
	231	#define ST_CH1GAIN(value) ((value<<16)) /* Bits 16:31 */
	232	#define ST_CH0GAIN(value) (value) /* Bits 0:15 */
	233
	234	/******************** McBSP Sidetone SFIRCR bit definitions ************/
	235	#define ST_FIRCOEFF(value) (value) /* Bits 0:15 */
	236
	237	/******************** McBSP Sidetone SSELCR bit definitions ************/
	238	#define ST_COEFFWRDONE 0x0004
	239	#define ST_COEFFWREN 0x0002
	240	#define ST_SIDETONEEN 0x0001
	241
98cb20e8 PU	242	/******************** McBSP DMA operating modes ************************/
	243	#define MCBSP_DMA_MODE_ELEMENT 0
	244	#define MCBSP_DMA_MODE_THRESHOLD 1
	245	#define MCBSP_DMA_MODE_FRAME 2
	246
2122fdc6 EN	247	/******************** McBSP WAKEUPEN bit definitions *******************/
	248	#define XEMPTYEOFEN 0x4000
	249	#define XRDYEN 0x0400
	250	#define XEOFEN 0x0200
	251	#define XFSXEN 0x0100
	252	#define XSYNCERREN 0x0080
	253	#define RRDYEN 0x0008
	254	#define REOFEN 0x0004
	255	#define RFSREN 0x0002
	256	#define RSYNCERREN 0x0001
2122fdc6	257
cf4c87ab PW	258	/* CLKR signal muxing options */
	259	#define CLKR_SRC_CLKR 0
	260	#define CLKR_SRC_CLKX 1
	261
	262	/* FSR signal muxing options */
	263	#define FSR_SRC_FSR 0
	264	#define FSR_SRC_FSX 1
	265
d1358657	266	/* McBSP functional clock sources */
e4cc41d7 JN	267	#define MCBSP_CLKS_PRCM_SRC 0
e4cc41d7 JN	268	#define MCBSP_CLKS_PAD_SRC 1
d1358657	269
1da177e4 LT	270	/* we don't do multichannel for now */
	271	struct omap_mcbsp_reg_cfg {
	272	u16 spcr2;
	273	u16 spcr1;
	274	u16 rcr2;
	275	u16 rcr1;
	276	u16 xcr2;
	277	u16 xcr1;
	278	u16 srgr2;
	279	u16 srgr1;
	280	u16 mcr2;
	281	u16 mcr1;
	282	u16 pcr0;
	283	u16 rcerc;
	284	u16 rcerd;
	285	u16 xcerc;
	286	u16 xcerd;
	287	u16 rcere;
	288	u16 rcerf;
	289	u16 xcere;
	290	u16 xcerf;
	291	u16 rcerg;
	292	u16 rcerh;
	293	u16 xcerg;
	294	u16 xcerh;
3127f8f8 TL	295	u16 xccr;
3127f8f8 TL	296	u16 rccr;
1da177e4 LT	297	};
1da177e4 LT	298
1da177e4 LT	299	typedef enum {
	300	OMAP_MCBSP_WORD_8 = 0,
	301	OMAP_MCBSP_WORD_12,
	302	OMAP_MCBSP_WORD_16,
	303	OMAP_MCBSP_WORD_20,
	304	OMAP_MCBSP_WORD_24,
	305	OMAP_MCBSP_WORD_32,
	306	} omap_mcbsp_word_length;
	307
bc5d0c89 EV	308	/* Platform specific configuration */
	309	struct omap_mcbsp_ops {
	310	void (*request)(unsigned int);
	311	void (*free)(unsigned int);
d1358657	312	int (*set_clks_src)(u8, u8);
bc5d0c89 EV	313	};
	314
	315	struct omap_mcbsp_platform_data {
bc5d0c89	316	struct omap_mcbsp_ops *ops;
64bcbd33	317	u16 buffer_size;
cdc71514 JN	318	u8 reg_size;
cdc71514 JN	319	u8 reg_step;
1a645884 JN	320
	321	/* McBSP platform and instance specific features */
	322	bool has_wakeup; /* Wakeup capability */
bc5d0c89 EV	323	};
bc5d0c89 EV	324
d912fa92 EN	325	struct omap_mcbsp_st_data {
	326	void __iomem *io_base_st;
	327	bool running;
	328	bool enabled;
	329	s16 taps[128]; /* Sidetone filter coefficients */
	330	int nr_taps; /* Number of filter coefficients in use */
	331	s16 ch0gain;
	332	s16 ch1gain;
	333	};
	334
bc5d0c89 EV	335	struct omap_mcbsp {
bc5d0c89 EV	336	struct device *dev;
65846909	337	unsigned long phys_base;
3cf32bba	338	unsigned long phys_dma_base;
d592dd1a	339	void __iomem *io_base;
bc5d0c89 EV	340	u8 id;
bc5d0c89 EV	341	u8 free;
bc5d0c89	342
bc5d0c89 EV	343	int rx_irq;
	344	int tx_irq;
	345
	346	/* DMA stuff */
	347	u8 dma_rx_sync;
bc5d0c89	348	u8 dma_tx_sync;
bc5d0c89 EV	349
	350	/* Protect the field .free, while checking if the mcbsp is in use */
	351	spinlock_t lock;
	352	struct omap_mcbsp_platform_data *pdata;
b820ce4e	353	struct clk *fclk;
a8eb7ca0	354	#ifdef CONFIG_ARCH_OMAP3
d912fa92	355	struct omap_mcbsp_st_data *st_data;
98cb20e8	356	int dma_op_mode;
a1a56f5f EV	357	u16 max_tx_thres;
	358	u16 max_rx_thres;
	359	#endif
c8c99699	360	void *reg_cache;
bc5d0c89	361	};
8b1906f1 KVA	362
	363	/**
	364	* omap_mcbsp_dev_attr - OMAP McBSP device attributes for omap_hwmod
	365	* @sidetone: name of the sidetone device
	366	*/
	367	struct omap_mcbsp_dev_attr {
	368	const char *sidetone;
	369	};
	370
b4b58f58	371	extern struct omap_mcbsp **mcbsp_ptr;
c8c99699	372	extern int omap_mcbsp_count, omap_mcbsp_cache_size;
bc5d0c89	373
d1358657 PW	374	#define omap_mcbsp_check_valid_id(id) (id < omap_mcbsp_count)
	375	#define id_to_mcbsp_ptr(id) mcbsp_ptr[id];
	376
bc5d0c89	377	int omap_mcbsp_init(void);
1da177e4	378	void omap_mcbsp_config(unsigned int id, const struct omap_mcbsp_reg_cfg * config);
a8eb7ca0	379	#ifdef CONFIG_ARCH_OMAP3
7aa9ff56 EV	380	void omap_mcbsp_set_tx_threshold(unsigned int id, u16 threshold);
7aa9ff56 EV	381	void omap_mcbsp_set_rx_threshold(unsigned int id, u16 threshold);
a1a56f5f EV	382	u16 omap_mcbsp_get_max_tx_threshold(unsigned int id);
a1a56f5f EV	383	u16 omap_mcbsp_get_max_rx_threshold(unsigned int id);
0acce82b	384	u16 omap_mcbsp_get_fifo_size(unsigned int id);
7dc976ed PU	385	u16 omap_mcbsp_get_tx_delay(unsigned int id);
7dc976ed PU	386	u16 omap_mcbsp_get_rx_delay(unsigned int id);
98cb20e8	387	int omap_mcbsp_get_dma_op_mode(unsigned int id);
7aa9ff56 EV	388	#else
	389	static inline void omap_mcbsp_set_tx_threshold(unsigned int id, u16 threshold)
	390	{ }
	391	static inline void omap_mcbsp_set_rx_threshold(unsigned int id, u16 threshold)
	392	{ }
a1a56f5f EV	393	static inline u16 omap_mcbsp_get_max_tx_threshold(unsigned int id) { return 0; }
a1a56f5f EV	394	static inline u16 omap_mcbsp_get_max_rx_threshold(unsigned int id) { return 0; }
0acce82b	395	static inline u16 omap_mcbsp_get_fifo_size(unsigned int id) { return 0; }
7dc976ed PU	396	static inline u16 omap_mcbsp_get_tx_delay(unsigned int id) { return 0; }
7dc976ed PU	397	static inline u16 omap_mcbsp_get_rx_delay(unsigned int id) { return 0; }
98cb20e8	398	static inline int omap_mcbsp_get_dma_op_mode(unsigned int id) { return 0; }
7aa9ff56	399	#endif
1da177e4 LT	400	int omap_mcbsp_request(unsigned int id);
1da177e4 LT	401	void omap_mcbsp_free(unsigned int id);
c12abc01 JN	402	void omap_mcbsp_start(unsigned int id, int tx, int rx);
c12abc01 JN	403	void omap_mcbsp_stop(unsigned int id, int tx, int rx);
1da177e4	404
d1358657 PW	405	/* McBSP functional clock source changing function */
d1358657 PW	406	extern int omap2_mcbsp_set_clks_src(u8 id, u8 fck_src_id);
1da177e4	407
cf4c87ab PW	408	/* McBSP signal muxing API */
	409	void omap2_mcbsp1_mux_clkr_src(u8 mux);
	410	void omap2_mcbsp1_mux_fsr_src(u8 mux);
	411
9504ba64 KVA	412	int omap_mcbsp_dma_ch_params(unsigned int id, unsigned int stream);
	413	int omap_mcbsp_dma_reg_params(unsigned int id, unsigned int stream);
	414
d912fa92 EN	415	#ifdef CONFIG_ARCH_OMAP3
	416	/* Sidetone specific API */
	417	int omap_st_set_chgain(unsigned int id, int channel, s16 chgain);
	418	int omap_st_get_chgain(unsigned int id, int channel, s16 *chgain);
	419	int omap_st_enable(unsigned int id);
	420	int omap_st_disable(unsigned int id);
	421	int omap_st_is_enabled(unsigned int id);
	422	#else
	423	static inline int omap_st_set_chgain(unsigned int id, int channel,
	424	s16 chgain) { return 0; }
	425	static inline int omap_st_get_chgain(unsigned int id, int channel,
	426	s16 *chgain) { return 0; }
	427	static inline int omap_st_enable(unsigned int id) { return 0; }
	428	static inline int omap_st_disable(unsigned int id) { return 0; }
	429	static inline int omap_st_is_enabled(unsigned int id) { return 0; }
	430	#endif
	431
1da177e4	432	#endif