Commit | Line | Data |
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1da177e4 LT |
1 | // include/asm-arm/mach-omap/usb.h |
2 | ||
3 | #ifndef __ASM_ARCH_OMAP_USB_H | |
4 | #define __ASM_ARCH_OMAP_USB_H | |
5 | ||
acea7c7b | 6 | #include <linux/io.h> |
884b8369 | 7 | #include <linux/usb/musb.h> |
ce491cf8 | 8 | #include <plat/board.h> |
1da177e4 | 9 | |
83720a82 | 10 | #define OMAP3_HS_USB_PORTS 3 |
83720a82 | 11 | |
181b250c KM |
12 | enum usbhs_omap_port_mode { |
13 | OMAP_USBHS_PORT_MODE_UNUSED, | |
14 | OMAP_EHCI_PORT_MODE_PHY, | |
15 | OMAP_EHCI_PORT_MODE_TLL, | |
16 | OMAP_EHCI_PORT_MODE_HSIC, | |
95344fcc AG |
17 | OMAP_OHCI_PORT_MODE_PHY_6PIN_DATSE0, |
18 | OMAP_OHCI_PORT_MODE_PHY_6PIN_DPDM, | |
19 | OMAP_OHCI_PORT_MODE_PHY_3PIN_DATSE0, | |
20 | OMAP_OHCI_PORT_MODE_PHY_4PIN_DPDM, | |
21 | OMAP_OHCI_PORT_MODE_TLL_6PIN_DATSE0, | |
22 | OMAP_OHCI_PORT_MODE_TLL_6PIN_DPDM, | |
23 | OMAP_OHCI_PORT_MODE_TLL_3PIN_DATSE0, | |
24 | OMAP_OHCI_PORT_MODE_TLL_4PIN_DPDM, | |
25 | OMAP_OHCI_PORT_MODE_TLL_2PIN_DATSE0, | |
181b250c | 26 | OMAP_OHCI_PORT_MODE_TLL_2PIN_DPDM |
95344fcc AG |
27 | }; |
28 | ||
181b250c KM |
29 | struct usbhs_omap_board_data { |
30 | enum usbhs_omap_port_mode port_mode[OMAP3_HS_USB_PORTS]; | |
83720a82 AG |
31 | |
32 | /* have to be valid if phy_reset is true and portx is in phy mode */ | |
33 | int reset_gpio_port[OMAP3_HS_USB_PORTS]; | |
181b250c KM |
34 | |
35 | /* Set this to true for ES2.x silicon */ | |
36 | unsigned es2_compatibility:1; | |
37 | ||
38 | unsigned phy_reset:1; | |
39 | ||
40 | /* | |
41 | * Regulators for USB PHYs. | |
42 | * Each PHY can have a separate regulator. | |
43 | */ | |
44 | struct regulator *regulator[OMAP3_HS_USB_PORTS]; | |
83720a82 AG |
45 | }; |
46 | ||
b924b204 TL |
47 | #ifdef CONFIG_ARCH_OMAP2PLUS |
48 | ||
181b250c KM |
49 | struct ehci_hcd_omap_platform_data { |
50 | enum usbhs_omap_port_mode port_mode[OMAP3_HS_USB_PORTS]; | |
51 | int reset_gpio_port[OMAP3_HS_USB_PORTS]; | |
52 | struct regulator *regulator[OMAP3_HS_USB_PORTS]; | |
53 | unsigned phy_reset:1; | |
54 | }; | |
95344fcc | 55 | |
181b250c KM |
56 | struct ohci_hcd_omap_platform_data { |
57 | enum usbhs_omap_port_mode port_mode[OMAP3_HS_USB_PORTS]; | |
95344fcc AG |
58 | unsigned es2_compatibility:1; |
59 | }; | |
60 | ||
181b250c KM |
61 | struct usbhs_omap_platform_data { |
62 | enum usbhs_omap_port_mode port_mode[OMAP3_HS_USB_PORTS]; | |
63 | ||
64 | struct ehci_hcd_omap_platform_data *ehci_data; | |
65 | struct ohci_hcd_omap_platform_data *ohci_data; | |
66 | }; | |
1da177e4 LT |
67 | /*-------------------------------------------------------------------------*/ |
68 | ||
884b8369 MM |
69 | struct omap_musb_board_data { |
70 | u8 interface_type; | |
71 | u8 mode; | |
1e753451 | 72 | u16 power; |
58815fa3 | 73 | unsigned extvbus:1; |
a9c03783 AKG |
74 | void (*set_phy_power)(u8 on); |
75 | void (*clear_irq)(void); | |
76 | void (*set_mode)(u8 mode); | |
77 | void (*reset)(void); | |
884b8369 MM |
78 | }; |
79 | ||
80 | enum musb_interface {MUSB_INTERFACE_ULPI, MUSB_INTERFACE_UTMI}; | |
81 | ||
82 | extern void usb_musb_init(struct omap_musb_board_data *board_data); | |
18cb7aca | 83 | |
2236396d KM |
84 | extern void usbhs_init(const struct usbhs_omap_board_data *pdata); |
85 | ||
c33fad0c HH |
86 | extern int omap4430_phy_power(struct device *dev, int ID, int on); |
87 | extern int omap4430_phy_set_clk(struct device *dev, int on); | |
88 | extern int omap4430_phy_init(struct device *dev); | |
89 | extern int omap4430_phy_exit(struct device *dev); | |
ee896e34 | 90 | extern int omap4430_phy_suspend(struct device *dev, int suspend); |
acea7c7b | 91 | |
f4e4c324 | 92 | #endif |
1da177e4 | 93 | |
fe5a4901 HH |
94 | extern void am35x_musb_reset(void); |
95 | extern void am35x_musb_phy_power(u8 on); | |
96 | extern void am35x_musb_clear_irq(void); | |
a6d28523 | 97 | extern void am35x_set_mode(u8 musb_mode); |
8f718d24 | 98 | extern void ti81xx_musb_phy_power(u8 on); |
dd0cdd88 | 99 | |
3a0d30bc AKG |
100 | /* AM35x */ |
101 | /* USB 2.0 PHY Control */ | |
102 | #define CONF2_PHY_GPIOMODE (1 << 23) | |
103 | #define CONF2_OTGMODE (3 << 14) | |
104 | #define CONF2_NO_OVERRIDE (0 << 14) | |
105 | #define CONF2_FORCE_HOST (1 << 14) | |
106 | #define CONF2_FORCE_DEVICE (2 << 14) | |
107 | #define CONF2_FORCE_HOST_VBUS_LOW (3 << 14) | |
108 | #define CONF2_SESENDEN (1 << 13) | |
109 | #define CONF2_VBDTCTEN (1 << 12) | |
110 | #define CONF2_REFFREQ_24MHZ (2 << 8) | |
111 | #define CONF2_REFFREQ_26MHZ (7 << 8) | |
112 | #define CONF2_REFFREQ_13MHZ (6 << 8) | |
113 | #define CONF2_REFFREQ (0xf << 8) | |
114 | #define CONF2_PHYCLKGD (1 << 7) | |
115 | #define CONF2_VBUSSENSE (1 << 6) | |
116 | #define CONF2_PHY_PLLON (1 << 5) | |
117 | #define CONF2_RESET (1 << 4) | |
118 | #define CONF2_PHYPWRDN (1 << 3) | |
119 | #define CONF2_OTGPWRDN (1 << 2) | |
120 | #define CONF2_DATPOL (1 << 1) | |
1da177e4 | 121 | |
8f718d24 AKG |
122 | /* TI81XX specific definitions */ |
123 | #define USBCTRL0 0x620 | |
124 | #define USBSTAT0 0x624 | |
125 | ||
126 | /* TI816X PHY controls bits */ | |
127 | #define TI816X_USBPHY0_NORMAL_MODE (1 << 0) | |
128 | #define TI816X_USBPHY_REFCLK_OSC (1 << 8) | |
129 | ||
130 | /* TI814X PHY controls bits */ | |
131 | #define USBPHY_CM_PWRDN (1 << 0) | |
132 | #define USBPHY_OTG_PWRDN (1 << 1) | |
133 | #define USBPHY_CHGDET_DIS (1 << 2) | |
134 | #define USBPHY_CHGDET_RSTRT (1 << 3) | |
135 | #define USBPHY_SRCONDM (1 << 4) | |
136 | #define USBPHY_SINKONDP (1 << 5) | |
137 | #define USBPHY_CHGISINK_EN (1 << 6) | |
138 | #define USBPHY_CHGVSRC_EN (1 << 7) | |
139 | #define USBPHY_DMPULLUP (1 << 8) | |
140 | #define USBPHY_DPPULLUP (1 << 9) | |
141 | #define USBPHY_CDET_EXTCTL (1 << 10) | |
142 | #define USBPHY_GPIO_MODE (1 << 12) | |
143 | #define USBPHY_DPOPBUFCTL (1 << 13) | |
144 | #define USBPHY_DMOPBUFCTL (1 << 14) | |
145 | #define USBPHY_DPINPUT (1 << 15) | |
146 | #define USBPHY_DMINPUT (1 << 16) | |
147 | #define USBPHY_DPGPIO_PD (1 << 17) | |
148 | #define USBPHY_DMGPIO_PD (1 << 18) | |
149 | #define USBPHY_OTGVDET_EN (1 << 19) | |
150 | #define USBPHY_OTGSESSEND_EN (1 << 20) | |
151 | #define USBPHY_DATA_POLARITY (1 << 23) | |
152 | ||
dd0cdd88 TL |
153 | #if defined(CONFIG_ARCH_OMAP1) && defined(CONFIG_USB) |
154 | u32 omap1_usb0_init(unsigned nwires, unsigned is_device); | |
155 | u32 omap1_usb1_init(unsigned nwires); | |
156 | u32 omap1_usb2_init(unsigned nwires, unsigned alt_pingroup); | |
157 | #else | |
158 | static inline u32 omap1_usb0_init(unsigned nwires, unsigned is_device) | |
159 | { | |
160 | return 0; | |
161 | } | |
162 | static inline u32 omap1_usb1_init(unsigned nwires) | |
163 | { | |
164 | return 0; | |
165 | ||
166 | } | |
167 | static inline u32 omap1_usb2_init(unsigned nwires, unsigned alt_pingroup) | |
168 | { | |
169 | return 0; | |
170 | } | |
171 | #endif | |
172 | ||
1da177e4 | 173 | #endif /* __ASM_ARCH_OMAP_USB_H */ |