projects / deliverable / linux.git / blame
| Commit | Line | Data |
|---|---|---|
| 65fa22b7 BD |
1 | /* linux/arch/arm/plat-s3c24xx/irq-om.c |
| 2 | * | |
| e02f8664 | 3 | * Copyright (c) 2003-2004 Simtec Electronics |
| 65fa22b7 BD |
4 | * Ben Dooks <ben@simtec.co.uk> |
| 5 | * http://armlinux.simtec.co.uk/ | |
| 6 | * | |
| 7 | * S3C24XX - IRQ PM code | |
| 8 | * | |
| 9 | * This program is free software; you can redistribute it and/or modify | |
| 10 | * it under the terms of the GNU General Public License version 2 as | |
| 11 | * published by the Free Software Foundation. | |
| 12 | */ | |
| 13 | ||
| 14 | #include <linux/init.h> | |
| 15 | #include <linux/module.h> | |
| 16 | #include <linux/interrupt.h> | |
| 17 | #include <linux/sysdev.h> | |
| 57436c2d | 18 | #include <linux/irq.h> |
| 65fa22b7 BD |
19 | |
| 20 | #include <plat/cpu.h> | |
| 21 | #include <plat/pm.h> | |
| 22 | #include <plat/irq.h> | |
| 23 | ||
| 57436c2d LB |
24 | #include <asm/irq.h> |
| 25 | ||
| 65fa22b7 BD |
26 | /* state for IRQs over sleep */ |
| 27 | ||
| 28 | /* default is to allow for EINT0..EINT15, and IRQ_RTC as wakeup sources | |
| 29 | * | |
| 30 | * set bit to 1 in allow bitfield to enable the wakeup settings on it | |
| 31 | */ | |
| 32 | ||
| 33 | unsigned long s3c_irqwake_intallow = 1L << (IRQ_RTC - IRQ_EINT0) | 0xfL; | |
| 65fa22b7 | 34 | unsigned long s3c_irqwake_eintallow = 0x0000fff0L; |
| 65fa22b7 | 35 | |
| 57436c2d | 36 | int s3c_irq_wake(struct irq_data *data, unsigned int state) |
| 65fa22b7 | 37 | { |
| 57436c2d | 38 | unsigned long irqbit = 1 << (data->irq - IRQ_EINT0); |
| 65fa22b7 BD |
39 | |
| 40 | if (!(s3c_irqwake_intallow & irqbit)) | |
| 41 | return -ENOENT; | |
| 42 | ||
| 43 | printk(KERN_INFO "wake %s for irq %d\n", | |
| 57436c2d | 44 | state ? "enabled" : "disabled", data->irq); |
| 65fa22b7 BD |
45 | |
| 46 | if (!state) | |
| 47 | s3c_irqwake_intmask |= irqbit; | |
| 48 | else | |
| 49 | s3c_irqwake_intmask &= ~irqbit; | |
| 50 | ||
| 51 | return 0; | |
| 52 | } | |
| 53 | ||
| 65fa22b7 BD |
54 | static struct sleep_save irq_save[] = { |
| 55 | SAVE_ITEM(S3C2410_INTMSK), | |
| 56 | SAVE_ITEM(S3C2410_INTSUBMSK), | |
| 57 | }; | |
| 58 | ||
| 59 | /* the extint values move between the s3c2410/s3c2440 and the s3c2412 | |
| 60 | * so we use an array to hold them, and to calculate the address of | |
| 61 | * the register at run-time | |
| 62 | */ | |
| 63 | ||
| 64 | static unsigned long save_extint[3]; | |
| 65 | static unsigned long save_eintflt[4]; | |
| 66 | static unsigned long save_eintmask; | |
| 67 | ||
| 68 | int s3c24xx_irq_suspend(struct sys_device *dev, pm_message_t state) | |
| 69 | { | |
| 70 | unsigned int i; | |
| 71 | ||
| 72 | for (i = 0; i < ARRAY_SIZE(save_extint); i++) | |
| 73 | save_extint[i] = __raw_readl(S3C24XX_EXTINT0 + (i*4)); | |
| 74 | ||
| 75 | for (i = 0; i < ARRAY_SIZE(save_eintflt); i++) | |
| 76 | save_eintflt[i] = __raw_readl(S3C24XX_EINFLT0 + (i*4)); | |
| 77 | ||
| 78 | s3c_pm_do_save(irq_save, ARRAY_SIZE(irq_save)); | |
| 79 | save_eintmask = __raw_readl(S3C24XX_EINTMASK); | |
| 80 | ||
| 81 | return 0; | |
| 82 | } | |
| 83 | ||
| 84 | int s3c24xx_irq_resume(struct sys_device *dev) | |
| 85 | { | |
| 86 | unsigned int i; | |
| 87 | ||
| 88 | for (i = 0; i < ARRAY_SIZE(save_extint); i++) | |
| 89 | __raw_writel(save_extint[i], S3C24XX_EXTINT0 + (i*4)); | |
| 90 | ||
| 91 | for (i = 0; i < ARRAY_SIZE(save_eintflt); i++) | |
| 92 | __raw_writel(save_eintflt[i], S3C24XX_EINFLT0 + (i*4)); | |
| 93 | ||
| 94 | s3c_pm_do_restore(irq_save, ARRAY_SIZE(irq_save)); | |
| 95 | __raw_writel(save_eintmask, S3C24XX_EINTMASK); | |
| 96 | ||
| 97 | return 0; | |
| 98 | } |