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1 | /* linux/arch/arm/plat-s3c24xx/irq.c |
2 | * | |
3 | * Copyright (c) 2003,2004 Simtec Electronics | |
4 | * Ben Dooks <ben@simtec.co.uk> | |
5 | * | |
6 | * This program is free software; you can redistribute it and/or modify | |
7 | * it under the terms of the GNU General Public License as published by | |
8 | * the Free Software Foundation; either version 2 of the License, or | |
9 | * (at your option) any later version. | |
10 | * | |
11 | * This program is distributed in the hope that it will be useful, | |
12 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
13 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
14 | * GNU General Public License for more details. | |
15 | * | |
16 | * You should have received a copy of the GNU General Public License | |
17 | * along with this program; if not, write to the Free Software | |
18 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
19 | * | |
20 | * Changelog: | |
21 | * | |
22 | * 22-Jul-2004 Ben Dooks <ben@simtec.co.uk> | |
23 | * Fixed compile warnings | |
24 | * | |
25 | * 22-Jul-2004 Roc Wu <cooloney@yahoo.com.cn> | |
26 | * Fixed s3c_extirq_type | |
27 | * | |
28 | * 21-Jul-2004 Arnaud Patard (Rtp) <arnaud.patard@rtp-net.org> | |
29 | * Addition of ADC/TC demux | |
30 | * | |
31 | * 04-Oct-2004 Klaus Fetscher <k.fetscher@fetron.de> | |
32 | * Fix for set_irq_type() on low EINT numbers | |
33 | * | |
34 | * 05-Oct-2004 Ben Dooks <ben@simtec.co.uk> | |
35 | * Tidy up KF's patch and sort out new release | |
36 | * | |
37 | * 05-Oct-2004 Ben Dooks <ben@simtec.co.uk> | |
38 | * Add support for power management controls | |
39 | * | |
40 | * 04-Nov-2004 Ben Dooks | |
41 | * Fix standard IRQ wake for EINT0..4 and RTC | |
42 | * | |
43 | * 22-Feb-2005 Ben Dooks | |
44 | * Fixed edge-triggering on ADC IRQ | |
45 | * | |
46 | * 28-Jun-2005 Ben Dooks | |
47 | * Mark IRQ_LCD valid | |
48 | * | |
49 | * 25-Jul-2005 Ben Dooks | |
50 | * Split the S3C2440 IRQ code to seperate file | |
51 | */ | |
52 | ||
53 | #include <linux/init.h> | |
54 | #include <linux/module.h> | |
55 | #include <linux/interrupt.h> | |
56 | #include <linux/ioport.h> | |
57 | #include <linux/ptrace.h> | |
58 | #include <linux/sysdev.h> | |
59 | ||
60 | #include <asm/hardware.h> | |
61 | #include <asm/irq.h> | |
62 | #include <asm/io.h> | |
63 | ||
64 | #include <asm/mach/irq.h> | |
65 | ||
66 | #include <asm/arch/regs-irq.h> | |
67 | #include <asm/arch/regs-gpio.h> | |
68 | ||
69 | #include <asm/plat-s3c24xx/cpu.h> | |
70 | #include <asm/plat-s3c24xx/pm.h> | |
71 | #include <asm/plat-s3c24xx/irq.h> | |
72 | ||
73 | /* wakeup irq control */ | |
74 | ||
75 | #ifdef CONFIG_PM | |
76 | ||
77 | /* state for IRQs over sleep */ | |
78 | ||
79 | /* default is to allow for EINT0..EINT15, and IRQ_RTC as wakeup sources | |
80 | * | |
81 | * set bit to 1 in allow bitfield to enable the wakeup settings on it | |
82 | */ | |
83 | ||
84 | unsigned long s3c_irqwake_intallow = 1L << (IRQ_RTC - IRQ_EINT0) | 0xfL; | |
85 | unsigned long s3c_irqwake_intmask = 0xffffffffL; | |
86 | unsigned long s3c_irqwake_eintallow = 0x0000fff0L; | |
87 | unsigned long s3c_irqwake_eintmask = 0xffffffffL; | |
88 | ||
89 | int | |
90 | s3c_irq_wake(unsigned int irqno, unsigned int state) | |
91 | { | |
92 | unsigned long irqbit = 1 << (irqno - IRQ_EINT0); | |
93 | ||
94 | if (!(s3c_irqwake_intallow & irqbit)) | |
95 | return -ENOENT; | |
96 | ||
97 | printk(KERN_INFO "wake %s for irq %d\n", | |
98 | state ? "enabled" : "disabled", irqno); | |
99 | ||
100 | if (!state) | |
101 | s3c_irqwake_intmask |= irqbit; | |
102 | else | |
103 | s3c_irqwake_intmask &= ~irqbit; | |
104 | ||
105 | return 0; | |
106 | } | |
107 | ||
108 | static int | |
109 | s3c_irqext_wake(unsigned int irqno, unsigned int state) | |
110 | { | |
111 | unsigned long bit = 1L << (irqno - EXTINT_OFF); | |
112 | ||
113 | if (!(s3c_irqwake_eintallow & bit)) | |
114 | return -ENOENT; | |
115 | ||
116 | printk(KERN_INFO "wake %s for irq %d\n", | |
117 | state ? "enabled" : "disabled", irqno); | |
118 | ||
119 | if (!state) | |
120 | s3c_irqwake_eintmask |= bit; | |
121 | else | |
122 | s3c_irqwake_eintmask &= ~bit; | |
123 | ||
124 | return 0; | |
125 | } | |
126 | ||
127 | #else | |
128 | #define s3c_irqext_wake NULL | |
129 | #define s3c_irq_wake NULL | |
130 | #endif | |
131 | ||
132 | ||
133 | static void | |
134 | s3c_irq_mask(unsigned int irqno) | |
135 | { | |
136 | unsigned long mask; | |
137 | ||
138 | irqno -= IRQ_EINT0; | |
139 | ||
140 | mask = __raw_readl(S3C2410_INTMSK); | |
141 | mask |= 1UL << irqno; | |
142 | __raw_writel(mask, S3C2410_INTMSK); | |
143 | } | |
144 | ||
145 | static inline void | |
146 | s3c_irq_ack(unsigned int irqno) | |
147 | { | |
148 | unsigned long bitval = 1UL << (irqno - IRQ_EINT0); | |
149 | ||
150 | __raw_writel(bitval, S3C2410_SRCPND); | |
151 | __raw_writel(bitval, S3C2410_INTPND); | |
152 | } | |
153 | ||
154 | static inline void | |
155 | s3c_irq_maskack(unsigned int irqno) | |
156 | { | |
157 | unsigned long bitval = 1UL << (irqno - IRQ_EINT0); | |
158 | unsigned long mask; | |
159 | ||
160 | mask = __raw_readl(S3C2410_INTMSK); | |
161 | __raw_writel(mask|bitval, S3C2410_INTMSK); | |
162 | ||
163 | __raw_writel(bitval, S3C2410_SRCPND); | |
164 | __raw_writel(bitval, S3C2410_INTPND); | |
165 | } | |
166 | ||
167 | ||
168 | static void | |
169 | s3c_irq_unmask(unsigned int irqno) | |
170 | { | |
171 | unsigned long mask; | |
172 | ||
173 | if (irqno != IRQ_TIMER4 && irqno != IRQ_EINT8t23) | |
174 | irqdbf2("s3c_irq_unmask %d\n", irqno); | |
175 | ||
176 | irqno -= IRQ_EINT0; | |
177 | ||
178 | mask = __raw_readl(S3C2410_INTMSK); | |
179 | mask &= ~(1UL << irqno); | |
180 | __raw_writel(mask, S3C2410_INTMSK); | |
181 | } | |
182 | ||
183 | struct irq_chip s3c_irq_level_chip = { | |
184 | .name = "s3c-level", | |
185 | .ack = s3c_irq_maskack, | |
186 | .mask = s3c_irq_mask, | |
187 | .unmask = s3c_irq_unmask, | |
188 | .set_wake = s3c_irq_wake | |
189 | }; | |
190 | ||
191 | static struct irq_chip s3c_irq_chip = { | |
192 | .name = "s3c", | |
193 | .ack = s3c_irq_ack, | |
194 | .mask = s3c_irq_mask, | |
195 | .unmask = s3c_irq_unmask, | |
196 | .set_wake = s3c_irq_wake | |
197 | }; | |
198 | ||
199 | static void | |
200 | s3c_irqext_mask(unsigned int irqno) | |
201 | { | |
202 | unsigned long mask; | |
203 | ||
204 | irqno -= EXTINT_OFF; | |
205 | ||
206 | mask = __raw_readl(S3C24XX_EINTMASK); | |
207 | mask |= ( 1UL << irqno); | |
208 | __raw_writel(mask, S3C24XX_EINTMASK); | |
209 | } | |
210 | ||
211 | static void | |
212 | s3c_irqext_ack(unsigned int irqno) | |
213 | { | |
214 | unsigned long req; | |
215 | unsigned long bit; | |
216 | unsigned long mask; | |
217 | ||
218 | bit = 1UL << (irqno - EXTINT_OFF); | |
219 | ||
220 | mask = __raw_readl(S3C24XX_EINTMASK); | |
221 | ||
222 | __raw_writel(bit, S3C24XX_EINTPEND); | |
223 | ||
224 | req = __raw_readl(S3C24XX_EINTPEND); | |
225 | req &= ~mask; | |
226 | ||
227 | /* not sure if we should be acking the parent irq... */ | |
228 | ||
229 | if (irqno <= IRQ_EINT7 ) { | |
230 | if ((req & 0xf0) == 0) | |
231 | s3c_irq_ack(IRQ_EINT4t7); | |
232 | } else { | |
233 | if ((req >> 8) == 0) | |
234 | s3c_irq_ack(IRQ_EINT8t23); | |
235 | } | |
236 | } | |
237 | ||
238 | static void | |
239 | s3c_irqext_unmask(unsigned int irqno) | |
240 | { | |
241 | unsigned long mask; | |
242 | ||
243 | irqno -= EXTINT_OFF; | |
244 | ||
245 | mask = __raw_readl(S3C24XX_EINTMASK); | |
246 | mask &= ~( 1UL << irqno); | |
247 | __raw_writel(mask, S3C24XX_EINTMASK); | |
248 | } | |
249 | ||
250 | int | |
251 | s3c_irqext_type(unsigned int irq, unsigned int type) | |
252 | { | |
253 | void __iomem *extint_reg; | |
254 | void __iomem *gpcon_reg; | |
255 | unsigned long gpcon_offset, extint_offset; | |
256 | unsigned long newvalue = 0, value; | |
257 | ||
258 | if ((irq >= IRQ_EINT0) && (irq <= IRQ_EINT3)) | |
259 | { | |
260 | gpcon_reg = S3C2410_GPFCON; | |
261 | extint_reg = S3C24XX_EXTINT0; | |
262 | gpcon_offset = (irq - IRQ_EINT0) * 2; | |
263 | extint_offset = (irq - IRQ_EINT0) * 4; | |
264 | } | |
265 | else if ((irq >= IRQ_EINT4) && (irq <= IRQ_EINT7)) | |
266 | { | |
267 | gpcon_reg = S3C2410_GPFCON; | |
268 | extint_reg = S3C24XX_EXTINT0; | |
269 | gpcon_offset = (irq - (EXTINT_OFF)) * 2; | |
270 | extint_offset = (irq - (EXTINT_OFF)) * 4; | |
271 | } | |
272 | else if ((irq >= IRQ_EINT8) && (irq <= IRQ_EINT15)) | |
273 | { | |
274 | gpcon_reg = S3C2410_GPGCON; | |
275 | extint_reg = S3C24XX_EXTINT1; | |
276 | gpcon_offset = (irq - IRQ_EINT8) * 2; | |
277 | extint_offset = (irq - IRQ_EINT8) * 4; | |
278 | } | |
279 | else if ((irq >= IRQ_EINT16) && (irq <= IRQ_EINT23)) | |
280 | { | |
281 | gpcon_reg = S3C2410_GPGCON; | |
282 | extint_reg = S3C24XX_EXTINT2; | |
283 | gpcon_offset = (irq - IRQ_EINT8) * 2; | |
284 | extint_offset = (irq - IRQ_EINT16) * 4; | |
285 | } else | |
286 | return -1; | |
287 | ||
288 | /* Set the GPIO to external interrupt mode */ | |
289 | value = __raw_readl(gpcon_reg); | |
290 | value = (value & ~(3 << gpcon_offset)) | (0x02 << gpcon_offset); | |
291 | __raw_writel(value, gpcon_reg); | |
292 | ||
293 | /* Set the external interrupt to pointed trigger type */ | |
294 | switch (type) | |
295 | { | |
296 | case IRQT_NOEDGE: | |
297 | printk(KERN_WARNING "No edge setting!\n"); | |
298 | break; | |
299 | ||
300 | case IRQT_RISING: | |
301 | newvalue = S3C2410_EXTINT_RISEEDGE; | |
302 | break; | |
303 | ||
304 | case IRQT_FALLING: | |
305 | newvalue = S3C2410_EXTINT_FALLEDGE; | |
306 | break; | |
307 | ||
308 | case IRQT_BOTHEDGE: | |
309 | newvalue = S3C2410_EXTINT_BOTHEDGE; | |
310 | break; | |
311 | ||
312 | case IRQT_LOW: | |
313 | newvalue = S3C2410_EXTINT_LOWLEV; | |
314 | break; | |
315 | ||
316 | case IRQT_HIGH: | |
317 | newvalue = S3C2410_EXTINT_HILEV; | |
318 | break; | |
319 | ||
320 | default: | |
321 | printk(KERN_ERR "No such irq type %d", type); | |
322 | return -1; | |
323 | } | |
324 | ||
325 | value = __raw_readl(extint_reg); | |
326 | value = (value & ~(7 << extint_offset)) | (newvalue << extint_offset); | |
327 | __raw_writel(value, extint_reg); | |
328 | ||
329 | return 0; | |
330 | } | |
331 | ||
332 | static struct irq_chip s3c_irqext_chip = { | |
333 | .name = "s3c-ext", | |
334 | .mask = s3c_irqext_mask, | |
335 | .unmask = s3c_irqext_unmask, | |
336 | .ack = s3c_irqext_ack, | |
337 | .set_type = s3c_irqext_type, | |
338 | .set_wake = s3c_irqext_wake | |
339 | }; | |
340 | ||
341 | static struct irq_chip s3c_irq_eint0t4 = { | |
342 | .name = "s3c-ext0", | |
343 | .ack = s3c_irq_ack, | |
344 | .mask = s3c_irq_mask, | |
345 | .unmask = s3c_irq_unmask, | |
346 | .set_wake = s3c_irq_wake, | |
347 | .set_type = s3c_irqext_type, | |
348 | }; | |
349 | ||
350 | /* mask values for the parent registers for each of the interrupt types */ | |
351 | ||
352 | #define INTMSK_UART0 (1UL << (IRQ_UART0 - IRQ_EINT0)) | |
353 | #define INTMSK_UART1 (1UL << (IRQ_UART1 - IRQ_EINT0)) | |
354 | #define INTMSK_UART2 (1UL << (IRQ_UART2 - IRQ_EINT0)) | |
355 | #define INTMSK_ADCPARENT (1UL << (IRQ_ADCPARENT - IRQ_EINT0)) | |
356 | ||
357 | ||
358 | /* UART0 */ | |
359 | ||
360 | static void | |
361 | s3c_irq_uart0_mask(unsigned int irqno) | |
362 | { | |
363 | s3c_irqsub_mask(irqno, INTMSK_UART0, 7); | |
364 | } | |
365 | ||
366 | static void | |
367 | s3c_irq_uart0_unmask(unsigned int irqno) | |
368 | { | |
369 | s3c_irqsub_unmask(irqno, INTMSK_UART0); | |
370 | } | |
371 | ||
372 | static void | |
373 | s3c_irq_uart0_ack(unsigned int irqno) | |
374 | { | |
375 | s3c_irqsub_maskack(irqno, INTMSK_UART0, 7); | |
376 | } | |
377 | ||
378 | static struct irq_chip s3c_irq_uart0 = { | |
379 | .name = "s3c-uart0", | |
380 | .mask = s3c_irq_uart0_mask, | |
381 | .unmask = s3c_irq_uart0_unmask, | |
382 | .ack = s3c_irq_uart0_ack, | |
383 | }; | |
384 | ||
385 | /* UART1 */ | |
386 | ||
387 | static void | |
388 | s3c_irq_uart1_mask(unsigned int irqno) | |
389 | { | |
390 | s3c_irqsub_mask(irqno, INTMSK_UART1, 7 << 3); | |
391 | } | |
392 | ||
393 | static void | |
394 | s3c_irq_uart1_unmask(unsigned int irqno) | |
395 | { | |
396 | s3c_irqsub_unmask(irqno, INTMSK_UART1); | |
397 | } | |
398 | ||
399 | static void | |
400 | s3c_irq_uart1_ack(unsigned int irqno) | |
401 | { | |
402 | s3c_irqsub_maskack(irqno, INTMSK_UART1, 7 << 3); | |
403 | } | |
404 | ||
405 | static struct irq_chip s3c_irq_uart1 = { | |
406 | .name = "s3c-uart1", | |
407 | .mask = s3c_irq_uart1_mask, | |
408 | .unmask = s3c_irq_uart1_unmask, | |
409 | .ack = s3c_irq_uart1_ack, | |
410 | }; | |
411 | ||
412 | /* UART2 */ | |
413 | ||
414 | static void | |
415 | s3c_irq_uart2_mask(unsigned int irqno) | |
416 | { | |
417 | s3c_irqsub_mask(irqno, INTMSK_UART2, 7 << 6); | |
418 | } | |
419 | ||
420 | static void | |
421 | s3c_irq_uart2_unmask(unsigned int irqno) | |
422 | { | |
423 | s3c_irqsub_unmask(irqno, INTMSK_UART2); | |
424 | } | |
425 | ||
426 | static void | |
427 | s3c_irq_uart2_ack(unsigned int irqno) | |
428 | { | |
429 | s3c_irqsub_maskack(irqno, INTMSK_UART2, 7 << 6); | |
430 | } | |
431 | ||
432 | static struct irq_chip s3c_irq_uart2 = { | |
433 | .name = "s3c-uart2", | |
434 | .mask = s3c_irq_uart2_mask, | |
435 | .unmask = s3c_irq_uart2_unmask, | |
436 | .ack = s3c_irq_uart2_ack, | |
437 | }; | |
438 | ||
439 | /* ADC and Touchscreen */ | |
440 | ||
441 | static void | |
442 | s3c_irq_adc_mask(unsigned int irqno) | |
443 | { | |
444 | s3c_irqsub_mask(irqno, INTMSK_ADCPARENT, 3 << 9); | |
445 | } | |
446 | ||
447 | static void | |
448 | s3c_irq_adc_unmask(unsigned int irqno) | |
449 | { | |
450 | s3c_irqsub_unmask(irqno, INTMSK_ADCPARENT); | |
451 | } | |
452 | ||
453 | static void | |
454 | s3c_irq_adc_ack(unsigned int irqno) | |
455 | { | |
456 | s3c_irqsub_ack(irqno, INTMSK_ADCPARENT, 3 << 9); | |
457 | } | |
458 | ||
459 | static struct irq_chip s3c_irq_adc = { | |
460 | .name = "s3c-adc", | |
461 | .mask = s3c_irq_adc_mask, | |
462 | .unmask = s3c_irq_adc_unmask, | |
463 | .ack = s3c_irq_adc_ack, | |
464 | }; | |
465 | ||
466 | /* irq demux for adc */ | |
467 | static void s3c_irq_demux_adc(unsigned int irq, | |
468 | struct irq_desc *desc) | |
469 | { | |
470 | unsigned int subsrc, submsk; | |
471 | unsigned int offset = 9; | |
472 | struct irq_desc *mydesc; | |
473 | ||
474 | /* read the current pending interrupts, and the mask | |
475 | * for what it is available */ | |
476 | ||
477 | subsrc = __raw_readl(S3C2410_SUBSRCPND); | |
478 | submsk = __raw_readl(S3C2410_INTSUBMSK); | |
479 | ||
480 | subsrc &= ~submsk; | |
481 | subsrc >>= offset; | |
482 | subsrc &= 3; | |
483 | ||
484 | if (subsrc != 0) { | |
485 | if (subsrc & 1) { | |
486 | mydesc = irq_desc + IRQ_TC; | |
487 | desc_handle_irq(IRQ_TC, mydesc); | |
488 | } | |
489 | if (subsrc & 2) { | |
490 | mydesc = irq_desc + IRQ_ADC; | |
491 | desc_handle_irq(IRQ_ADC, mydesc); | |
492 | } | |
493 | } | |
494 | } | |
495 | ||
496 | static void s3c_irq_demux_uart(unsigned int start) | |
497 | { | |
498 | unsigned int subsrc, submsk; | |
499 | unsigned int offset = start - IRQ_S3CUART_RX0; | |
500 | struct irq_desc *desc; | |
501 | ||
502 | /* read the current pending interrupts, and the mask | |
503 | * for what it is available */ | |
504 | ||
505 | subsrc = __raw_readl(S3C2410_SUBSRCPND); | |
506 | submsk = __raw_readl(S3C2410_INTSUBMSK); | |
507 | ||
508 | irqdbf2("s3c_irq_demux_uart: start=%d (%d), subsrc=0x%08x,0x%08x\n", | |
509 | start, offset, subsrc, submsk); | |
510 | ||
511 | subsrc &= ~submsk; | |
512 | subsrc >>= offset; | |
513 | subsrc &= 7; | |
514 | ||
515 | if (subsrc != 0) { | |
516 | desc = irq_desc + start; | |
517 | ||
518 | if (subsrc & 1) | |
519 | desc_handle_irq(start, desc); | |
520 | ||
521 | desc++; | |
522 | ||
523 | if (subsrc & 2) | |
524 | desc_handle_irq(start+1, desc); | |
525 | ||
526 | desc++; | |
527 | ||
528 | if (subsrc & 4) | |
529 | desc_handle_irq(start+2, desc); | |
530 | } | |
531 | } | |
532 | ||
533 | /* uart demux entry points */ | |
534 | ||
535 | static void | |
536 | s3c_irq_demux_uart0(unsigned int irq, | |
537 | struct irq_desc *desc) | |
538 | { | |
539 | irq = irq; | |
540 | s3c_irq_demux_uart(IRQ_S3CUART_RX0); | |
541 | } | |
542 | ||
543 | static void | |
544 | s3c_irq_demux_uart1(unsigned int irq, | |
545 | struct irq_desc *desc) | |
546 | { | |
547 | irq = irq; | |
548 | s3c_irq_demux_uart(IRQ_S3CUART_RX1); | |
549 | } | |
550 | ||
551 | static void | |
552 | s3c_irq_demux_uart2(unsigned int irq, | |
553 | struct irq_desc *desc) | |
554 | { | |
555 | irq = irq; | |
556 | s3c_irq_demux_uart(IRQ_S3CUART_RX2); | |
557 | } | |
558 | ||
559 | static void | |
560 | s3c_irq_demux_extint8(unsigned int irq, | |
561 | struct irq_desc *desc) | |
562 | { | |
563 | unsigned long eintpnd = __raw_readl(S3C24XX_EINTPEND); | |
564 | unsigned long eintmsk = __raw_readl(S3C24XX_EINTMASK); | |
565 | ||
566 | eintpnd &= ~eintmsk; | |
567 | eintpnd &= ~0xff; /* ignore lower irqs */ | |
568 | ||
569 | /* we may as well handle all the pending IRQs here */ | |
570 | ||
571 | while (eintpnd) { | |
572 | irq = __ffs(eintpnd); | |
573 | eintpnd &= ~(1<<irq); | |
574 | ||
575 | irq += (IRQ_EINT4 - 4); | |
576 | desc_handle_irq(irq, irq_desc + irq); | |
577 | } | |
578 | ||
579 | } | |
580 | ||
581 | static void | |
582 | s3c_irq_demux_extint4t7(unsigned int irq, | |
583 | struct irq_desc *desc) | |
584 | { | |
585 | unsigned long eintpnd = __raw_readl(S3C24XX_EINTPEND); | |
586 | unsigned long eintmsk = __raw_readl(S3C24XX_EINTMASK); | |
587 | ||
588 | eintpnd &= ~eintmsk; | |
589 | eintpnd &= 0xff; /* only lower irqs */ | |
590 | ||
591 | /* we may as well handle all the pending IRQs here */ | |
592 | ||
593 | while (eintpnd) { | |
594 | irq = __ffs(eintpnd); | |
595 | eintpnd &= ~(1<<irq); | |
596 | ||
597 | irq += (IRQ_EINT4 - 4); | |
598 | ||
599 | desc_handle_irq(irq, irq_desc + irq); | |
600 | } | |
601 | } | |
602 | ||
603 | #ifdef CONFIG_PM | |
604 | ||
605 | static struct sleep_save irq_save[] = { | |
606 | SAVE_ITEM(S3C2410_INTMSK), | |
607 | SAVE_ITEM(S3C2410_INTSUBMSK), | |
608 | }; | |
609 | ||
610 | /* the extint values move between the s3c2410/s3c2440 and the s3c2412 | |
611 | * so we use an array to hold them, and to calculate the address of | |
612 | * the register at run-time | |
613 | */ | |
614 | ||
615 | static unsigned long save_extint[3]; | |
616 | static unsigned long save_eintflt[4]; | |
617 | static unsigned long save_eintmask; | |
618 | ||
619 | int s3c24xx_irq_suspend(struct sys_device *dev, pm_message_t state) | |
620 | { | |
621 | unsigned int i; | |
622 | ||
623 | for (i = 0; i < ARRAY_SIZE(save_extint); i++) | |
624 | save_extint[i] = __raw_readl(S3C24XX_EXTINT0 + (i*4)); | |
625 | ||
626 | for (i = 0; i < ARRAY_SIZE(save_eintflt); i++) | |
627 | save_eintflt[i] = __raw_readl(S3C24XX_EINFLT0 + (i*4)); | |
628 | ||
629 | s3c2410_pm_do_save(irq_save, ARRAY_SIZE(irq_save)); | |
630 | save_eintmask = __raw_readl(S3C24XX_EINTMASK); | |
631 | ||
632 | return 0; | |
633 | } | |
634 | ||
635 | int s3c24xx_irq_resume(struct sys_device *dev) | |
636 | { | |
637 | unsigned int i; | |
638 | ||
639 | for (i = 0; i < ARRAY_SIZE(save_extint); i++) | |
640 | __raw_writel(save_extint[i], S3C24XX_EXTINT0 + (i*4)); | |
641 | ||
642 | for (i = 0; i < ARRAY_SIZE(save_eintflt); i++) | |
643 | __raw_writel(save_eintflt[i], S3C24XX_EINFLT0 + (i*4)); | |
644 | ||
645 | s3c2410_pm_do_restore(irq_save, ARRAY_SIZE(irq_save)); | |
646 | __raw_writel(save_eintmask, S3C24XX_EINTMASK); | |
647 | ||
648 | return 0; | |
649 | } | |
650 | ||
651 | #else | |
652 | #define s3c24xx_irq_suspend NULL | |
653 | #define s3c24xx_irq_resume NULL | |
654 | #endif | |
655 | ||
656 | /* s3c24xx_init_irq | |
657 | * | |
658 | * Initialise S3C2410 IRQ system | |
659 | */ | |
660 | ||
661 | void __init s3c24xx_init_irq(void) | |
662 | { | |
663 | unsigned long pend; | |
664 | unsigned long last; | |
665 | int irqno; | |
666 | int i; | |
667 | ||
668 | irqdbf("s3c2410_init_irq: clearing interrupt status flags\n"); | |
669 | ||
670 | /* first, clear all interrupts pending... */ | |
671 | ||
672 | last = 0; | |
673 | for (i = 0; i < 4; i++) { | |
674 | pend = __raw_readl(S3C24XX_EINTPEND); | |
675 | ||
676 | if (pend == 0 || pend == last) | |
677 | break; | |
678 | ||
679 | __raw_writel(pend, S3C24XX_EINTPEND); | |
680 | printk("irq: clearing pending ext status %08x\n", (int)pend); | |
681 | last = pend; | |
682 | } | |
683 | ||
684 | last = 0; | |
685 | for (i = 0; i < 4; i++) { | |
686 | pend = __raw_readl(S3C2410_INTPND); | |
687 | ||
688 | if (pend == 0 || pend == last) | |
689 | break; | |
690 | ||
691 | __raw_writel(pend, S3C2410_SRCPND); | |
692 | __raw_writel(pend, S3C2410_INTPND); | |
693 | printk("irq: clearing pending status %08x\n", (int)pend); | |
694 | last = pend; | |
695 | } | |
696 | ||
697 | last = 0; | |
698 | for (i = 0; i < 4; i++) { | |
699 | pend = __raw_readl(S3C2410_SUBSRCPND); | |
700 | ||
701 | if (pend == 0 || pend == last) | |
702 | break; | |
703 | ||
704 | printk("irq: clearing subpending status %08x\n", (int)pend); | |
705 | __raw_writel(pend, S3C2410_SUBSRCPND); | |
706 | last = pend; | |
707 | } | |
708 | ||
709 | /* register the main interrupts */ | |
710 | ||
711 | irqdbf("s3c2410_init_irq: registering s3c2410 interrupt handlers\n"); | |
712 | ||
713 | for (irqno = IRQ_EINT4t7; irqno <= IRQ_ADCPARENT; irqno++) { | |
714 | /* set all the s3c2410 internal irqs */ | |
715 | ||
716 | switch (irqno) { | |
717 | /* deal with the special IRQs (cascaded) */ | |
718 | ||
719 | case IRQ_EINT4t7: | |
720 | case IRQ_EINT8t23: | |
721 | case IRQ_UART0: | |
722 | case IRQ_UART1: | |
723 | case IRQ_UART2: | |
724 | case IRQ_ADCPARENT: | |
725 | set_irq_chip(irqno, &s3c_irq_level_chip); | |
726 | set_irq_handler(irqno, handle_level_irq); | |
727 | break; | |
728 | ||
729 | case IRQ_RESERVED6: | |
730 | case IRQ_RESERVED24: | |
731 | /* no IRQ here */ | |
732 | break; | |
733 | ||
734 | default: | |
735 | //irqdbf("registering irq %d (s3c irq)\n", irqno); | |
736 | set_irq_chip(irqno, &s3c_irq_chip); | |
737 | set_irq_handler(irqno, handle_edge_irq); | |
738 | set_irq_flags(irqno, IRQF_VALID); | |
739 | } | |
740 | } | |
741 | ||
742 | /* setup the cascade irq handlers */ | |
743 | ||
744 | set_irq_chained_handler(IRQ_EINT4t7, s3c_irq_demux_extint4t7); | |
745 | set_irq_chained_handler(IRQ_EINT8t23, s3c_irq_demux_extint8); | |
746 | ||
747 | set_irq_chained_handler(IRQ_UART0, s3c_irq_demux_uart0); | |
748 | set_irq_chained_handler(IRQ_UART1, s3c_irq_demux_uart1); | |
749 | set_irq_chained_handler(IRQ_UART2, s3c_irq_demux_uart2); | |
750 | set_irq_chained_handler(IRQ_ADCPARENT, s3c_irq_demux_adc); | |
751 | ||
752 | /* external interrupts */ | |
753 | ||
754 | for (irqno = IRQ_EINT0; irqno <= IRQ_EINT3; irqno++) { | |
755 | irqdbf("registering irq %d (ext int)\n", irqno); | |
756 | set_irq_chip(irqno, &s3c_irq_eint0t4); | |
757 | set_irq_handler(irqno, handle_edge_irq); | |
758 | set_irq_flags(irqno, IRQF_VALID); | |
759 | } | |
760 | ||
761 | for (irqno = IRQ_EINT4; irqno <= IRQ_EINT23; irqno++) { | |
762 | irqdbf("registering irq %d (extended s3c irq)\n", irqno); | |
763 | set_irq_chip(irqno, &s3c_irqext_chip); | |
764 | set_irq_handler(irqno, handle_edge_irq); | |
765 | set_irq_flags(irqno, IRQF_VALID); | |
766 | } | |
767 | ||
768 | /* register the uart interrupts */ | |
769 | ||
770 | irqdbf("s3c2410: registering external interrupts\n"); | |
771 | ||
772 | for (irqno = IRQ_S3CUART_RX0; irqno <= IRQ_S3CUART_ERR0; irqno++) { | |
773 | irqdbf("registering irq %d (s3c uart0 irq)\n", irqno); | |
774 | set_irq_chip(irqno, &s3c_irq_uart0); | |
775 | set_irq_handler(irqno, handle_level_irq); | |
776 | set_irq_flags(irqno, IRQF_VALID); | |
777 | } | |
778 | ||
779 | for (irqno = IRQ_S3CUART_RX1; irqno <= IRQ_S3CUART_ERR1; irqno++) { | |
780 | irqdbf("registering irq %d (s3c uart1 irq)\n", irqno); | |
781 | set_irq_chip(irqno, &s3c_irq_uart1); | |
782 | set_irq_handler(irqno, handle_level_irq); | |
783 | set_irq_flags(irqno, IRQF_VALID); | |
784 | } | |
785 | ||
786 | for (irqno = IRQ_S3CUART_RX2; irqno <= IRQ_S3CUART_ERR2; irqno++) { | |
787 | irqdbf("registering irq %d (s3c uart2 irq)\n", irqno); | |
788 | set_irq_chip(irqno, &s3c_irq_uart2); | |
789 | set_irq_handler(irqno, handle_level_irq); | |
790 | set_irq_flags(irqno, IRQF_VALID); | |
791 | } | |
792 | ||
793 | for (irqno = IRQ_TC; irqno <= IRQ_ADC; irqno++) { | |
794 | irqdbf("registering irq %d (s3c adc irq)\n", irqno); | |
795 | set_irq_chip(irqno, &s3c_irq_adc); | |
796 | set_irq_handler(irqno, handle_edge_irq); | |
797 | set_irq_flags(irqno, IRQF_VALID); | |
798 | } | |
799 | ||
800 | irqdbf("s3c2410: registered interrupt handlers\n"); | |
801 | } |