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c116c1d7 | 1 | /* arch/arm/plat-samsung/include/plat/regs-fb.h |
8f995cc3 BD |
2 | * |
3 | * Copyright 2008 Openmoko, Inc. | |
4 | * Copyright 2008 Simtec Electronics | |
5 | * http://armlinux.simtec.co.uk/ | |
6 | * Ben Dooks <ben@simtec.co.uk> | |
7 | * | |
8 | * S3C Platform - new-style framebuffer register definitions | |
9 | * | |
10 | * This is the register set for the new style framebuffer interface | |
11 | * found from the S3C2443 onwards into the S3C2416, S3C2450 and the | |
12 | * S3C64XX series such as the S3C6400 and S3C6410. | |
13 | * | |
14 | * The file does not contain the cpu specific items which are based on | |
15 | * whichever architecture is selected, it only contains the core of the | |
16 | * register set. See <mach/regs-fb.h> to get the specifics. | |
17 | * | |
18 | * Note, we changed to using regs-fb.h as it avoids any clashes with | |
19 | * the original regs-lcd.h so out of the way of regs-lcd.h as well as | |
20 | * indicating the newer block is much more than just an LCD interface. | |
21 | * | |
22 | * This program is free software; you can redistribute it and/or modify | |
23 | * it under the terms of the GNU General Public License version 2 as | |
24 | * published by the Free Software Foundation. | |
25 | */ | |
26 | ||
27 | /* Please do not include this file directly, use <mach/regs-fb.h> to | |
28 | * ensure all the localised SoC support is included as necessary. | |
29 | */ | |
30 | ||
31 | /* VIDCON0 */ | |
32 | ||
33 | #define VIDCON0 (0x00) | |
34 | #define VIDCON0_INTERLACE (1 << 29) | |
35 | #define VIDCON0_VIDOUT_MASK (0x3 << 26) | |
36 | #define VIDCON0_VIDOUT_SHIFT (26) | |
37 | #define VIDCON0_VIDOUT_RGB (0x0 << 26) | |
38 | #define VIDCON0_VIDOUT_TV (0x1 << 26) | |
39 | #define VIDCON0_VIDOUT_I80_LDI0 (0x2 << 26) | |
40 | #define VIDCON0_VIDOUT_I80_LDI1 (0x3 << 26) | |
41 | ||
42 | #define VIDCON0_L1_DATA_MASK (0x7 << 23) | |
43 | #define VIDCON0_L1_DATA_SHIFT (23) | |
44 | #define VIDCON0_L1_DATA_16BPP (0x0 << 23) | |
45 | #define VIDCON0_L1_DATA_18BPP16 (0x1 << 23) | |
46 | #define VIDCON0_L1_DATA_18BPP9 (0x2 << 23) | |
47 | #define VIDCON0_L1_DATA_24BPP (0x3 << 23) | |
48 | #define VIDCON0_L1_DATA_18BPP (0x4 << 23) | |
49 | #define VIDCON0_L1_DATA_16BPP8 (0x5 << 23) | |
50 | ||
51 | #define VIDCON0_L0_DATA_MASK (0x7 << 20) | |
52 | #define VIDCON0_L0_DATA_SHIFT (20) | |
53 | #define VIDCON0_L0_DATA_16BPP (0x0 << 20) | |
54 | #define VIDCON0_L0_DATA_18BPP16 (0x1 << 20) | |
55 | #define VIDCON0_L0_DATA_18BPP9 (0x2 << 20) | |
56 | #define VIDCON0_L0_DATA_24BPP (0x3 << 20) | |
57 | #define VIDCON0_L0_DATA_18BPP (0x4 << 20) | |
58 | #define VIDCON0_L0_DATA_16BPP8 (0x5 << 20) | |
59 | ||
60 | #define VIDCON0_PNRMODE_MASK (0x3 << 17) | |
61 | #define VIDCON0_PNRMODE_SHIFT (17) | |
62 | #define VIDCON0_PNRMODE_RGB (0x0 << 17) | |
63 | #define VIDCON0_PNRMODE_BGR (0x1 << 17) | |
64 | #define VIDCON0_PNRMODE_SERIAL_RGB (0x2 << 17) | |
65 | #define VIDCON0_PNRMODE_SERIAL_BGR (0x3 << 17) | |
66 | ||
67 | #define VIDCON0_CLKVALUP (1 << 16) | |
68 | #define VIDCON0_CLKVAL_F_MASK (0xff << 6) | |
69 | #define VIDCON0_CLKVAL_F_SHIFT (6) | |
70 | #define VIDCON0_CLKVAL_F_LIMIT (0xff) | |
71 | #define VIDCON0_CLKVAL_F(_x) ((_x) << 6) | |
72 | #define VIDCON0_VLCKFREE (1 << 5) | |
73 | #define VIDCON0_CLKDIR (1 << 4) | |
74 | ||
75 | #define VIDCON0_CLKSEL_MASK (0x3 << 2) | |
76 | #define VIDCON0_CLKSEL_SHIFT (2) | |
77 | #define VIDCON0_CLKSEL_HCLK (0x0 << 2) | |
78 | #define VIDCON0_CLKSEL_LCD (0x1 << 2) | |
79 | #define VIDCON0_CLKSEL_27M (0x3 << 2) | |
80 | ||
81 | #define VIDCON0_ENVID (1 << 1) | |
82 | #define VIDCON0_ENVID_F (1 << 0) | |
83 | ||
84 | #define VIDCON1 (0x04) | |
85 | #define VIDCON1_LINECNT_MASK (0x7ff << 16) | |
86 | #define VIDCON1_LINECNT_SHIFT (16) | |
87 | #define VIDCON1_LINECNT_GET(_v) (((_v) >> 16) & 0x7ff) | |
88 | #define VIDCON1_VSTATUS_MASK (0x3 << 13) | |
89 | #define VIDCON1_VSTATUS_SHIFT (13) | |
90 | #define VIDCON1_VSTATUS_VSYNC (0x0 << 13) | |
91 | #define VIDCON1_VSTATUS_BACKPORCH (0x1 << 13) | |
92 | #define VIDCON1_VSTATUS_ACTIVE (0x2 << 13) | |
93 | #define VIDCON1_VSTATUS_FRONTPORCH (0x0 << 13) | |
94 | ||
95 | #define VIDCON1_INV_VCLK (1 << 7) | |
96 | #define VIDCON1_INV_HSYNC (1 << 6) | |
97 | #define VIDCON1_INV_VSYNC (1 << 5) | |
98 | #define VIDCON1_INV_VDEN (1 << 4) | |
99 | ||
100 | /* VIDCON2 */ | |
101 | ||
102 | #define VIDCON2 (0x08) | |
103 | #define VIDCON2_EN601 (1 << 23) | |
104 | #define VIDCON2_TVFMTSEL_SW (1 << 14) | |
105 | ||
106 | #define VIDCON2_TVFMTSEL1_MASK (0x3 << 12) | |
107 | #define VIDCON2_TVFMTSEL1_SHIFT (12) | |
108 | #define VIDCON2_TVFMTSEL1_RGB (0x0 << 12) | |
109 | #define VIDCON2_TVFMTSEL1_YUV422 (0x1 << 12) | |
110 | #define VIDCON2_TVFMTSEL1_YUV444 (0x2 << 12) | |
111 | ||
112 | #define VIDCON2_ORGYCbCr (1 << 8) | |
113 | #define VIDCON2_YUVORDCrCb (1 << 7) | |
114 | ||
067b226b PO |
115 | /* PRTCON (S3C6410, S5PC100) |
116 | * Might not be present in the S3C6410 documentation, | |
117 | * but tests prove it's there almost for sure; shouldn't hurt in any case. | |
118 | */ | |
119 | #define PRTCON (0x0c) | |
120 | #define PRTCON_PROTECT (1 << 11) | |
121 | ||
8f995cc3 BD |
122 | /* VIDTCON0 */ |
123 | ||
124 | #define VIDTCON0_VBPDE_MASK (0xff << 24) | |
125 | #define VIDTCON0_VBPDE_SHIFT (24) | |
126 | #define VIDTCON0_VBPDE_LIMIT (0xff) | |
127 | #define VIDTCON0_VBPDE(_x) ((_x) << 24) | |
128 | ||
129 | #define VIDTCON0_VBPD_MASK (0xff << 16) | |
130 | #define VIDTCON0_VBPD_SHIFT (16) | |
131 | #define VIDTCON0_VBPD_LIMIT (0xff) | |
132 | #define VIDTCON0_VBPD(_x) ((_x) << 16) | |
133 | ||
134 | #define VIDTCON0_VFPD_MASK (0xff << 8) | |
135 | #define VIDTCON0_VFPD_SHIFT (8) | |
136 | #define VIDTCON0_VFPD_LIMIT (0xff) | |
137 | #define VIDTCON0_VFPD(_x) ((_x) << 8) | |
138 | ||
139 | #define VIDTCON0_VSPW_MASK (0xff << 0) | |
140 | #define VIDTCON0_VSPW_SHIFT (0) | |
141 | #define VIDTCON0_VSPW_LIMIT (0xff) | |
142 | #define VIDTCON0_VSPW(_x) ((_x) << 0) | |
143 | ||
144 | /* VIDTCON1 */ | |
145 | ||
146 | #define VIDTCON1_VFPDE_MASK (0xff << 24) | |
147 | #define VIDTCON1_VFPDE_SHIFT (24) | |
148 | #define VIDTCON1_VFPDE_LIMIT (0xff) | |
149 | #define VIDTCON1_VFPDE(_x) ((_x) << 24) | |
150 | ||
151 | #define VIDTCON1_HBPD_MASK (0xff << 16) | |
152 | #define VIDTCON1_HBPD_SHIFT (16) | |
153 | #define VIDTCON1_HBPD_LIMIT (0xff) | |
154 | #define VIDTCON1_HBPD(_x) ((_x) << 16) | |
155 | ||
156 | #define VIDTCON1_HFPD_MASK (0xff << 8) | |
157 | #define VIDTCON1_HFPD_SHIFT (8) | |
158 | #define VIDTCON1_HFPD_LIMIT (0xff) | |
159 | #define VIDTCON1_HFPD(_x) ((_x) << 8) | |
160 | ||
161 | #define VIDTCON1_HSPW_MASK (0xff << 0) | |
162 | #define VIDTCON1_HSPW_SHIFT (0) | |
163 | #define VIDTCON1_HSPW_LIMIT (0xff) | |
164 | #define VIDTCON1_HSPW(_x) ((_x) << 0) | |
165 | ||
166 | #define VIDTCON2 (0x18) | |
167 | #define VIDTCON2_LINEVAL_MASK (0x7ff << 11) | |
168 | #define VIDTCON2_LINEVAL_SHIFT (11) | |
169 | #define VIDTCON2_LINEVAL_LIMIT (0x7ff) | |
170 | #define VIDTCON2_LINEVAL(_x) ((_x) << 11) | |
171 | ||
172 | #define VIDTCON2_HOZVAL_MASK (0x7ff << 0) | |
173 | #define VIDTCON2_HOZVAL_SHIFT (0) | |
174 | #define VIDTCON2_HOZVAL_LIMIT (0x7ff) | |
175 | #define VIDTCON2_HOZVAL(_x) ((_x) << 0) | |
176 | ||
177 | /* WINCONx */ | |
178 | ||
179 | ||
180 | #define WINCONx_BITSWP (1 << 18) | |
181 | #define WINCONx_BYTSWP (1 << 17) | |
182 | #define WINCONx_HAWSWP (1 << 16) | |
dc8498c0 | 183 | #define WINCONx_WSWP (1 << 15) |
8f995cc3 BD |
184 | #define WINCONx_BURSTLEN_MASK (0x3 << 9) |
185 | #define WINCONx_BURSTLEN_SHIFT (9) | |
186 | #define WINCONx_BURSTLEN_16WORD (0x0 << 9) | |
187 | #define WINCONx_BURSTLEN_8WORD (0x1 << 9) | |
188 | #define WINCONx_BURSTLEN_4WORD (0x2 << 9) | |
189 | ||
190 | #define WINCONx_ENWIN (1 << 0) | |
191 | #define WINCON0_BPPMODE_MASK (0xf << 2) | |
192 | #define WINCON0_BPPMODE_SHIFT (2) | |
193 | #define WINCON0_BPPMODE_1BPP (0x0 << 2) | |
194 | #define WINCON0_BPPMODE_2BPP (0x1 << 2) | |
195 | #define WINCON0_BPPMODE_4BPP (0x2 << 2) | |
196 | #define WINCON0_BPPMODE_8BPP_PALETTE (0x3 << 2) | |
197 | #define WINCON0_BPPMODE_16BPP_565 (0x5 << 2) | |
198 | #define WINCON0_BPPMODE_16BPP_1555 (0x7 << 2) | |
199 | #define WINCON0_BPPMODE_18BPP_666 (0x8 << 2) | |
200 | #define WINCON0_BPPMODE_24BPP_888 (0xb << 2) | |
201 | ||
202 | #define WINCON1_BLD_PIX (1 << 6) | |
203 | ||
204 | #define WINCON1_ALPHA_SEL (1 << 1) | |
205 | #define WINCON1_BPPMODE_MASK (0xf << 2) | |
206 | #define WINCON1_BPPMODE_SHIFT (2) | |
207 | #define WINCON1_BPPMODE_1BPP (0x0 << 2) | |
208 | #define WINCON1_BPPMODE_2BPP (0x1 << 2) | |
209 | #define WINCON1_BPPMODE_4BPP (0x2 << 2) | |
210 | #define WINCON1_BPPMODE_8BPP_PALETTE (0x3 << 2) | |
211 | #define WINCON1_BPPMODE_8BPP_1232 (0x4 << 2) | |
212 | #define WINCON1_BPPMODE_16BPP_565 (0x5 << 2) | |
213 | #define WINCON1_BPPMODE_16BPP_A1555 (0x6 << 2) | |
214 | #define WINCON1_BPPMODE_16BPP_I1555 (0x7 << 2) | |
215 | #define WINCON1_BPPMODE_18BPP_666 (0x8 << 2) | |
216 | #define WINCON1_BPPMODE_18BPP_A1665 (0x9 << 2) | |
217 | #define WINCON1_BPPMODE_19BPP_A1666 (0xa << 2) | |
218 | #define WINCON1_BPPMODE_24BPP_888 (0xb << 2) | |
219 | #define WINCON1_BPPMODE_24BPP_A1887 (0xc << 2) | |
220 | #define WINCON1_BPPMODE_25BPP_A1888 (0xd << 2) | |
221 | #define WINCON1_BPPMODE_28BPP_A4888 (0xd << 2) | |
222 | ||
223 | ||
224 | #define VIDOSDxA_TOPLEFT_X_MASK (0x7ff << 11) | |
225 | #define VIDOSDxA_TOPLEFT_X_SHIFT (11) | |
226 | #define VIDOSDxA_TOPLEFT_X_LIMIT (0x7ff) | |
227 | #define VIDOSDxA_TOPLEFT_X(_x) ((_x) << 11) | |
228 | ||
229 | #define VIDOSDxA_TOPLEFT_Y_MASK (0x7ff << 0) | |
230 | #define VIDOSDxA_TOPLEFT_Y_SHIFT (0) | |
231 | #define VIDOSDxA_TOPLEFT_Y_LIMIT (0x7ff) | |
232 | #define VIDOSDxA_TOPLEFT_Y(_x) ((_x) << 0) | |
233 | ||
234 | #define VIDOSDxB_BOTRIGHT_X_MASK (0x7ff << 11) | |
235 | #define VIDOSDxB_BOTRIGHT_X_SHIFT (11) | |
236 | #define VIDOSDxB_BOTRIGHT_X_LIMIT (0x7ff) | |
237 | #define VIDOSDxB_BOTRIGHT_X(_x) ((_x) << 11) | |
238 | ||
239 | #define VIDOSDxB_BOTRIGHT_Y_MASK (0x7ff << 0) | |
240 | #define VIDOSDxB_BOTRIGHT_Y_SHIFT (0) | |
241 | #define VIDOSDxB_BOTRIGHT_Y_LIMIT (0x7ff) | |
242 | #define VIDOSDxB_BOTRIGHT_Y(_x) ((_x) << 0) | |
243 | ||
244 | /* For VIDOSD[1..4]C */ | |
245 | #define VIDISD14C_ALPHA0_R(_x) ((_x) << 20) | |
246 | #define VIDISD14C_ALPHA0_G_MASK (0xf << 16) | |
247 | #define VIDISD14C_ALPHA0_G_SHIFT (16) | |
248 | #define VIDISD14C_ALPHA0_G_LIMIT (0xf) | |
249 | #define VIDISD14C_ALPHA0_G(_x) ((_x) << 16) | |
250 | #define VIDISD14C_ALPHA0_B_MASK (0xf << 12) | |
251 | #define VIDISD14C_ALPHA0_B_SHIFT (12) | |
252 | #define VIDISD14C_ALPHA0_B_LIMIT (0xf) | |
253 | #define VIDISD14C_ALPHA0_B(_x) ((_x) << 12) | |
254 | #define VIDISD14C_ALPHA1_R_MASK (0xf << 8) | |
255 | #define VIDISD14C_ALPHA1_R_SHIFT (8) | |
256 | #define VIDISD14C_ALPHA1_R_LIMIT (0xf) | |
257 | #define VIDISD14C_ALPHA1_R(_x) ((_x) << 8) | |
258 | #define VIDISD14C_ALPHA1_G_MASK (0xf << 4) | |
259 | #define VIDISD14C_ALPHA1_G_SHIFT (4) | |
260 | #define VIDISD14C_ALPHA1_G_LIMIT (0xf) | |
261 | #define VIDISD14C_ALPHA1_G(_x) ((_x) << 4) | |
262 | #define VIDISD14C_ALPHA1_B_MASK (0xf << 0) | |
263 | #define VIDISD14C_ALPHA1_B_SHIFT (0) | |
264 | #define VIDISD14C_ALPHA1_B_LIMIT (0xf) | |
265 | #define VIDISD14C_ALPHA1_B(_x) ((_x) << 0) | |
266 | ||
267 | /* Video buffer addresses */ | |
268 | #define VIDW_BUF_START(_buff) (0xA0 + ((_buff) * 8)) | |
269 | #define VIDW_BUF_START1(_buff) (0xA4 + ((_buff) * 8)) | |
270 | #define VIDW_BUF_END(_buff) (0xD0 + ((_buff) * 8)) | |
271 | #define VIDW_BUF_END1(_buff) (0xD4 + ((_buff) * 8)) | |
272 | #define VIDW_BUF_SIZE(_buff) (0x100 + ((_buff) * 4)) | |
273 | ||
274 | #define VIDW_BUF_SIZE_OFFSET_MASK (0x1fff << 13) | |
275 | #define VIDW_BUF_SIZE_OFFSET_SHIFT (13) | |
276 | #define VIDW_BUF_SIZE_OFFSET_LIMIT (0x1fff) | |
277 | #define VIDW_BUF_SIZE_OFFSET(_x) ((_x) << 13) | |
278 | ||
279 | #define VIDW_BUF_SIZE_PAGEWIDTH_MASK (0x1fff << 0) | |
280 | #define VIDW_BUF_SIZE_PAGEWIDTH_SHIFT (0) | |
281 | #define VIDW_BUF_SIZE_PAGEWIDTH_LIMIT (0x1fff) | |
282 | #define VIDW_BUF_SIZE_PAGEWIDTH(_x) ((_x) << 0) | |
283 | ||
284 | /* Interrupt controls and status */ | |
285 | ||
286 | #define VIDINTCON0_FIFOINTERVAL_MASK (0x3f << 20) | |
287 | #define VIDINTCON0_FIFOINTERVAL_SHIFT (20) | |
288 | #define VIDINTCON0_FIFOINTERVAL_LIMIT (0x3f) | |
289 | #define VIDINTCON0_FIFOINTERVAL(_x) ((_x) << 20) | |
290 | ||
291 | #define VIDINTCON0_INT_SYSMAINCON (1 << 19) | |
292 | #define VIDINTCON0_INT_SYSSUBCON (1 << 18) | |
293 | #define VIDINTCON0_INT_I80IFDONE (1 << 17) | |
294 | ||
295 | #define VIDINTCON0_FRAMESEL0_MASK (0x3 << 15) | |
296 | #define VIDINTCON0_FRAMESEL0_SHIFT (15) | |
297 | #define VIDINTCON0_FRAMESEL0_BACKPORCH (0x0 << 15) | |
298 | #define VIDINTCON0_FRAMESEL0_VSYNC (0x1 << 15) | |
299 | #define VIDINTCON0_FRAMESEL0_ACTIVE (0x2 << 15) | |
300 | #define VIDINTCON0_FRAMESEL0_FRONTPORCH (0x3 << 15) | |
301 | ||
9fa424a4 | 302 | #define VIDINTCON0_FRAMESEL1 (1 << 13) |
efdc846d | 303 | #define VIDINTCON0_FRAMESEL1_MASK (0x3 << 13) |
9fa424a4 PO |
304 | #define VIDINTCON0_FRAMESEL1_NONE (0x0 << 13) |
305 | #define VIDINTCON0_FRAMESEL1_BACKPORCH (0x1 << 13) | |
306 | #define VIDINTCON0_FRAMESEL1_VSYNC (0x2 << 13) | |
307 | #define VIDINTCON0_FRAMESEL1_FRONTPORCH (0x3 << 13) | |
8f995cc3 BD |
308 | |
309 | #define VIDINTCON0_INT_FRAME (1 << 12) | |
310 | #define VIDINTCON0_FIFIOSEL_MASK (0x7f << 5) | |
311 | #define VIDINTCON0_FIFIOSEL_SHIFT (5) | |
312 | #define VIDINTCON0_FIFIOSEL_WINDOW0 (0x1 << 5) | |
313 | #define VIDINTCON0_FIFIOSEL_WINDOW1 (0x2 << 5) | |
314 | ||
315 | #define VIDINTCON0_FIFOLEVEL_MASK (0x7 << 2) | |
316 | #define VIDINTCON0_FIFOLEVEL_SHIFT (2) | |
317 | #define VIDINTCON0_FIFOLEVEL_TO25PC (0x0 << 2) | |
318 | #define VIDINTCON0_FIFOLEVEL_TO50PC (0x1 << 2) | |
319 | #define VIDINTCON0_FIFOLEVEL_TO75PC (0x2 << 2) | |
320 | #define VIDINTCON0_FIFOLEVEL_EMPTY (0x3 << 2) | |
321 | #define VIDINTCON0_FIFOLEVEL_FULL (0x4 << 2) | |
322 | ||
323 | #define VIDINTCON0_INT_FIFO_MASK (0x3 << 0) | |
324 | #define VIDINTCON0_INT_FIFO_SHIFT (0) | |
325 | #define VIDINTCON0_INT_ENABLE (1 << 0) | |
326 | ||
327 | #define VIDINTCON1 (0x134) | |
328 | #define VIDINTCON1_INT_I180 (1 << 2) | |
329 | #define VIDINTCON1_INT_FRAME (1 << 1) | |
330 | #define VIDINTCON1_INT_FIFO (1 << 0) | |
331 | ||
332 | /* Window colour-key control registers */ | |
c4bb6ffa BD |
333 | #define WKEYCON (0x140) /* 6410,V210 */ |
334 | ||
335 | #define WKEYCON0 (0x00) | |
336 | #define WKEYCON1 (0x04) | |
8f995cc3 BD |
337 | |
338 | #define WxKEYCON0_KEYBL_EN (1 << 26) | |
339 | #define WxKEYCON0_KEYEN_F (1 << 25) | |
340 | #define WxKEYCON0_DIRCON (1 << 24) | |
341 | #define WxKEYCON0_COMPKEY_MASK (0xffffff << 0) | |
342 | #define WxKEYCON0_COMPKEY_SHIFT (0) | |
343 | #define WxKEYCON0_COMPKEY_LIMIT (0xffffff) | |
344 | #define WxKEYCON0_COMPKEY(_x) ((_x) << 0) | |
345 | #define WxKEYCON1_COLVAL_MASK (0xffffff << 0) | |
346 | #define WxKEYCON1_COLVAL_SHIFT (0) | |
347 | #define WxKEYCON1_COLVAL_LIMIT (0xffffff) | |
348 | #define WxKEYCON1_COLVAL(_x) ((_x) << 0) | |
349 | ||
350 | ||
351 | /* Window blanking (MAP) */ | |
352 | ||
353 | #define WINxMAP_MAP (1 << 24) | |
354 | #define WINxMAP_MAP_COLOUR_MASK (0xffffff << 0) | |
355 | #define WINxMAP_MAP_COLOUR_SHIFT (0) | |
356 | #define WINxMAP_MAP_COLOUR_LIMIT (0xffffff) | |
357 | #define WINxMAP_MAP_COLOUR(_x) ((_x) << 0) | |
358 | ||
359 | #define WPALCON_PAL_UPDATE (1 << 9) | |
360 | #define WPALCON_W1PAL_MASK (0x7 << 3) | |
361 | #define WPALCON_W1PAL_SHIFT (3) | |
362 | #define WPALCON_W1PAL_25BPP_A888 (0x0 << 3) | |
363 | #define WPALCON_W1PAL_24BPP (0x1 << 3) | |
364 | #define WPALCON_W1PAL_19BPP_A666 (0x2 << 3) | |
365 | #define WPALCON_W1PAL_18BPP_A665 (0x3 << 3) | |
366 | #define WPALCON_W1PAL_18BPP (0x4 << 3) | |
367 | #define WPALCON_W1PAL_16BPP_A555 (0x5 << 3) | |
368 | #define WPALCON_W1PAL_16BPP_565 (0x6 << 3) | |
369 | ||
370 | #define WPALCON_W0PAL_MASK (0x7 << 0) | |
371 | #define WPALCON_W0PAL_SHIFT (0) | |
372 | #define WPALCON_W0PAL_25BPP_A888 (0x0 << 0) | |
373 | #define WPALCON_W0PAL_24BPP (0x1 << 0) | |
374 | #define WPALCON_W0PAL_19BPP_A666 (0x2 << 0) | |
375 | #define WPALCON_W0PAL_18BPP_A665 (0x3 << 0) | |
376 | #define WPALCON_W0PAL_18BPP (0x4 << 0) | |
377 | #define WPALCON_W0PAL_16BPP_A555 (0x5 << 0) | |
378 | #define WPALCON_W0PAL_16BPP_565 (0x6 << 0) | |
379 |