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1 | /* arch/arm/plat-samsung/irq-uart.c |
2 | * originally part of arch/arm/plat-s3c64xx/irq.c | |
3 | * | |
4 | * Copyright 2008 Openmoko, Inc. | |
5 | * Copyright 2008 Simtec Electronics | |
6 | * Ben Dooks <ben@simtec.co.uk> | |
7 | * http://armlinux.simtec.co.uk/ | |
8 | * | |
9 | * Samsung- UART Interrupt handling | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License version 2 as | |
13 | * published by the Free Software Foundation. | |
14 | */ | |
15 | ||
16 | #include <linux/kernel.h> | |
17 | #include <linux/interrupt.h> | |
18 | #include <linux/serial_core.h> | |
19 | #include <linux/irq.h> | |
20 | #include <linux/io.h> | |
21 | ||
22 | #include <mach/map.h> | |
23 | #include <plat/irq-uart.h> | |
24 | #include <plat/regs-serial.h> | |
25 | #include <plat/cpu.h> | |
26 | ||
27 | /* Note, we make use of the fact that the parent IRQs, IRQ_UART[0..3] | |
28 | * are consecutive when looking up the interrupt in the demux routines. | |
29 | */ | |
30 | ||
27b31e56 | 31 | static inline void __iomem *s3c_irq_uart_base(struct irq_data *data) |
51022cf6 | 32 | { |
04ea1cc8 | 33 | struct s3c_uart_irq *uirq = irq_data_get_irq_chip_data(data); |
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34 | return uirq->regs; |
35 | } | |
36 | ||
37 | static inline unsigned int s3c_irq_uart_bit(unsigned int irq) | |
38 | { | |
39 | return irq & 3; | |
40 | } | |
41 | ||
27b31e56 | 42 | static void s3c_irq_uart_mask(struct irq_data *data) |
51022cf6 | 43 | { |
27b31e56 MB |
44 | void __iomem *regs = s3c_irq_uart_base(data); |
45 | unsigned int bit = s3c_irq_uart_bit(data->irq); | |
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46 | u32 reg; |
47 | ||
48 | reg = __raw_readl(regs + S3C64XX_UINTM); | |
49 | reg |= (1 << bit); | |
50 | __raw_writel(reg, regs + S3C64XX_UINTM); | |
51 | } | |
52 | ||
27b31e56 | 53 | static void s3c_irq_uart_maskack(struct irq_data *data) |
51022cf6 | 54 | { |
27b31e56 MB |
55 | void __iomem *regs = s3c_irq_uart_base(data); |
56 | unsigned int bit = s3c_irq_uart_bit(data->irq); | |
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57 | u32 reg; |
58 | ||
59 | reg = __raw_readl(regs + S3C64XX_UINTM); | |
60 | reg |= (1 << bit); | |
61 | __raw_writel(reg, regs + S3C64XX_UINTM); | |
62 | __raw_writel(1 << bit, regs + S3C64XX_UINTP); | |
63 | } | |
64 | ||
27b31e56 | 65 | static void s3c_irq_uart_unmask(struct irq_data *data) |
51022cf6 | 66 | { |
27b31e56 MB |
67 | void __iomem *regs = s3c_irq_uart_base(data); |
68 | unsigned int bit = s3c_irq_uart_bit(data->irq); | |
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69 | u32 reg; |
70 | ||
71 | reg = __raw_readl(regs + S3C64XX_UINTM); | |
72 | reg &= ~(1 << bit); | |
73 | __raw_writel(reg, regs + S3C64XX_UINTM); | |
74 | } | |
75 | ||
27b31e56 | 76 | static void s3c_irq_uart_ack(struct irq_data *data) |
51022cf6 | 77 | { |
27b31e56 MB |
78 | void __iomem *regs = s3c_irq_uart_base(data); |
79 | unsigned int bit = s3c_irq_uart_bit(data->irq); | |
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80 | |
81 | __raw_writel(1 << bit, regs + S3C64XX_UINTP); | |
82 | } | |
83 | ||
84 | static void s3c_irq_demux_uart(unsigned int irq, struct irq_desc *desc) | |
85 | { | |
04ea1cc8 | 86 | struct s3c_uart_irq *uirq = desc->irq_data.handler_data; |
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87 | u32 pend = __raw_readl(uirq->regs + S3C64XX_UINTP); |
88 | int base = uirq->base_irq; | |
89 | ||
90 | if (pend & (1 << 0)) | |
91 | generic_handle_irq(base); | |
92 | if (pend & (1 << 1)) | |
93 | generic_handle_irq(base + 1); | |
94 | if (pend & (1 << 2)) | |
95 | generic_handle_irq(base + 2); | |
96 | if (pend & (1 << 3)) | |
97 | generic_handle_irq(base + 3); | |
98 | } | |
99 | ||
100 | static struct irq_chip s3c_irq_uart = { | |
101 | .name = "s3c-uart", | |
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102 | .irq_mask = s3c_irq_uart_mask, |
103 | .irq_unmask = s3c_irq_uart_unmask, | |
104 | .irq_mask_ack = s3c_irq_uart_maskack, | |
105 | .irq_ack = s3c_irq_uart_ack, | |
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106 | }; |
107 | ||
108 | static void __init s3c_init_uart_irq(struct s3c_uart_irq *uirq) | |
109 | { | |
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110 | void __iomem *reg_base = uirq->regs; |
111 | unsigned int irq; | |
112 | int offs; | |
113 | ||
114 | /* mask all interrupts at the start. */ | |
115 | __raw_writel(0xf, reg_base + S3C64XX_UINTM); | |
116 | ||
117 | for (offs = 0; offs < 3; offs++) { | |
118 | irq = uirq->base_irq + offs; | |
119 | ||
6845664a TG |
120 | irq_set_chip(irq, &s3c_irq_uart); |
121 | irq_set_chip_data(irq, uirq); | |
122 | irq_set_handler(irq, handle_level_irq); | |
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123 | set_irq_flags(irq, IRQF_VALID); |
124 | } | |
125 | ||
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126 | irq_set_handler_data(uirq->parent_irq, uirq); |
127 | irq_set_chained_handler(uirq->parent_irq, s3c_irq_demux_uart); | |
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128 | } |
129 | ||
130 | /** | |
131 | * s3c_init_uart_irqs() - initialise UART IRQs and the necessary demuxing | |
132 | * @irq: The interrupt data for registering | |
133 | * @nr_irqs: The number of interrupt descriptions in @irq. | |
134 | * | |
135 | * Register the UART interrupts specified by @irq including the demuxing | |
136 | * routines. This supports the S3C6400 and newer style of devices. | |
137 | */ | |
138 | void __init s3c_init_uart_irqs(struct s3c_uart_irq *irq, unsigned int nr_irqs) | |
139 | { | |
140 | for (; nr_irqs > 0; nr_irqs--, irq++) | |
141 | s3c_init_uart_irq(irq); | |
142 | } |